Struct lpc55_pac::dma0::channel::xfercfg::R

pub struct R(_);

Register XFERCFG reader

Implementations

impl R

pub fn cfgvalid(&self) -> CFGVALID_R

Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.

pub fn reload(&self) -> RELOAD_R

Bit 1 - Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.

pub fn swtrig(&self) -> SWTRIG_R

Bit 2 - Software Trigger.

pub fn clrtrig(&self) -> CLRTRIG_R

Bit 3 - Clear Trigger.

pub fn setinta(&self) -> SETINTA_R

Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.

pub fn setintb(&self) -> SETINTB_R

Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.

pub fn width(&self) -> WIDTH_R

Bits 8:9 - Transfer width used for this DMA channel.

pub fn srcinc(&self) -> SRCINC_R

Bits 12:13 - Determines whether the source address is incremented for each DMA transfer.

pub fn dstinc(&self) -> DSTINC_R

Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer.

pub fn xfercount(&self) -> XFERCOUNT_R

Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.

Methods from Deref<Target = R<XFERCFG_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<XFERCFG_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<XFERCFG_SPEC>> for R

fn from(reader: R<XFERCFG_SPEC>) -> Self

Performs the conversion.