Struct lpc55_pac::ahb_secure_ctrl::sec_ctrl_ahb_port8_slave1_rule::W [−][src]
pub struct W(_);
Register SEC_CTRL_AHB_PORT8_SLAVE1_RULE
writer
Implementations
impl W
[src]
impl W
[src]pub fn flexcomm2_rule(&mut self) -> FLEXCOMM2_RULE_W<'_>
[src]
Bits 0:1 - Flexcomm interface 2
pub fn flexcomm3_rule(&mut self) -> FLEXCOMM3_RULE_W<'_>
[src]
Bits 4:5 - Flexcomm interface 3
pub fn flexcomm4_rule(&mut self) -> FLEXCOMM4_RULE_W<'_>
[src]
Bits 8:9 - Flexcomm interface 4
pub fn mailbox_rule(&mut self) -> MAILBOX_RULE_W<'_>
[src]
Bits 12:13 - Inter CPU communication Mailbox
pub fn gpio0_rule(&mut self) -> GPIO0_RULE_W<'_>
[src]
Bits 16:17 - High Speed GPIO
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
[src]
Writes raw bits to the register.
Methods from Deref<Target = W<SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>>
Trait Implementations
impl From<W<SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>> for W
[src]
impl From<W<SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>> for W
[src]