Struct lpc55_pac::i2s0::RegisterBlock [−][src]
Register block
Fields
cfg1: CFG1
0xc00 - Configuration register 1 for the primary channel pair.
cfg2: CFG2
0xc04 - Configuration register 2 for the primary channel pair.
stat: STAT
0xc08 - Status register for the primary channel pair.
div: DIV
0xc1c - Clock divider, used by all channel pairs.
fifocfg: FIFOCFG
0xe00 - FIFO configuration and enable register.
fifostat: FIFOSTAT
0xe04 - FIFO status register.
fifotrig: FIFOTRIG
0xe08 - FIFO trigger settings for interrupt and DMA request.
fifointenset: FIFOINTENSET
0xe10 - FIFO interrupt enable set (enable) and read register.
fifointenclr: FIFOINTENCLR
0xe14 - FIFO interrupt enable clear (disable) and read register.
fifointstat: FIFOINTSTAT
0xe18 - FIFO interrupt status register.
fifowr: FIFOWR
0xe20 - FIFO write data.
fifowr48h: FIFOWR48H
0xe24 - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fiford: FIFORD
0xe30 - FIFO read data.
fiford48h: FIFORD48H
0xe34 - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fifordnopop: FIFORDNOPOP
0xe40 - FIFO data read with no FIFO pop.
fiford48hnopop: FIFORD48HNOPOP
0xe44 - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
id: ID
0xffc - I2S Module identification
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