[−][src]Type Definition lpc55_pac::syscon::pll1stat::R
type R = R<u32, PLL1STAT>;
Reader of register PLL1STAT
Implementations
impl R[src]
pub fn lock(&self) -> LOCK_R[src]
Bit 0 - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
pub fn predivack(&self) -> PREDIVACK_R[src]
Bit 1 - pre-divider ratio change acknowledge.
pub fn feeddivack(&self) -> FEEDDIVACK_R[src]
Bit 2 - feedback divider ratio change acknowledge.
pub fn postdivack(&self) -> POSTDIVACK_R[src]
Bit 3 - post-divider ratio change acknowledge.
pub fn frmdet(&self) -> FRMDET_R[src]
Bit 4 - free running detector output (active high).