[−][src]Type Definition lpc55_pac::syscon::pll0clkdiv::W

type W = W<u32, PLL0CLKDIV>;

Writer for register PLL0CLKDIV

Implementations

`impl W`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.