[−][src]Struct lpc55_pac::inputmux::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub sct0_inmux: [SCT0_INMUX; 7],
    pub timer0captsel: [TIMER0CAPTSEL; 4],
    pub timer1captsel: [TIMER1CAPTSEL; 4],
    pub timer2captsel: [TIMER2CAPTSEL; 4],
    pub pintsel: [PINTSEL; 8],
    pub dma0_itrig_inmux: [DMA0_ITRIG_INMUX; 23],
    pub dma0_otrig_inmux: [DMA0_OTRIG_INMUX; 4],
    pub freqmeas_ref: FREQMEAS_REF,
    pub freqmeas_target: FREQMEAS_TARGET,
    pub timer3captsel: [TIMER3CAPTSEL; 4],
    pub timer4captsel: [TIMER4CAPTSEL; 4],
    pub pintsecsel: [PINTSECSEL; 2],
    pub dma1_itrig_inmux: [DMA1_ITRIG_INMUX; 10],
    pub dma1_otrig_inmux: [DMA1_OTRIG_INMUX; 4],
    pub dma0_req_ena: DMA0_REQ_ENA,
    pub dma0_req_ena_set: DMA0_REQ_ENA_SET,
    pub dma0_req_ena_clr: DMA0_REQ_ENA_CLR,
    pub dma1_req_ena: DMA1_REQ_ENA,
    pub dma1_req_ena_set: DMA1_REQ_ENA_SET,
    pub dma1_req_ena_clr: DMA1_REQ_ENA_CLR,
    pub dma0_itrig_ena: DMA0_ITRIG_ENA,
    pub dma0_itrig_ena_set: DMA0_ITRIG_ENA_SET,
    pub dma0_itrig_ena_clr: DMA0_ITRIG_ENA_CLR,
    pub dma1_itrig_ena: DMA1_ITRIG_ENA,
    pub dma1_itrig_ena_set: DMA1_ITRIG_ENA_SET,
    pub dma1_itrig_ena_clr: DMA1_ITRIG_ENA_CLR,
    // some fields omitted
}

Register block

Fields

sct0_inmux: [SCT0_INMUX; 7]

0x00 - Input mux register for SCT0 input

timer0captsel: [TIMER0CAPTSEL; 4]

0x20 - Capture select registers for TIMER0 inputs

timer1captsel: [TIMER1CAPTSEL; 4]

0x40 - Capture select registers for TIMER1 inputs

timer2captsel: [TIMER2CAPTSEL; 4]

0x60 - Capture select registers for TIMER2 inputs

pintsel: [PINTSEL; 8]

0xc0 - Pin interrupt select register

dma0_itrig_inmux: [DMA0_ITRIG_INMUX; 23]

0xe0 - Trigger select register for DMA0 channel

dma0_otrig_inmux: [DMA0_OTRIG_INMUX; 4]

0x160 - DMA0 output trigger selection to become DMA0 trigger

freqmeas_ref: FREQMEAS_REF

0x180 - Selection for frequency measurement reference clock

freqmeas_target: FREQMEAS_TARGET

0x184 - Selection for frequency measurement target clock

timer3captsel: [TIMER3CAPTSEL; 4]

0x1a0 - Capture select registers for TIMER3 inputs

timer4captsel: [TIMER4CAPTSEL; 4]

0x1c0 - Capture select registers for TIMER4 inputs

pintsecsel: [PINTSECSEL; 2]

0x1e0 - Pin interrupt secure select register

dma1_itrig_inmux: [DMA1_ITRIG_INMUX; 10]

0x200 - Trigger select register for DMA1 channel

dma1_otrig_inmux: [DMA1_OTRIG_INMUX; 4]

0x240 - DMA1 output trigger selection to become DMA1 trigger

dma0_req_ena: DMA0_REQ_ENA

0x740 - Enable DMA0 requests

dma0_req_ena_set: DMA0_REQ_ENA_SET

0x748 - Set one or several bits in DMA0_REQ_ENA register

dma0_req_ena_clr: DMA0_REQ_ENA_CLR

0x750 - Clear one or several bits in DMA0_REQ_ENA register

dma1_req_ena: DMA1_REQ_ENA

0x760 - Enable DMA1 requests

dma1_req_ena_set: DMA1_REQ_ENA_SET

0x768 - Set one or several bits in DMA1_REQ_ENA register

dma1_req_ena_clr: DMA1_REQ_ENA_CLR

0x770 - Clear one or several bits in DMA1_REQ_ENA register

dma0_itrig_ena: DMA0_ITRIG_ENA

0x780 - Enable DMA0 triggers

dma0_itrig_ena_set: DMA0_ITRIG_ENA_SET

0x788 - Set one or several bits in DMA0_ITRIG_ENA register

dma0_itrig_ena_clr: DMA0_ITRIG_ENA_CLR

0x790 - Clear one or several bits in DMA0_ITRIG_ENA register

dma1_itrig_ena: DMA1_ITRIG_ENA

0x7a0 - Enable DMA1 triggers

dma1_itrig_ena_set: DMA1_ITRIG_ENA_SET

0x7a8 - Set one or several bits in DMA1_ITRIG_ENA register

dma1_itrig_ena_clr: DMA1_ITRIG_ENA_CLR

0x7b0 - Clear one or several bits in DMA1_ITRIG_ENA register

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