[−][src]Type Definition lpc55_pac::dma0::intenset0::W

type W = W<u32, INTENSET0>;

Writer for register INTENSET0

Implementations

`impl W`[src]

`pub fn inten(&mut self) -> INTEN_W<'_>`[src]

Bits 0:31 - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.

[−][src]Type Definition lpc55_pac::dma0::intenset0::W

Implementations

impl W[src]

pub fn inten(&mut self) -> INTEN_W<'_>[src]

`impl W`[src]

`pub fn inten(&mut self) -> INTEN_W<'_>`[src]