[][src]Type Definition lpc55_pac::ahb_secure_ctrl::sec_ctrl_apb_bridge0_mem_ctrl0::W

type W = W<u32, SEC_CTRL_APB_BRIDGE0_MEM_CTRL0>;

Writer for register SEC_CTRL_APB_BRIDGE0_MEM_CTRL0

Implementations

impl W[src]

pub fn syscon_rule(&mut self) -> SYSCON_RULE_W<'_>[src]

Bits 0:1 - System Configuration

pub fn iocon_rule(&mut self) -> IOCON_RULE_W<'_>[src]

Bits 4:5 - I/O Configuration

pub fn gint0_rule(&mut self) -> GINT0_RULE_W<'_>[src]

Bits 8:9 - GPIO input Interrupt 0

pub fn gint1_rule(&mut self) -> GINT1_RULE_W<'_>[src]

Bits 12:13 - GPIO input Interrupt 1

pub fn pint_rule(&mut self) -> PINT_RULE_W<'_>[src]

Bits 16:17 - Pin Interrupt and Pattern match

pub fn sec_pint_rule(&mut self) -> SEC_PINT_RULE_W<'_>[src]

Bits 20:21 - Secure Pin Interrupt and Pattern match

pub fn inputmux_rule(&mut self) -> INPUTMUX_RULE_W<'_>[src]

Bits 24:25 - Peripheral input multiplexing