[−][src]Struct lpc55_pac::adc0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub verid: VERID,
    pub param: PARAM,
    pub ctrl: CTRL,
    pub stat: STAT,
    pub ie: IE,
    pub de: DE,
    pub cfg: CFG,
    pub pause: PAUSE,
    pub swtrig: SWTRIG,
    pub tstat: TSTAT,
    pub ofstrim: OFSTRIM,
    pub tctrl: [TCTRL; 16],
    pub fctrl: [FCTRL; 2],
    pub gcc: [GCC; 2],
    pub gcr: [GCR; 2],
    pub cmdl1: CMDL1,
    pub cmdh1: CMDH1,
    pub cmdl2: CMDL2,
    pub cmdh2: CMDH2,
    pub cmdl3: CMDL3,
    pub cmdh3: CMDH3,
    pub cmdl4: CMDL4,
    pub cmdh4: CMDH4,
    pub cmdl5: CMDL5,
    pub cmdh5: CMDH5,
    pub cmdl6: CMDL6,
    pub cmdh6: CMDH6,
    pub cmdl7: CMDL7,
    pub cmdh7: CMDH7,
    pub cmdl8: CMDL8,
    pub cmdh8: CMDH8,
    pub cmdl9: CMDL9,
    pub cmdh9: CMDH9,
    pub cmdl10: CMDL10,
    pub cmdh10: CMDH10,
    pub cmdl11: CMDL11,
    pub cmdh11: CMDH11,
    pub cmdl12: CMDL12,
    pub cmdh12: CMDH12,
    pub cmdl13: CMDL13,
    pub cmdh13: CMDH13,
    pub cmdl14: CMDL14,
    pub cmdh14: CMDH14,
    pub cmdl15: CMDL15,
    pub cmdh15: CMDH15,
    pub cv1: CV,
    pub cv2: CV,
    pub cv3: CV,
    pub cv4: CV,
    pub resfifo: [RESFIFO; 2],
    pub cal_gar: [CAL_GAR; 33],
    pub cal_gbr: [CAL_GBR; 33],
    pub tst: TST,
    // some fields omitted
}

Register block

Fields

verid: VERID

0x00 - Version ID Register

param: PARAM

0x04 - Parameter Register

ctrl: CTRL

0x10 - ADC Control Register

stat: STAT

0x14 - ADC Status Register

ie: IE

0x18 - Interrupt Enable Register

de: DE

0x1c - DMA Enable Register

cfg: CFG

0x20 - ADC Configuration Register

pause: PAUSE

0x24 - ADC Pause Register

swtrig: SWTRIG

0x34 - Software Trigger Register

tstat: TSTAT

0x38 - Trigger Status Register

ofstrim: OFSTRIM

0x40 - ADC Offset Trim Register

tctrl: [TCTRL; 16]

0xa0 - Trigger Control Register

fctrl: [FCTRL; 2]

0xe0 - FIFO Control Register

gcc: [GCC; 2]

0xf0 - Gain Calibration Control

gcr: [GCR; 2]

0xf8 - Gain Calculation Result

cmdl1: CMDL1

0x100 - ADC Command Low Buffer Register

cmdh1: CMDH1

0x104 - ADC Command High Buffer Register

cmdl2: CMDL2

0x108 - ADC Command Low Buffer Register

cmdh2: CMDH2

0x10c - ADC Command High Buffer Register

cmdl3: CMDL3

0x110 - ADC Command Low Buffer Register

cmdh3: CMDH3

0x114 - ADC Command High Buffer Register

cmdl4: CMDL4

0x118 - ADC Command Low Buffer Register

cmdh4: CMDH4

0x11c - ADC Command High Buffer Register

cmdl5: CMDL5

0x120 - ADC Command Low Buffer Register

cmdh5: CMDH5

0x124 - ADC Command High Buffer Register

cmdl6: CMDL6

0x128 - ADC Command Low Buffer Register

cmdh6: CMDH6

0x12c - ADC Command High Buffer Register

cmdl7: CMDL7

0x130 - ADC Command Low Buffer Register

cmdh7: CMDH7

0x134 - ADC Command High Buffer Register

cmdl8: CMDL8

0x138 - ADC Command Low Buffer Register

cmdh8: CMDH8

0x13c - ADC Command High Buffer Register

cmdl9: CMDL9

0x140 - ADC Command Low Buffer Register

cmdh9: CMDH9

0x144 - ADC Command High Buffer Register

cmdl10: CMDL10

0x148 - ADC Command Low Buffer Register

cmdh10: CMDH10

0x14c - ADC Command High Buffer Register

cmdl11: CMDL11

0x150 - ADC Command Low Buffer Register

cmdh11: CMDH11

0x154 - ADC Command High Buffer Register

cmdl12: CMDL12

0x158 - ADC Command Low Buffer Register

cmdh12: CMDH12

0x15c - ADC Command High Buffer Register

cmdl13: CMDL13

0x160 - ADC Command Low Buffer Register

cmdh13: CMDH13

0x164 - ADC Command High Buffer Register

cmdl14: CMDL14

0x168 - ADC Command Low Buffer Register

cmdh14: CMDH14

0x16c - ADC Command High Buffer Register

cmdl15: CMDL15

0x170 - ADC Command Low Buffer Register

cmdh15: CMDH15

0x174 - ADC Command High Buffer Register

cv1: CV

0x200 - Compare Value Register

cv2: CV

0x204 - Compare Value Register

cv3: CV

0x208 - Compare Value Register

cv4: CV

0x20c - Compare Value Register

resfifo: [RESFIFO; 2]

0x300 - ADC Data Result FIFO Register

cal_gar: [CAL_GAR; 33]

0x400 - Calibration General A-Side Registers

cal_gbr: [CAL_GBR; 33]

0x500 - Calibration General B-Side Registers

tst: TST

0xffc - ADC Test Register

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