1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 16usize],
5 #[doc = "0x10 - AHB multilayer matrix priority control"]
6 pub ahbmatprio: AHBMATPRIO,
7 _reserved1: [u8; 44usize],
8 #[doc = "0x40 - System tick counter calibration"]
9 pub systckcal: SYSTCKCAL,
10 _reserved2: [u8; 4usize],
11 #[doc = "0x48 - NMI Source Select"]
12 pub nmisrc: NMISRC,
13 #[doc = "0x4c - Asynchronous APB Control"]
14 pub asyncapbctrl: ASYNCAPBCTRL,
15 _reserved4: [u8; 112usize],
16 #[doc = "0xc0 - POR captured value of port n"]
17 pub pioporcap: [PIOPORCAP; 2],
18 _reserved5: [u8; 8usize],
19 #[doc = "0xd0 - Reset captured value of port n"]
20 pub piorescap: [PIORESCAP; 2],
21 _reserved6: [u8; 40usize],
22 #[doc = "0x100 - Peripheral reset control n"]
23 pub presetctrl0: PRESETCTRL0,
24 #[doc = "0x104 - Peripheral reset control n"]
25 pub presetctrl1: PRESETCTRL1,
26 #[doc = "0x108 - Peripheral reset control n"]
27 pub presetctrl2: PRESETCTRL2,
28 _reserved9: [u8; 20usize],
29 #[doc = "0x120 - Set bits in PRESETCTRLn"]
30 pub presetctrlset: [PRESETCTRLSET; 3],
31 _reserved10: [u8; 20usize],
32 #[doc = "0x140 - Clear bits in PRESETCTRLn"]
33 pub presetctrlclr: [PRESETCTRLCLR; 3],
34 _reserved11: [u8; 164usize],
35 #[doc = "0x1f0 - System reset status register"]
36 pub sysrststat: SYSRSTSTAT,
37 _reserved12: [u8; 12usize],
38 #[doc = "0x200 - AHB Clock control n"]
39 pub ahbclkctrl0: AHBCLKCTRL0,
40 #[doc = "0x204 - AHB Clock control n"]
41 pub ahbclkctrl1: AHBCLKCTRL1,
42 #[doc = "0x208 - AHB Clock control n"]
43 pub ahbclkctrl2: AHBCLKCTRL2,
44 _reserved15: [u8; 20usize],
45 #[doc = "0x220 - Set bits in AHBCLKCTRLn"]
46 pub ahbclkctrlset: [AHBCLKCTRLSET; 3],
47 _reserved16: [u8; 20usize],
48 #[doc = "0x240 - Clear bits in AHBCLKCTRLn"]
49 pub ahbclkctrlclr: [AHBCLKCTRLCLR; 3],
50 _reserved17: [u8; 52usize],
51 #[doc = "0x280 - Main clock source select A"]
52 pub mainclksela: MAINCLKSELA,
53 #[doc = "0x284 - Main clock source select B"]
54 pub mainclkselb: MAINCLKSELB,
55 #[doc = "0x288 - CLKOUT clock source select A"]
56 pub clkoutsela: CLKOUTSELA,
57 _reserved20: [u8; 4usize],
58 #[doc = "0x290 - PLL clock source select"]
59 pub syspllclksel: SYSPLLCLKSEL,
60 _reserved21: [u8; 4usize],
61 #[doc = "0x298 - Audio PLL clock source select"]
62 pub audpllclksel: AUDPLLCLKSEL,
63 _reserved22: [u8; 4usize],
64 #[doc = "0x2a0 - SPIFI clock source select"]
65 pub spificlksel: SPIFICLKSEL,
66 #[doc = "0x2a4 - ADC clock source select"]
67 pub adcclksel: ADCCLKSEL,
68 #[doc = "0x2a8 - USB0 clock source select"]
69 pub usb0clksel: USB0CLKSEL,
70 #[doc = "0x2ac - USB1 clock source select"]
71 pub usb1clksel: USB1CLKSEL,
72 #[doc = "0x2b0 - Flexcomm 0 clock source select"]
73 pub fclksel: [FCLKSEL; 10],
74 _reserved27: [u8; 8usize],
75 #[doc = "0x2e0 - MCLK clock source select"]
76 pub mclkclksel: MCLKCLKSEL,
77 _reserved28: [u8; 4usize],
78 #[doc = "0x2e8 - Fractional Rate Generator clock source select"]
79 pub frgclksel: FRGCLKSEL,
80 #[doc = "0x2ec - Digital microphone (DMIC) subsystem clock select"]
81 pub dmicclksel: DMICCLKSEL,
82 #[doc = "0x2f0 - SCTimer/PWM clock source select"]
83 pub sctclksel: SCTCLKSEL,
84 #[doc = "0x2f4 - LCD clock source select"]
85 pub lcdclksel: LCDCLKSEL,
86 #[doc = "0x2f8 - SDIO clock source select"]
87 pub sdioclksel: SDIOCLKSEL,
88 _reserved33: [u8; 4usize],
89 #[doc = "0x300 - SYSTICK clock divider"]
90 pub systickclkdiv: SYSTICKCLKDIV,
91 #[doc = "0x304 - ARM Trace clock divider"]
92 pub armtraceclkdiv: ARMTRACECLKDIV,
93 #[doc = "0x308 - MCAN0 clock divider"]
94 pub can0clkdiv: CAN0CLKDIV,
95 #[doc = "0x30c - MCAN1 clock divider"]
96 pub can1clkdiv: CAN1CLKDIV,
97 #[doc = "0x310 - Smartcard0 clock divider"]
98 pub sc0clkdiv: SC0CLKDIV,
99 #[doc = "0x314 - Smartcard1 clock divider"]
100 pub sc1clkdiv: SC1CLKDIV,
101 _reserved39: [u8; 104usize],
102 #[doc = "0x380 - AHB clock divider"]
103 pub ahbclkdiv: AHBCLKDIV,
104 #[doc = "0x384 - CLKOUT clock divider"]
105 pub clkoutdiv: CLKOUTDIV,
106 #[doc = "0x388 - FROHF clock divider"]
107 pub frohfclkdiv: FROHFCLKDIV,
108 _reserved42: [u8; 4usize],
109 #[doc = "0x390 - SPIFI clock divider"]
110 pub spificlkdiv: SPIFICLKDIV,
111 #[doc = "0x394 - ADC clock divider"]
112 pub adcclkdiv: ADCCLKDIV,
113 #[doc = "0x398 - USB0 clock divider"]
114 pub usb0clkdiv: USB0CLKDIV,
115 #[doc = "0x39c - USB1 clock divider"]
116 pub usb1clkdiv: USB1CLKDIV,
117 #[doc = "0x3a0 - Fractional rate divider"]
118 pub frgctrl: FRGCTRL,
119 _reserved47: [u8; 4usize],
120 #[doc = "0x3a8 - DMIC clock divider"]
121 pub dmicclkdiv: DMICCLKDIV,
122 #[doc = "0x3ac - I2S MCLK clock divider"]
123 pub mclkdiv: MCLKDIV,
124 #[doc = "0x3b0 - LCD clock divider"]
125 pub lcdclkdiv: LCDCLKDIV,
126 #[doc = "0x3b4 - SCT/PWM clock divider"]
127 pub sctclkdiv: SCTCLKDIV,
128 #[doc = "0x3b8 - EMC clock divider"]
129 pub emcclkdiv: EMCCLKDIV,
130 #[doc = "0x3bc - SDIO clock divider"]
131 pub sdioclkdiv: SDIOCLKDIV,
132 _reserved53: [u8; 64usize],
133 #[doc = "0x400 - Flash wait states configuration"]
134 pub flashcfg: FLASHCFG,
135 _reserved54: [u8; 8usize],
136 #[doc = "0x40c - USB0 clock control"]
137 pub usb0clkctrl: USB0CLKCTRL,
138 #[doc = "0x410 - USB0 clock status"]
139 pub usb0clkstat: USB0CLKSTAT,
140 _reserved56: [u8; 4usize],
141 #[doc = "0x418 - Frequency measure register"]
142 pub freqmectrl: FREQMECTRL,
143 _reserved57: [u8; 4usize],
144 #[doc = "0x420 - MCLK input/output control"]
145 pub mclkio: MCLKIO,
146 #[doc = "0x424 - USB1 clock control"]
147 pub usb1clkctrl: USB1CLKCTRL,
148 #[doc = "0x428 - USB1 clock status"]
149 pub usb1clkstat: USB1CLKSTAT,
150 _reserved60: [u8; 24usize],
151 #[doc = "0x444 - EMC system control"]
152 pub emcsysctrl: EMCSYSCTRL,
153 #[doc = "0x448 - EMC clock delay control"]
154 pub emcdlyctrl: EMCDLYCTRL,
155 #[doc = "0x44c - EMC delay chain calibration control"]
156 pub emcdlycal: EMCDLYCAL,
157 #[doc = "0x450 - Ethernet PHY Selection"]
158 pub ethphysel: ETHPHYSEL,
159 #[doc = "0x454 - Ethernet SBD flow control"]
160 pub ethsbdctrl: ETHSBDCTRL,
161 _reserved65: [u8; 8usize],
162 #[doc = "0x460 - SDIO CCLKIN phase and delay control"]
163 pub sdioclkctrl: SDIOCLKCTRL,
164 _reserved66: [u8; 156usize],
165 #[doc = "0x500 - FRO oscillator control"]
166 pub froctrl: FROCTRL,
167 #[doc = "0x504 - System oscillator control"]
168 pub sysoscctrl: SYSOSCCTRL,
169 #[doc = "0x508 - Watchdog oscillator control"]
170 pub wdtoscctrl: WDTOSCCTRL,
171 #[doc = "0x50c - RTC oscillator 32 kHz output control"]
172 pub rtcoscctrl: RTCOSCCTRL,
173 _reserved70: [u8; 12usize],
174 #[doc = "0x51c - USB PLL control"]
175 pub usbpllctrl: USBPLLCTRL,
176 #[doc = "0x520 - USB PLL status"]
177 pub usbpllstat: USBPLLSTAT,
178 _reserved72: [u8; 92usize],
179 #[doc = "0x580 - System PLL control"]
180 pub syspllctrl: SYSPLLCTRL,
181 #[doc = "0x584 - PLL status"]
182 pub syspllstat: SYSPLLSTAT,
183 #[doc = "0x588 - PLL N divider"]
184 pub syspllndec: SYSPLLNDEC,
185 #[doc = "0x58c - PLL P divider"]
186 pub syspllpdec: SYSPLLPDEC,
187 #[doc = "0x590 - System PLL M divider"]
188 pub syspllmdec: SYSPLLMDEC,
189 _reserved77: [u8; 12usize],
190 #[doc = "0x5a0 - Audio PLL control"]
191 pub audpllctrl: AUDPLLCTRL,
192 #[doc = "0x5a4 - Audio PLL status"]
193 pub audpllstat: AUDPLLSTAT,
194 #[doc = "0x5a8 - Audio PLL N divider"]
195 pub audpllndec: AUDPLLNDEC,
196 #[doc = "0x5ac - Audio PLL P divider"]
197 pub audpllpdec: AUDPLLPDEC,
198 #[doc = "0x5b0 - Audio PLL M divider"]
199 pub audpllmdec: AUDPLLMDEC,
200 #[doc = "0x5b4 - Audio PLL fractional divider control"]
201 pub audpllfrac: AUDPLLFRAC,
202 _reserved83: [u8; 72usize],
203 #[doc = "0x600 - Sleep configuration register"]
204 pub pdsleepcfg0: PDSLEEPCFG0,
205 #[doc = "0x604 - Sleep configuration register"]
206 pub pdsleepcfg1: PDSLEEPCFG1,
207 _reserved85: [u8; 8usize],
208 #[doc = "0x610 - Power configuration register"]
209 pub pdruncfg0: PDRUNCFG0,
210 #[doc = "0x614 - Power configuration register"]
211 pub pdruncfg1: PDRUNCFG1,
212 _reserved87: [u8; 8usize],
213 #[doc = "0x620 - Power configuration set register"]
214 pub pdruncfgset0: PDRUNCFGSET0,
215 #[doc = "0x624 - Power configuration set register"]
216 pub pdruncfgset1: PDRUNCFGSET1,
217 _reserved89: [u8; 8usize],
218 #[doc = "0x630 - Power configuration clear register"]
219 pub pdruncfgclr0: PDRUNCFGCLR0,
220 #[doc = "0x634 - Power configuration clear register"]
221 pub pdruncfgclr1: PDRUNCFGCLR1,
222 _reserved91: [u8; 72usize],
223 #[doc = "0x680 - Start logic 0 wake-up enable register"]
224 pub starter0: STARTER0,
225 #[doc = "0x684 - Start logic 0 wake-up enable register"]
226 pub starter1: STARTER1,
227 _reserved93: [u8; 24usize],
228 #[doc = "0x6a0 - Set bits in STARTER"]
229 pub starterset: [STARTERSET; 2],
230 _reserved94: [u8; 24usize],
231 #[doc = "0x6c0 - Clear bits in STARTER0"]
232 pub starterclr: [STARTERCLR; 2],
233 _reserved95: [u8; 184usize],
234 #[doc = "0x780 - Configures special cases of hardware wake-up"]
235 pub hwwake: HWWAKE,
236 _reserved96: [u8; 1664usize],
237 #[doc = "0xe04 - Auto Clock-Gate Override Register"]
238 pub autocgor: AUTOCGOR,
239 _reserved97: [u8; 492usize],
240 #[doc = "0xff4 - JTAG ID code register"]
241 pub jtagidcode: JTAGIDCODE,
242 #[doc = "0xff8 - Part ID register"]
243 pub device_id0: DEVICE_ID0,
244 #[doc = "0xffc - Boot ROM and die revision register"]
245 pub device_id1: DEVICE_ID1,
246 _reserved100: [u8; 127044usize],
247 #[doc = "0x20044 - Brown-Out Detect control"]
248 pub bodctrl: BODCTRL,
249}
250#[doc = "AHB multilayer matrix priority control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmatprio](ahbmatprio) module"]
251pub type AHBMATPRIO = crate::Reg<u32, _AHBMATPRIO>;
252#[allow(missing_docs)]
253#[doc(hidden)]
254pub struct _AHBMATPRIO;
255#[doc = "`read()` method returns [ahbmatprio::R](ahbmatprio::R) reader structure"]
256impl crate::Readable for AHBMATPRIO {}
257#[doc = "`write(|w| ..)` method takes [ahbmatprio::W](ahbmatprio::W) writer structure"]
258impl crate::Writable for AHBMATPRIO {}
259#[doc = "AHB multilayer matrix priority control"]
260pub mod ahbmatprio;
261#[doc = "System tick counter calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systckcal](systckcal) module"]
262pub type SYSTCKCAL = crate::Reg<u32, _SYSTCKCAL>;
263#[allow(missing_docs)]
264#[doc(hidden)]
265pub struct _SYSTCKCAL;
266#[doc = "`read()` method returns [systckcal::R](systckcal::R) reader structure"]
267impl crate::Readable for SYSTCKCAL {}
268#[doc = "`write(|w| ..)` method takes [systckcal::W](systckcal::W) writer structure"]
269impl crate::Writable for SYSTCKCAL {}
270#[doc = "System tick counter calibration"]
271pub mod systckcal;
272#[doc = "NMI Source Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmisrc](nmisrc) module"]
273pub type NMISRC = crate::Reg<u32, _NMISRC>;
274#[allow(missing_docs)]
275#[doc(hidden)]
276pub struct _NMISRC;
277#[doc = "`read()` method returns [nmisrc::R](nmisrc::R) reader structure"]
278impl crate::Readable for NMISRC {}
279#[doc = "`write(|w| ..)` method takes [nmisrc::W](nmisrc::W) writer structure"]
280impl crate::Writable for NMISRC {}
281#[doc = "NMI Source Select"]
282pub mod nmisrc;
283#[doc = "Asynchronous APB Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asyncapbctrl](asyncapbctrl) module"]
284pub type ASYNCAPBCTRL = crate::Reg<u32, _ASYNCAPBCTRL>;
285#[allow(missing_docs)]
286#[doc(hidden)]
287pub struct _ASYNCAPBCTRL;
288#[doc = "`read()` method returns [asyncapbctrl::R](asyncapbctrl::R) reader structure"]
289impl crate::Readable for ASYNCAPBCTRL {}
290#[doc = "`write(|w| ..)` method takes [asyncapbctrl::W](asyncapbctrl::W) writer structure"]
291impl crate::Writable for ASYNCAPBCTRL {}
292#[doc = "Asynchronous APB Control"]
293pub mod asyncapbctrl;
294#[doc = "POR captured value of port n\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pioporcap](pioporcap) module"]
295pub type PIOPORCAP = crate::Reg<u32, _PIOPORCAP>;
296#[allow(missing_docs)]
297#[doc(hidden)]
298pub struct _PIOPORCAP;
299#[doc = "`read()` method returns [pioporcap::R](pioporcap::R) reader structure"]
300impl crate::Readable for PIOPORCAP {}
301#[doc = "POR captured value of port n"]
302pub mod pioporcap;
303#[doc = "Reset captured value of port n\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [piorescap](piorescap) module"]
304pub type PIORESCAP = crate::Reg<u32, _PIORESCAP>;
305#[allow(missing_docs)]
306#[doc(hidden)]
307pub struct _PIORESCAP;
308#[doc = "`read()` method returns [piorescap::R](piorescap::R) reader structure"]
309impl crate::Readable for PIORESCAP {}
310#[doc = "Reset captured value of port n"]
311pub mod piorescap;
312#[doc = "Peripheral reset control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl0](presetctrl0) module"]
313pub type PRESETCTRL0 = crate::Reg<u32, _PRESETCTRL0>;
314#[allow(missing_docs)]
315#[doc(hidden)]
316pub struct _PRESETCTRL0;
317#[doc = "`read()` method returns [presetctrl0::R](presetctrl0::R) reader structure"]
318impl crate::Readable for PRESETCTRL0 {}
319#[doc = "`write(|w| ..)` method takes [presetctrl0::W](presetctrl0::W) writer structure"]
320impl crate::Writable for PRESETCTRL0 {}
321#[doc = "Peripheral reset control n"]
322pub mod presetctrl0;
323#[doc = "Peripheral reset control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl1](presetctrl1) module"]
324pub type PRESETCTRL1 = crate::Reg<u32, _PRESETCTRL1>;
325#[allow(missing_docs)]
326#[doc(hidden)]
327pub struct _PRESETCTRL1;
328#[doc = "`read()` method returns [presetctrl1::R](presetctrl1::R) reader structure"]
329impl crate::Readable for PRESETCTRL1 {}
330#[doc = "`write(|w| ..)` method takes [presetctrl1::W](presetctrl1::W) writer structure"]
331impl crate::Writable for PRESETCTRL1 {}
332#[doc = "Peripheral reset control n"]
333pub mod presetctrl1;
334#[doc = "Peripheral reset control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl2](presetctrl2) module"]
335pub type PRESETCTRL2 = crate::Reg<u32, _PRESETCTRL2>;
336#[allow(missing_docs)]
337#[doc(hidden)]
338pub struct _PRESETCTRL2;
339#[doc = "`read()` method returns [presetctrl2::R](presetctrl2::R) reader structure"]
340impl crate::Readable for PRESETCTRL2 {}
341#[doc = "`write(|w| ..)` method takes [presetctrl2::W](presetctrl2::W) writer structure"]
342impl crate::Writable for PRESETCTRL2 {}
343#[doc = "Peripheral reset control n"]
344pub mod presetctrl2;
345#[doc = "Set bits in PRESETCTRLn\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrlset](presetctrlset) module"]
346pub type PRESETCTRLSET = crate::Reg<u32, _PRESETCTRLSET>;
347#[allow(missing_docs)]
348#[doc(hidden)]
349pub struct _PRESETCTRLSET;
350#[doc = "`write(|w| ..)` method takes [presetctrlset::W](presetctrlset::W) writer structure"]
351impl crate::Writable for PRESETCTRLSET {}
352#[doc = "Set bits in PRESETCTRLn"]
353pub mod presetctrlset;
354#[doc = "Clear bits in PRESETCTRLn\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrlclr](presetctrlclr) module"]
355pub type PRESETCTRLCLR = crate::Reg<u32, _PRESETCTRLCLR>;
356#[allow(missing_docs)]
357#[doc(hidden)]
358pub struct _PRESETCTRLCLR;
359#[doc = "`write(|w| ..)` method takes [presetctrlclr::W](presetctrlclr::W) writer structure"]
360impl crate::Writable for PRESETCTRLCLR {}
361#[doc = "Clear bits in PRESETCTRLn"]
362pub mod presetctrlclr;
363#[doc = "System reset status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sysrststat](sysrststat) module"]
364pub type SYSRSTSTAT = crate::Reg<u32, _SYSRSTSTAT>;
365#[allow(missing_docs)]
366#[doc(hidden)]
367pub struct _SYSRSTSTAT;
368#[doc = "`read()` method returns [sysrststat::R](sysrststat::R) reader structure"]
369impl crate::Readable for SYSRSTSTAT {}
370#[doc = "`write(|w| ..)` method takes [sysrststat::W](sysrststat::W) writer structure"]
371impl crate::Writable for SYSRSTSTAT {}
372#[doc = "System reset status register"]
373pub mod sysrststat;
374#[doc = "AHB Clock control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl0](ahbclkctrl0) module"]
375pub type AHBCLKCTRL0 = crate::Reg<u32, _AHBCLKCTRL0>;
376#[allow(missing_docs)]
377#[doc(hidden)]
378pub struct _AHBCLKCTRL0;
379#[doc = "`read()` method returns [ahbclkctrl0::R](ahbclkctrl0::R) reader structure"]
380impl crate::Readable for AHBCLKCTRL0 {}
381#[doc = "`write(|w| ..)` method takes [ahbclkctrl0::W](ahbclkctrl0::W) writer structure"]
382impl crate::Writable for AHBCLKCTRL0 {}
383#[doc = "AHB Clock control n"]
384pub mod ahbclkctrl0;
385#[doc = "AHB Clock control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl1](ahbclkctrl1) module"]
386pub type AHBCLKCTRL1 = crate::Reg<u32, _AHBCLKCTRL1>;
387#[allow(missing_docs)]
388#[doc(hidden)]
389pub struct _AHBCLKCTRL1;
390#[doc = "`read()` method returns [ahbclkctrl1::R](ahbclkctrl1::R) reader structure"]
391impl crate::Readable for AHBCLKCTRL1 {}
392#[doc = "`write(|w| ..)` method takes [ahbclkctrl1::W](ahbclkctrl1::W) writer structure"]
393impl crate::Writable for AHBCLKCTRL1 {}
394#[doc = "AHB Clock control n"]
395pub mod ahbclkctrl1;
396#[doc = "AHB Clock control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl2](ahbclkctrl2) module"]
397pub type AHBCLKCTRL2 = crate::Reg<u32, _AHBCLKCTRL2>;
398#[allow(missing_docs)]
399#[doc(hidden)]
400pub struct _AHBCLKCTRL2;
401#[doc = "`read()` method returns [ahbclkctrl2::R](ahbclkctrl2::R) reader structure"]
402impl crate::Readable for AHBCLKCTRL2 {}
403#[doc = "`write(|w| ..)` method takes [ahbclkctrl2::W](ahbclkctrl2::W) writer structure"]
404impl crate::Writable for AHBCLKCTRL2 {}
405#[doc = "AHB Clock control n"]
406pub mod ahbclkctrl2;
407#[doc = "Set bits in AHBCLKCTRLn\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrlset](ahbclkctrlset) module"]
408pub type AHBCLKCTRLSET = crate::Reg<u32, _AHBCLKCTRLSET>;
409#[allow(missing_docs)]
410#[doc(hidden)]
411pub struct _AHBCLKCTRLSET;
412#[doc = "`write(|w| ..)` method takes [ahbclkctrlset::W](ahbclkctrlset::W) writer structure"]
413impl crate::Writable for AHBCLKCTRLSET {}
414#[doc = "Set bits in AHBCLKCTRLn"]
415pub mod ahbclkctrlset;
416#[doc = "Clear bits in AHBCLKCTRLn\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrlclr](ahbclkctrlclr) module"]
417pub type AHBCLKCTRLCLR = crate::Reg<u32, _AHBCLKCTRLCLR>;
418#[allow(missing_docs)]
419#[doc(hidden)]
420pub struct _AHBCLKCTRLCLR;
421#[doc = "`write(|w| ..)` method takes [ahbclkctrlclr::W](ahbclkctrlclr::W) writer structure"]
422impl crate::Writable for AHBCLKCTRLCLR {}
423#[doc = "Clear bits in AHBCLKCTRLn"]
424pub mod ahbclkctrlclr;
425#[doc = "Main clock source select A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclksela](mainclksela) module"]
426pub type MAINCLKSELA = crate::Reg<u32, _MAINCLKSELA>;
427#[allow(missing_docs)]
428#[doc(hidden)]
429pub struct _MAINCLKSELA;
430#[doc = "`read()` method returns [mainclksela::R](mainclksela::R) reader structure"]
431impl crate::Readable for MAINCLKSELA {}
432#[doc = "`write(|w| ..)` method takes [mainclksela::W](mainclksela::W) writer structure"]
433impl crate::Writable for MAINCLKSELA {}
434#[doc = "Main clock source select A"]
435pub mod mainclksela;
436#[doc = "Main clock source select B\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclkselb](mainclkselb) module"]
437pub type MAINCLKSELB = crate::Reg<u32, _MAINCLKSELB>;
438#[allow(missing_docs)]
439#[doc(hidden)]
440pub struct _MAINCLKSELB;
441#[doc = "`read()` method returns [mainclkselb::R](mainclkselb::R) reader structure"]
442impl crate::Readable for MAINCLKSELB {}
443#[doc = "`write(|w| ..)` method takes [mainclkselb::W](mainclkselb::W) writer structure"]
444impl crate::Writable for MAINCLKSELB {}
445#[doc = "Main clock source select B"]
446pub mod mainclkselb;
447#[doc = "CLKOUT clock source select A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkoutsela](clkoutsela) module"]
448pub type CLKOUTSELA = crate::Reg<u32, _CLKOUTSELA>;
449#[allow(missing_docs)]
450#[doc(hidden)]
451pub struct _CLKOUTSELA;
452#[doc = "`read()` method returns [clkoutsela::R](clkoutsela::R) reader structure"]
453impl crate::Readable for CLKOUTSELA {}
454#[doc = "`write(|w| ..)` method takes [clkoutsela::W](clkoutsela::W) writer structure"]
455impl crate::Writable for CLKOUTSELA {}
456#[doc = "CLKOUT clock source select A"]
457pub mod clkoutsela;
458#[doc = "PLL clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllclksel](syspllclksel) module"]
459pub type SYSPLLCLKSEL = crate::Reg<u32, _SYSPLLCLKSEL>;
460#[allow(missing_docs)]
461#[doc(hidden)]
462pub struct _SYSPLLCLKSEL;
463#[doc = "`read()` method returns [syspllclksel::R](syspllclksel::R) reader structure"]
464impl crate::Readable for SYSPLLCLKSEL {}
465#[doc = "`write(|w| ..)` method takes [syspllclksel::W](syspllclksel::W) writer structure"]
466impl crate::Writable for SYSPLLCLKSEL {}
467#[doc = "PLL clock source select"]
468pub mod syspllclksel;
469#[doc = "Audio PLL clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllclksel](audpllclksel) module"]
470pub type AUDPLLCLKSEL = crate::Reg<u32, _AUDPLLCLKSEL>;
471#[allow(missing_docs)]
472#[doc(hidden)]
473pub struct _AUDPLLCLKSEL;
474#[doc = "`read()` method returns [audpllclksel::R](audpllclksel::R) reader structure"]
475impl crate::Readable for AUDPLLCLKSEL {}
476#[doc = "`write(|w| ..)` method takes [audpllclksel::W](audpllclksel::W) writer structure"]
477impl crate::Writable for AUDPLLCLKSEL {}
478#[doc = "Audio PLL clock source select"]
479pub mod audpllclksel;
480#[doc = "SPIFI clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spificlksel](spificlksel) module"]
481pub type SPIFICLKSEL = crate::Reg<u32, _SPIFICLKSEL>;
482#[allow(missing_docs)]
483#[doc(hidden)]
484pub struct _SPIFICLKSEL;
485#[doc = "`read()` method returns [spificlksel::R](spificlksel::R) reader structure"]
486impl crate::Readable for SPIFICLKSEL {}
487#[doc = "`write(|w| ..)` method takes [spificlksel::W](spificlksel::W) writer structure"]
488impl crate::Writable for SPIFICLKSEL {}
489#[doc = "SPIFI clock source select"]
490pub mod spificlksel;
491#[doc = "ADC clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcclksel](adcclksel) module"]
492pub type ADCCLKSEL = crate::Reg<u32, _ADCCLKSEL>;
493#[allow(missing_docs)]
494#[doc(hidden)]
495pub struct _ADCCLKSEL;
496#[doc = "`read()` method returns [adcclksel::R](adcclksel::R) reader structure"]
497impl crate::Readable for ADCCLKSEL {}
498#[doc = "`write(|w| ..)` method takes [adcclksel::W](adcclksel::W) writer structure"]
499impl crate::Writable for ADCCLKSEL {}
500#[doc = "ADC clock source select"]
501pub mod adcclksel;
502#[doc = "USB0 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clksel](usb0clksel) module"]
503pub type USB0CLKSEL = crate::Reg<u32, _USB0CLKSEL>;
504#[allow(missing_docs)]
505#[doc(hidden)]
506pub struct _USB0CLKSEL;
507#[doc = "`read()` method returns [usb0clksel::R](usb0clksel::R) reader structure"]
508impl crate::Readable for USB0CLKSEL {}
509#[doc = "`write(|w| ..)` method takes [usb0clksel::W](usb0clksel::W) writer structure"]
510impl crate::Writable for USB0CLKSEL {}
511#[doc = "USB0 clock source select"]
512pub mod usb0clksel;
513#[doc = "USB1 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1clksel](usb1clksel) module"]
514pub type USB1CLKSEL = crate::Reg<u32, _USB1CLKSEL>;
515#[allow(missing_docs)]
516#[doc(hidden)]
517pub struct _USB1CLKSEL;
518#[doc = "`read()` method returns [usb1clksel::R](usb1clksel::R) reader structure"]
519impl crate::Readable for USB1CLKSEL {}
520#[doc = "`write(|w| ..)` method takes [usb1clksel::W](usb1clksel::W) writer structure"]
521impl crate::Writable for USB1CLKSEL {}
522#[doc = "USB1 clock source select"]
523pub mod usb1clksel;
524#[doc = "Flexcomm 0 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fclksel](fclksel) module"]
525pub type FCLKSEL = crate::Reg<u32, _FCLKSEL>;
526#[allow(missing_docs)]
527#[doc(hidden)]
528pub struct _FCLKSEL;
529#[doc = "`read()` method returns [fclksel::R](fclksel::R) reader structure"]
530impl crate::Readable for FCLKSEL {}
531#[doc = "`write(|w| ..)` method takes [fclksel::W](fclksel::W) writer structure"]
532impl crate::Writable for FCLKSEL {}
533#[doc = "Flexcomm 0 clock source select"]
534pub mod fclksel;
535#[doc = "MCLK clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkclksel](mclkclksel) module"]
536pub type MCLKCLKSEL = crate::Reg<u32, _MCLKCLKSEL>;
537#[allow(missing_docs)]
538#[doc(hidden)]
539pub struct _MCLKCLKSEL;
540#[doc = "`read()` method returns [mclkclksel::R](mclkclksel::R) reader structure"]
541impl crate::Readable for MCLKCLKSEL {}
542#[doc = "`write(|w| ..)` method takes [mclkclksel::W](mclkclksel::W) writer structure"]
543impl crate::Writable for MCLKCLKSEL {}
544#[doc = "MCLK clock source select"]
545pub mod mclkclksel;
546#[doc = "Fractional Rate Generator clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frgclksel](frgclksel) module"]
547pub type FRGCLKSEL = crate::Reg<u32, _FRGCLKSEL>;
548#[allow(missing_docs)]
549#[doc(hidden)]
550pub struct _FRGCLKSEL;
551#[doc = "`read()` method returns [frgclksel::R](frgclksel::R) reader structure"]
552impl crate::Readable for FRGCLKSEL {}
553#[doc = "`write(|w| ..)` method takes [frgclksel::W](frgclksel::W) writer structure"]
554impl crate::Writable for FRGCLKSEL {}
555#[doc = "Fractional Rate Generator clock source select"]
556pub mod frgclksel;
557#[doc = "Digital microphone (DMIC) subsystem clock select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmicclksel](dmicclksel) module"]
558pub type DMICCLKSEL = crate::Reg<u32, _DMICCLKSEL>;
559#[allow(missing_docs)]
560#[doc(hidden)]
561pub struct _DMICCLKSEL;
562#[doc = "`read()` method returns [dmicclksel::R](dmicclksel::R) reader structure"]
563impl crate::Readable for DMICCLKSEL {}
564#[doc = "`write(|w| ..)` method takes [dmicclksel::W](dmicclksel::W) writer structure"]
565impl crate::Writable for DMICCLKSEL {}
566#[doc = "Digital microphone (DMIC) subsystem clock select"]
567pub mod dmicclksel;
568#[doc = "SCTimer/PWM clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sctclksel](sctclksel) module"]
569pub type SCTCLKSEL = crate::Reg<u32, _SCTCLKSEL>;
570#[allow(missing_docs)]
571#[doc(hidden)]
572pub struct _SCTCLKSEL;
573#[doc = "`read()` method returns [sctclksel::R](sctclksel::R) reader structure"]
574impl crate::Readable for SCTCLKSEL {}
575#[doc = "`write(|w| ..)` method takes [sctclksel::W](sctclksel::W) writer structure"]
576impl crate::Writable for SCTCLKSEL {}
577#[doc = "SCTimer/PWM clock source select"]
578pub mod sctclksel;
579#[doc = "LCD clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcdclksel](lcdclksel) module"]
580pub type LCDCLKSEL = crate::Reg<u32, _LCDCLKSEL>;
581#[allow(missing_docs)]
582#[doc(hidden)]
583pub struct _LCDCLKSEL;
584#[doc = "`read()` method returns [lcdclksel::R](lcdclksel::R) reader structure"]
585impl crate::Readable for LCDCLKSEL {}
586#[doc = "`write(|w| ..)` method takes [lcdclksel::W](lcdclksel::W) writer structure"]
587impl crate::Writable for LCDCLKSEL {}
588#[doc = "LCD clock source select"]
589pub mod lcdclksel;
590#[doc = "SDIO clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclksel](sdioclksel) module"]
591pub type SDIOCLKSEL = crate::Reg<u32, _SDIOCLKSEL>;
592#[allow(missing_docs)]
593#[doc(hidden)]
594pub struct _SDIOCLKSEL;
595#[doc = "`read()` method returns [sdioclksel::R](sdioclksel::R) reader structure"]
596impl crate::Readable for SDIOCLKSEL {}
597#[doc = "`write(|w| ..)` method takes [sdioclksel::W](sdioclksel::W) writer structure"]
598impl crate::Writable for SDIOCLKSEL {}
599#[doc = "SDIO clock source select"]
600pub mod sdioclksel;
601#[doc = "SYSTICK clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclkdiv](systickclkdiv) module"]
602pub type SYSTICKCLKDIV = crate::Reg<u32, _SYSTICKCLKDIV>;
603#[allow(missing_docs)]
604#[doc(hidden)]
605pub struct _SYSTICKCLKDIV;
606#[doc = "`read()` method returns [systickclkdiv::R](systickclkdiv::R) reader structure"]
607impl crate::Readable for SYSTICKCLKDIV {}
608#[doc = "`write(|w| ..)` method takes [systickclkdiv::W](systickclkdiv::W) writer structure"]
609impl crate::Writable for SYSTICKCLKDIV {}
610#[doc = "SYSTICK clock divider"]
611pub mod systickclkdiv;
612#[doc = "ARM Trace clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [armtraceclkdiv](armtraceclkdiv) module"]
613pub type ARMTRACECLKDIV = crate::Reg<u32, _ARMTRACECLKDIV>;
614#[allow(missing_docs)]
615#[doc(hidden)]
616pub struct _ARMTRACECLKDIV;
617#[doc = "`read()` method returns [armtraceclkdiv::R](armtraceclkdiv::R) reader structure"]
618impl crate::Readable for ARMTRACECLKDIV {}
619#[doc = "`write(|w| ..)` method takes [armtraceclkdiv::W](armtraceclkdiv::W) writer structure"]
620impl crate::Writable for ARMTRACECLKDIV {}
621#[doc = "ARM Trace clock divider"]
622pub mod armtraceclkdiv;
623#[doc = "MCAN0 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [can0clkdiv](can0clkdiv) module"]
624pub type CAN0CLKDIV = crate::Reg<u32, _CAN0CLKDIV>;
625#[allow(missing_docs)]
626#[doc(hidden)]
627pub struct _CAN0CLKDIV;
628#[doc = "`read()` method returns [can0clkdiv::R](can0clkdiv::R) reader structure"]
629impl crate::Readable for CAN0CLKDIV {}
630#[doc = "`write(|w| ..)` method takes [can0clkdiv::W](can0clkdiv::W) writer structure"]
631impl crate::Writable for CAN0CLKDIV {}
632#[doc = "MCAN0 clock divider"]
633pub mod can0clkdiv;
634#[doc = "MCAN1 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [can1clkdiv](can1clkdiv) module"]
635pub type CAN1CLKDIV = crate::Reg<u32, _CAN1CLKDIV>;
636#[allow(missing_docs)]
637#[doc(hidden)]
638pub struct _CAN1CLKDIV;
639#[doc = "`read()` method returns [can1clkdiv::R](can1clkdiv::R) reader structure"]
640impl crate::Readable for CAN1CLKDIV {}
641#[doc = "`write(|w| ..)` method takes [can1clkdiv::W](can1clkdiv::W) writer structure"]
642impl crate::Writable for CAN1CLKDIV {}
643#[doc = "MCAN1 clock divider"]
644pub mod can1clkdiv;
645#[doc = "Smartcard0 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc0clkdiv](sc0clkdiv) module"]
646pub type SC0CLKDIV = crate::Reg<u32, _SC0CLKDIV>;
647#[allow(missing_docs)]
648#[doc(hidden)]
649pub struct _SC0CLKDIV;
650#[doc = "`read()` method returns [sc0clkdiv::R](sc0clkdiv::R) reader structure"]
651impl crate::Readable for SC0CLKDIV {}
652#[doc = "`write(|w| ..)` method takes [sc0clkdiv::W](sc0clkdiv::W) writer structure"]
653impl crate::Writable for SC0CLKDIV {}
654#[doc = "Smartcard0 clock divider"]
655pub mod sc0clkdiv;
656#[doc = "Smartcard1 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc1clkdiv](sc1clkdiv) module"]
657pub type SC1CLKDIV = crate::Reg<u32, _SC1CLKDIV>;
658#[allow(missing_docs)]
659#[doc(hidden)]
660pub struct _SC1CLKDIV;
661#[doc = "`read()` method returns [sc1clkdiv::R](sc1clkdiv::R) reader structure"]
662impl crate::Readable for SC1CLKDIV {}
663#[doc = "`write(|w| ..)` method takes [sc1clkdiv::W](sc1clkdiv::W) writer structure"]
664impl crate::Writable for SC1CLKDIV {}
665#[doc = "Smartcard1 clock divider"]
666pub mod sc1clkdiv;
667#[doc = "AHB clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkdiv](ahbclkdiv) module"]
668pub type AHBCLKDIV = crate::Reg<u32, _AHBCLKDIV>;
669#[allow(missing_docs)]
670#[doc(hidden)]
671pub struct _AHBCLKDIV;
672#[doc = "`read()` method returns [ahbclkdiv::R](ahbclkdiv::R) reader structure"]
673impl crate::Readable for AHBCLKDIV {}
674#[doc = "`write(|w| ..)` method takes [ahbclkdiv::W](ahbclkdiv::W) writer structure"]
675impl crate::Writable for AHBCLKDIV {}
676#[doc = "AHB clock divider"]
677pub mod ahbclkdiv;
678#[doc = "CLKOUT clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkoutdiv](clkoutdiv) module"]
679pub type CLKOUTDIV = crate::Reg<u32, _CLKOUTDIV>;
680#[allow(missing_docs)]
681#[doc(hidden)]
682pub struct _CLKOUTDIV;
683#[doc = "`read()` method returns [clkoutdiv::R](clkoutdiv::R) reader structure"]
684impl crate::Readable for CLKOUTDIV {}
685#[doc = "`write(|w| ..)` method takes [clkoutdiv::W](clkoutdiv::W) writer structure"]
686impl crate::Writable for CLKOUTDIV {}
687#[doc = "CLKOUT clock divider"]
688pub mod clkoutdiv;
689#[doc = "FROHF clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frohfclkdiv](frohfclkdiv) module"]
690pub type FROHFCLKDIV = crate::Reg<u32, _FROHFCLKDIV>;
691#[allow(missing_docs)]
692#[doc(hidden)]
693pub struct _FROHFCLKDIV;
694#[doc = "`read()` method returns [frohfclkdiv::R](frohfclkdiv::R) reader structure"]
695impl crate::Readable for FROHFCLKDIV {}
696#[doc = "`write(|w| ..)` method takes [frohfclkdiv::W](frohfclkdiv::W) writer structure"]
697impl crate::Writable for FROHFCLKDIV {}
698#[doc = "FROHF clock divider"]
699pub mod frohfclkdiv;
700#[doc = "SPIFI clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spificlkdiv](spificlkdiv) module"]
701pub type SPIFICLKDIV = crate::Reg<u32, _SPIFICLKDIV>;
702#[allow(missing_docs)]
703#[doc(hidden)]
704pub struct _SPIFICLKDIV;
705#[doc = "`read()` method returns [spificlkdiv::R](spificlkdiv::R) reader structure"]
706impl crate::Readable for SPIFICLKDIV {}
707#[doc = "`write(|w| ..)` method takes [spificlkdiv::W](spificlkdiv::W) writer structure"]
708impl crate::Writable for SPIFICLKDIV {}
709#[doc = "SPIFI clock divider"]
710pub mod spificlkdiv;
711#[doc = "ADC clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcclkdiv](adcclkdiv) module"]
712pub type ADCCLKDIV = crate::Reg<u32, _ADCCLKDIV>;
713#[allow(missing_docs)]
714#[doc(hidden)]
715pub struct _ADCCLKDIV;
716#[doc = "`read()` method returns [adcclkdiv::R](adcclkdiv::R) reader structure"]
717impl crate::Readable for ADCCLKDIV {}
718#[doc = "`write(|w| ..)` method takes [adcclkdiv::W](adcclkdiv::W) writer structure"]
719impl crate::Writable for ADCCLKDIV {}
720#[doc = "ADC clock divider"]
721pub mod adcclkdiv;
722#[doc = "USB0 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clkdiv](usb0clkdiv) module"]
723pub type USB0CLKDIV = crate::Reg<u32, _USB0CLKDIV>;
724#[allow(missing_docs)]
725#[doc(hidden)]
726pub struct _USB0CLKDIV;
727#[doc = "`read()` method returns [usb0clkdiv::R](usb0clkdiv::R) reader structure"]
728impl crate::Readable for USB0CLKDIV {}
729#[doc = "`write(|w| ..)` method takes [usb0clkdiv::W](usb0clkdiv::W) writer structure"]
730impl crate::Writable for USB0CLKDIV {}
731#[doc = "USB0 clock divider"]
732pub mod usb0clkdiv;
733#[doc = "USB1 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1clkdiv](usb1clkdiv) module"]
734pub type USB1CLKDIV = crate::Reg<u32, _USB1CLKDIV>;
735#[allow(missing_docs)]
736#[doc(hidden)]
737pub struct _USB1CLKDIV;
738#[doc = "`read()` method returns [usb1clkdiv::R](usb1clkdiv::R) reader structure"]
739impl crate::Readable for USB1CLKDIV {}
740#[doc = "`write(|w| ..)` method takes [usb1clkdiv::W](usb1clkdiv::W) writer structure"]
741impl crate::Writable for USB1CLKDIV {}
742#[doc = "USB1 clock divider"]
743pub mod usb1clkdiv;
744#[doc = "Fractional rate divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frgctrl](frgctrl) module"]
745pub type FRGCTRL = crate::Reg<u32, _FRGCTRL>;
746#[allow(missing_docs)]
747#[doc(hidden)]
748pub struct _FRGCTRL;
749#[doc = "`read()` method returns [frgctrl::R](frgctrl::R) reader structure"]
750impl crate::Readable for FRGCTRL {}
751#[doc = "`write(|w| ..)` method takes [frgctrl::W](frgctrl::W) writer structure"]
752impl crate::Writable for FRGCTRL {}
753#[doc = "Fractional rate divider"]
754pub mod frgctrl;
755#[doc = "DMIC clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmicclkdiv](dmicclkdiv) module"]
756pub type DMICCLKDIV = crate::Reg<u32, _DMICCLKDIV>;
757#[allow(missing_docs)]
758#[doc(hidden)]
759pub struct _DMICCLKDIV;
760#[doc = "`read()` method returns [dmicclkdiv::R](dmicclkdiv::R) reader structure"]
761impl crate::Readable for DMICCLKDIV {}
762#[doc = "`write(|w| ..)` method takes [dmicclkdiv::W](dmicclkdiv::W) writer structure"]
763impl crate::Writable for DMICCLKDIV {}
764#[doc = "DMIC clock divider"]
765pub mod dmicclkdiv;
766#[doc = "I2S MCLK clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkdiv](mclkdiv) module"]
767pub type MCLKDIV = crate::Reg<u32, _MCLKDIV>;
768#[allow(missing_docs)]
769#[doc(hidden)]
770pub struct _MCLKDIV;
771#[doc = "`read()` method returns [mclkdiv::R](mclkdiv::R) reader structure"]
772impl crate::Readable for MCLKDIV {}
773#[doc = "`write(|w| ..)` method takes [mclkdiv::W](mclkdiv::W) writer structure"]
774impl crate::Writable for MCLKDIV {}
775#[doc = "I2S MCLK clock divider"]
776pub mod mclkdiv;
777#[doc = "LCD clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcdclkdiv](lcdclkdiv) module"]
778pub type LCDCLKDIV = crate::Reg<u32, _LCDCLKDIV>;
779#[allow(missing_docs)]
780#[doc(hidden)]
781pub struct _LCDCLKDIV;
782#[doc = "`read()` method returns [lcdclkdiv::R](lcdclkdiv::R) reader structure"]
783impl crate::Readable for LCDCLKDIV {}
784#[doc = "`write(|w| ..)` method takes [lcdclkdiv::W](lcdclkdiv::W) writer structure"]
785impl crate::Writable for LCDCLKDIV {}
786#[doc = "LCD clock divider"]
787pub mod lcdclkdiv;
788#[doc = "SCT/PWM clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sctclkdiv](sctclkdiv) module"]
789pub type SCTCLKDIV = crate::Reg<u32, _SCTCLKDIV>;
790#[allow(missing_docs)]
791#[doc(hidden)]
792pub struct _SCTCLKDIV;
793#[doc = "`read()` method returns [sctclkdiv::R](sctclkdiv::R) reader structure"]
794impl crate::Readable for SCTCLKDIV {}
795#[doc = "`write(|w| ..)` method takes [sctclkdiv::W](sctclkdiv::W) writer structure"]
796impl crate::Writable for SCTCLKDIV {}
797#[doc = "SCT/PWM clock divider"]
798pub mod sctclkdiv;
799#[doc = "EMC clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emcclkdiv](emcclkdiv) module"]
800pub type EMCCLKDIV = crate::Reg<u32, _EMCCLKDIV>;
801#[allow(missing_docs)]
802#[doc(hidden)]
803pub struct _EMCCLKDIV;
804#[doc = "`read()` method returns [emcclkdiv::R](emcclkdiv::R) reader structure"]
805impl crate::Readable for EMCCLKDIV {}
806#[doc = "`write(|w| ..)` method takes [emcclkdiv::W](emcclkdiv::W) writer structure"]
807impl crate::Writable for EMCCLKDIV {}
808#[doc = "EMC clock divider"]
809pub mod emcclkdiv;
810#[doc = "SDIO clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclkdiv](sdioclkdiv) module"]
811pub type SDIOCLKDIV = crate::Reg<u32, _SDIOCLKDIV>;
812#[allow(missing_docs)]
813#[doc(hidden)]
814pub struct _SDIOCLKDIV;
815#[doc = "`read()` method returns [sdioclkdiv::R](sdioclkdiv::R) reader structure"]
816impl crate::Readable for SDIOCLKDIV {}
817#[doc = "`write(|w| ..)` method takes [sdioclkdiv::W](sdioclkdiv::W) writer structure"]
818impl crate::Writable for SDIOCLKDIV {}
819#[doc = "SDIO clock divider"]
820pub mod sdioclkdiv;
821#[doc = "Flash wait states configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flashcfg](flashcfg) module"]
822pub type FLASHCFG = crate::Reg<u32, _FLASHCFG>;
823#[allow(missing_docs)]
824#[doc(hidden)]
825pub struct _FLASHCFG;
826#[doc = "`read()` method returns [flashcfg::R](flashcfg::R) reader structure"]
827impl crate::Readable for FLASHCFG {}
828#[doc = "`write(|w| ..)` method takes [flashcfg::W](flashcfg::W) writer structure"]
829impl crate::Writable for FLASHCFG {}
830#[doc = "Flash wait states configuration"]
831pub mod flashcfg;
832#[doc = "USB0 clock control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clkctrl](usb0clkctrl) module"]
833pub type USB0CLKCTRL = crate::Reg<u32, _USB0CLKCTRL>;
834#[allow(missing_docs)]
835#[doc(hidden)]
836pub struct _USB0CLKCTRL;
837#[doc = "`read()` method returns [usb0clkctrl::R](usb0clkctrl::R) reader structure"]
838impl crate::Readable for USB0CLKCTRL {}
839#[doc = "`write(|w| ..)` method takes [usb0clkctrl::W](usb0clkctrl::W) writer structure"]
840impl crate::Writable for USB0CLKCTRL {}
841#[doc = "USB0 clock control"]
842pub mod usb0clkctrl;
843#[doc = "USB0 clock status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clkstat](usb0clkstat) module"]
844pub type USB0CLKSTAT = crate::Reg<u32, _USB0CLKSTAT>;
845#[allow(missing_docs)]
846#[doc(hidden)]
847pub struct _USB0CLKSTAT;
848#[doc = "`read()` method returns [usb0clkstat::R](usb0clkstat::R) reader structure"]
849impl crate::Readable for USB0CLKSTAT {}
850#[doc = "`write(|w| ..)` method takes [usb0clkstat::W](usb0clkstat::W) writer structure"]
851impl crate::Writable for USB0CLKSTAT {}
852#[doc = "USB0 clock status"]
853pub mod usb0clkstat;
854#[doc = "Frequency measure register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqmectrl](freqmectrl) module"]
855pub type FREQMECTRL = crate::Reg<u32, _FREQMECTRL>;
856#[allow(missing_docs)]
857#[doc(hidden)]
858pub struct _FREQMECTRL;
859#[doc = "`read()` method returns [freqmectrl::R](freqmectrl::R) reader structure"]
860impl crate::Readable for FREQMECTRL {}
861#[doc = "`write(|w| ..)` method takes [freqmectrl::W](freqmectrl::W) writer structure"]
862impl crate::Writable for FREQMECTRL {}
863#[doc = "Frequency measure register"]
864pub mod freqmectrl;
865#[doc = "MCLK input/output control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkio](mclkio) module"]
866pub type MCLKIO = crate::Reg<u32, _MCLKIO>;
867#[allow(missing_docs)]
868#[doc(hidden)]
869pub struct _MCLKIO;
870#[doc = "`read()` method returns [mclkio::R](mclkio::R) reader structure"]
871impl crate::Readable for MCLKIO {}
872#[doc = "`write(|w| ..)` method takes [mclkio::W](mclkio::W) writer structure"]
873impl crate::Writable for MCLKIO {}
874#[doc = "MCLK input/output control"]
875pub mod mclkio;
876#[doc = "USB1 clock control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1clkctrl](usb1clkctrl) module"]
877pub type USB1CLKCTRL = crate::Reg<u32, _USB1CLKCTRL>;
878#[allow(missing_docs)]
879#[doc(hidden)]
880pub struct _USB1CLKCTRL;
881#[doc = "`read()` method returns [usb1clkctrl::R](usb1clkctrl::R) reader structure"]
882impl crate::Readable for USB1CLKCTRL {}
883#[doc = "`write(|w| ..)` method takes [usb1clkctrl::W](usb1clkctrl::W) writer structure"]
884impl crate::Writable for USB1CLKCTRL {}
885#[doc = "USB1 clock control"]
886pub mod usb1clkctrl;
887#[doc = "USB1 clock status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1clkstat](usb1clkstat) module"]
888pub type USB1CLKSTAT = crate::Reg<u32, _USB1CLKSTAT>;
889#[allow(missing_docs)]
890#[doc(hidden)]
891pub struct _USB1CLKSTAT;
892#[doc = "`read()` method returns [usb1clkstat::R](usb1clkstat::R) reader structure"]
893impl crate::Readable for USB1CLKSTAT {}
894#[doc = "`write(|w| ..)` method takes [usb1clkstat::W](usb1clkstat::W) writer structure"]
895impl crate::Writable for USB1CLKSTAT {}
896#[doc = "USB1 clock status"]
897pub mod usb1clkstat;
898#[doc = "EMC system control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emcsysctrl](emcsysctrl) module"]
899pub type EMCSYSCTRL = crate::Reg<u32, _EMCSYSCTRL>;
900#[allow(missing_docs)]
901#[doc(hidden)]
902pub struct _EMCSYSCTRL;
903#[doc = "`read()` method returns [emcsysctrl::R](emcsysctrl::R) reader structure"]
904impl crate::Readable for EMCSYSCTRL {}
905#[doc = "`write(|w| ..)` method takes [emcsysctrl::W](emcsysctrl::W) writer structure"]
906impl crate::Writable for EMCSYSCTRL {}
907#[doc = "EMC system control"]
908pub mod emcsysctrl;
909#[doc = "EMC clock delay control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emcdlyctrl](emcdlyctrl) module"]
910pub type EMCDLYCTRL = crate::Reg<u32, _EMCDLYCTRL>;
911#[allow(missing_docs)]
912#[doc(hidden)]
913pub struct _EMCDLYCTRL;
914#[doc = "`read()` method returns [emcdlyctrl::R](emcdlyctrl::R) reader structure"]
915impl crate::Readable for EMCDLYCTRL {}
916#[doc = "`write(|w| ..)` method takes [emcdlyctrl::W](emcdlyctrl::W) writer structure"]
917impl crate::Writable for EMCDLYCTRL {}
918#[doc = "EMC clock delay control"]
919pub mod emcdlyctrl;
920#[doc = "EMC delay chain calibration control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emcdlycal](emcdlycal) module"]
921pub type EMCDLYCAL = crate::Reg<u32, _EMCDLYCAL>;
922#[allow(missing_docs)]
923#[doc(hidden)]
924pub struct _EMCDLYCAL;
925#[doc = "`read()` method returns [emcdlycal::R](emcdlycal::R) reader structure"]
926impl crate::Readable for EMCDLYCAL {}
927#[doc = "`write(|w| ..)` method takes [emcdlycal::W](emcdlycal::W) writer structure"]
928impl crate::Writable for EMCDLYCAL {}
929#[doc = "EMC delay chain calibration control"]
930pub mod emcdlycal;
931#[doc = "Ethernet PHY Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ethphysel](ethphysel) module"]
932pub type ETHPHYSEL = crate::Reg<u32, _ETHPHYSEL>;
933#[allow(missing_docs)]
934#[doc(hidden)]
935pub struct _ETHPHYSEL;
936#[doc = "`read()` method returns [ethphysel::R](ethphysel::R) reader structure"]
937impl crate::Readable for ETHPHYSEL {}
938#[doc = "`write(|w| ..)` method takes [ethphysel::W](ethphysel::W) writer structure"]
939impl crate::Writable for ETHPHYSEL {}
940#[doc = "Ethernet PHY Selection"]
941pub mod ethphysel;
942#[doc = "Ethernet SBD flow control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ethsbdctrl](ethsbdctrl) module"]
943pub type ETHSBDCTRL = crate::Reg<u32, _ETHSBDCTRL>;
944#[allow(missing_docs)]
945#[doc(hidden)]
946pub struct _ETHSBDCTRL;
947#[doc = "`read()` method returns [ethsbdctrl::R](ethsbdctrl::R) reader structure"]
948impl crate::Readable for ETHSBDCTRL {}
949#[doc = "`write(|w| ..)` method takes [ethsbdctrl::W](ethsbdctrl::W) writer structure"]
950impl crate::Writable for ETHSBDCTRL {}
951#[doc = "Ethernet SBD flow control"]
952pub mod ethsbdctrl;
953#[doc = "SDIO CCLKIN phase and delay control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclkctrl](sdioclkctrl) module"]
954pub type SDIOCLKCTRL = crate::Reg<u32, _SDIOCLKCTRL>;
955#[allow(missing_docs)]
956#[doc(hidden)]
957pub struct _SDIOCLKCTRL;
958#[doc = "`read()` method returns [sdioclkctrl::R](sdioclkctrl::R) reader structure"]
959impl crate::Readable for SDIOCLKCTRL {}
960#[doc = "`write(|w| ..)` method takes [sdioclkctrl::W](sdioclkctrl::W) writer structure"]
961impl crate::Writable for SDIOCLKCTRL {}
962#[doc = "SDIO CCLKIN phase and delay control"]
963pub mod sdioclkctrl;
964#[doc = "FRO oscillator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [froctrl](froctrl) module"]
965pub type FROCTRL = crate::Reg<u32, _FROCTRL>;
966#[allow(missing_docs)]
967#[doc(hidden)]
968pub struct _FROCTRL;
969#[doc = "`read()` method returns [froctrl::R](froctrl::R) reader structure"]
970impl crate::Readable for FROCTRL {}
971#[doc = "`write(|w| ..)` method takes [froctrl::W](froctrl::W) writer structure"]
972impl crate::Writable for FROCTRL {}
973#[doc = "FRO oscillator control"]
974pub mod froctrl;
975#[doc = "System oscillator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sysoscctrl](sysoscctrl) module"]
976pub type SYSOSCCTRL = crate::Reg<u32, _SYSOSCCTRL>;
977#[allow(missing_docs)]
978#[doc(hidden)]
979pub struct _SYSOSCCTRL;
980#[doc = "`read()` method returns [sysoscctrl::R](sysoscctrl::R) reader structure"]
981impl crate::Readable for SYSOSCCTRL {}
982#[doc = "`write(|w| ..)` method takes [sysoscctrl::W](sysoscctrl::W) writer structure"]
983impl crate::Writable for SYSOSCCTRL {}
984#[doc = "System oscillator control"]
985pub mod sysoscctrl;
986#[doc = "Watchdog oscillator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdtoscctrl](wdtoscctrl) module"]
987pub type WDTOSCCTRL = crate::Reg<u32, _WDTOSCCTRL>;
988#[allow(missing_docs)]
989#[doc(hidden)]
990pub struct _WDTOSCCTRL;
991#[doc = "`read()` method returns [wdtoscctrl::R](wdtoscctrl::R) reader structure"]
992impl crate::Readable for WDTOSCCTRL {}
993#[doc = "`write(|w| ..)` method takes [wdtoscctrl::W](wdtoscctrl::W) writer structure"]
994impl crate::Writable for WDTOSCCTRL {}
995#[doc = "Watchdog oscillator control"]
996pub mod wdtoscctrl;
997#[doc = "RTC oscillator 32 kHz output control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcoscctrl](rtcoscctrl) module"]
998pub type RTCOSCCTRL = crate::Reg<u32, _RTCOSCCTRL>;
999#[allow(missing_docs)]
1000#[doc(hidden)]
1001pub struct _RTCOSCCTRL;
1002#[doc = "`read()` method returns [rtcoscctrl::R](rtcoscctrl::R) reader structure"]
1003impl crate::Readable for RTCOSCCTRL {}
1004#[doc = "`write(|w| ..)` method takes [rtcoscctrl::W](rtcoscctrl::W) writer structure"]
1005impl crate::Writable for RTCOSCCTRL {}
1006#[doc = "RTC oscillator 32 kHz output control"]
1007pub mod rtcoscctrl;
1008#[doc = "USB PLL control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usbpllctrl](usbpllctrl) module"]
1009pub type USBPLLCTRL = crate::Reg<u32, _USBPLLCTRL>;
1010#[allow(missing_docs)]
1011#[doc(hidden)]
1012pub struct _USBPLLCTRL;
1013#[doc = "`read()` method returns [usbpllctrl::R](usbpllctrl::R) reader structure"]
1014impl crate::Readable for USBPLLCTRL {}
1015#[doc = "`write(|w| ..)` method takes [usbpllctrl::W](usbpllctrl::W) writer structure"]
1016impl crate::Writable for USBPLLCTRL {}
1017#[doc = "USB PLL control"]
1018pub mod usbpllctrl;
1019#[doc = "USB PLL status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usbpllstat](usbpllstat) module"]
1020pub type USBPLLSTAT = crate::Reg<u32, _USBPLLSTAT>;
1021#[allow(missing_docs)]
1022#[doc(hidden)]
1023pub struct _USBPLLSTAT;
1024#[doc = "`read()` method returns [usbpllstat::R](usbpllstat::R) reader structure"]
1025impl crate::Readable for USBPLLSTAT {}
1026#[doc = "`write(|w| ..)` method takes [usbpllstat::W](usbpllstat::W) writer structure"]
1027impl crate::Writable for USBPLLSTAT {}
1028#[doc = "USB PLL status"]
1029pub mod usbpllstat;
1030#[doc = "System PLL control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllctrl](syspllctrl) module"]
1031pub type SYSPLLCTRL = crate::Reg<u32, _SYSPLLCTRL>;
1032#[allow(missing_docs)]
1033#[doc(hidden)]
1034pub struct _SYSPLLCTRL;
1035#[doc = "`read()` method returns [syspllctrl::R](syspllctrl::R) reader structure"]
1036impl crate::Readable for SYSPLLCTRL {}
1037#[doc = "`write(|w| ..)` method takes [syspllctrl::W](syspllctrl::W) writer structure"]
1038impl crate::Writable for SYSPLLCTRL {}
1039#[doc = "System PLL control"]
1040pub mod syspllctrl;
1041#[doc = "PLL status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllstat](syspllstat) module"]
1042pub type SYSPLLSTAT = crate::Reg<u32, _SYSPLLSTAT>;
1043#[allow(missing_docs)]
1044#[doc(hidden)]
1045pub struct _SYSPLLSTAT;
1046#[doc = "`read()` method returns [syspllstat::R](syspllstat::R) reader structure"]
1047impl crate::Readable for SYSPLLSTAT {}
1048#[doc = "`write(|w| ..)` method takes [syspllstat::W](syspllstat::W) writer structure"]
1049impl crate::Writable for SYSPLLSTAT {}
1050#[doc = "PLL status"]
1051pub mod syspllstat;
1052#[doc = "PLL N divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllndec](syspllndec) module"]
1053pub type SYSPLLNDEC = crate::Reg<u32, _SYSPLLNDEC>;
1054#[allow(missing_docs)]
1055#[doc(hidden)]
1056pub struct _SYSPLLNDEC;
1057#[doc = "`read()` method returns [syspllndec::R](syspllndec::R) reader structure"]
1058impl crate::Readable for SYSPLLNDEC {}
1059#[doc = "`write(|w| ..)` method takes [syspllndec::W](syspllndec::W) writer structure"]
1060impl crate::Writable for SYSPLLNDEC {}
1061#[doc = "PLL N divider"]
1062pub mod syspllndec;
1063#[doc = "PLL P divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllpdec](syspllpdec) module"]
1064pub type SYSPLLPDEC = crate::Reg<u32, _SYSPLLPDEC>;
1065#[allow(missing_docs)]
1066#[doc(hidden)]
1067pub struct _SYSPLLPDEC;
1068#[doc = "`read()` method returns [syspllpdec::R](syspllpdec::R) reader structure"]
1069impl crate::Readable for SYSPLLPDEC {}
1070#[doc = "`write(|w| ..)` method takes [syspllpdec::W](syspllpdec::W) writer structure"]
1071impl crate::Writable for SYSPLLPDEC {}
1072#[doc = "PLL P divider"]
1073pub mod syspllpdec;
1074#[doc = "System PLL M divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllmdec](syspllmdec) module"]
1075pub type SYSPLLMDEC = crate::Reg<u32, _SYSPLLMDEC>;
1076#[allow(missing_docs)]
1077#[doc(hidden)]
1078pub struct _SYSPLLMDEC;
1079#[doc = "`read()` method returns [syspllmdec::R](syspllmdec::R) reader structure"]
1080impl crate::Readable for SYSPLLMDEC {}
1081#[doc = "`write(|w| ..)` method takes [syspllmdec::W](syspllmdec::W) writer structure"]
1082impl crate::Writable for SYSPLLMDEC {}
1083#[doc = "System PLL M divider"]
1084pub mod syspllmdec;
1085#[doc = "Audio PLL control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllctrl](audpllctrl) module"]
1086pub type AUDPLLCTRL = crate::Reg<u32, _AUDPLLCTRL>;
1087#[allow(missing_docs)]
1088#[doc(hidden)]
1089pub struct _AUDPLLCTRL;
1090#[doc = "`read()` method returns [audpllctrl::R](audpllctrl::R) reader structure"]
1091impl crate::Readable for AUDPLLCTRL {}
1092#[doc = "`write(|w| ..)` method takes [audpllctrl::W](audpllctrl::W) writer structure"]
1093impl crate::Writable for AUDPLLCTRL {}
1094#[doc = "Audio PLL control"]
1095pub mod audpllctrl;
1096#[doc = "Audio PLL status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllstat](audpllstat) module"]
1097pub type AUDPLLSTAT = crate::Reg<u32, _AUDPLLSTAT>;
1098#[allow(missing_docs)]
1099#[doc(hidden)]
1100pub struct _AUDPLLSTAT;
1101#[doc = "`read()` method returns [audpllstat::R](audpllstat::R) reader structure"]
1102impl crate::Readable for AUDPLLSTAT {}
1103#[doc = "`write(|w| ..)` method takes [audpllstat::W](audpllstat::W) writer structure"]
1104impl crate::Writable for AUDPLLSTAT {}
1105#[doc = "Audio PLL status"]
1106pub mod audpllstat;
1107#[doc = "Audio PLL N divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllndec](audpllndec) module"]
1108pub type AUDPLLNDEC = crate::Reg<u32, _AUDPLLNDEC>;
1109#[allow(missing_docs)]
1110#[doc(hidden)]
1111pub struct _AUDPLLNDEC;
1112#[doc = "`read()` method returns [audpllndec::R](audpllndec::R) reader structure"]
1113impl crate::Readable for AUDPLLNDEC {}
1114#[doc = "`write(|w| ..)` method takes [audpllndec::W](audpllndec::W) writer structure"]
1115impl crate::Writable for AUDPLLNDEC {}
1116#[doc = "Audio PLL N divider"]
1117pub mod audpllndec;
1118#[doc = "Audio PLL P divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllpdec](audpllpdec) module"]
1119pub type AUDPLLPDEC = crate::Reg<u32, _AUDPLLPDEC>;
1120#[allow(missing_docs)]
1121#[doc(hidden)]
1122pub struct _AUDPLLPDEC;
1123#[doc = "`read()` method returns [audpllpdec::R](audpllpdec::R) reader structure"]
1124impl crate::Readable for AUDPLLPDEC {}
1125#[doc = "`write(|w| ..)` method takes [audpllpdec::W](audpllpdec::W) writer structure"]
1126impl crate::Writable for AUDPLLPDEC {}
1127#[doc = "Audio PLL P divider"]
1128pub mod audpllpdec;
1129#[doc = "Audio PLL M divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllmdec](audpllmdec) module"]
1130pub type AUDPLLMDEC = crate::Reg<u32, _AUDPLLMDEC>;
1131#[allow(missing_docs)]
1132#[doc(hidden)]
1133pub struct _AUDPLLMDEC;
1134#[doc = "`read()` method returns [audpllmdec::R](audpllmdec::R) reader structure"]
1135impl crate::Readable for AUDPLLMDEC {}
1136#[doc = "`write(|w| ..)` method takes [audpllmdec::W](audpllmdec::W) writer structure"]
1137impl crate::Writable for AUDPLLMDEC {}
1138#[doc = "Audio PLL M divider"]
1139pub mod audpllmdec;
1140#[doc = "Audio PLL fractional divider control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audpllfrac](audpllfrac) module"]
1141pub type AUDPLLFRAC = crate::Reg<u32, _AUDPLLFRAC>;
1142#[allow(missing_docs)]
1143#[doc(hidden)]
1144pub struct _AUDPLLFRAC;
1145#[doc = "`read()` method returns [audpllfrac::R](audpllfrac::R) reader structure"]
1146impl crate::Readable for AUDPLLFRAC {}
1147#[doc = "`write(|w| ..)` method takes [audpllfrac::W](audpllfrac::W) writer structure"]
1148impl crate::Writable for AUDPLLFRAC {}
1149#[doc = "Audio PLL fractional divider control"]
1150pub mod audpllfrac;
1151#[doc = "Sleep configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdsleepcfg0](pdsleepcfg0) module"]
1152pub type PDSLEEPCFG0 = crate::Reg<u32, _PDSLEEPCFG0>;
1153#[allow(missing_docs)]
1154#[doc(hidden)]
1155pub struct _PDSLEEPCFG0;
1156#[doc = "`read()` method returns [pdsleepcfg0::R](pdsleepcfg0::R) reader structure"]
1157impl crate::Readable for PDSLEEPCFG0 {}
1158#[doc = "`write(|w| ..)` method takes [pdsleepcfg0::W](pdsleepcfg0::W) writer structure"]
1159impl crate::Writable for PDSLEEPCFG0 {}
1160#[doc = "Sleep configuration register"]
1161pub mod pdsleepcfg0;
1162#[doc = "Sleep configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdsleepcfg1](pdsleepcfg1) module"]
1163pub type PDSLEEPCFG1 = crate::Reg<u32, _PDSLEEPCFG1>;
1164#[allow(missing_docs)]
1165#[doc(hidden)]
1166pub struct _PDSLEEPCFG1;
1167#[doc = "`read()` method returns [pdsleepcfg1::R](pdsleepcfg1::R) reader structure"]
1168impl crate::Readable for PDSLEEPCFG1 {}
1169#[doc = "`write(|w| ..)` method takes [pdsleepcfg1::W](pdsleepcfg1::W) writer structure"]
1170impl crate::Writable for PDSLEEPCFG1 {}
1171#[doc = "Sleep configuration register"]
1172pub mod pdsleepcfg1;
1173#[doc = "Power configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfg0](pdruncfg0) module"]
1174pub type PDRUNCFG0 = crate::Reg<u32, _PDRUNCFG0>;
1175#[allow(missing_docs)]
1176#[doc(hidden)]
1177pub struct _PDRUNCFG0;
1178#[doc = "`read()` method returns [pdruncfg0::R](pdruncfg0::R) reader structure"]
1179impl crate::Readable for PDRUNCFG0 {}
1180#[doc = "`write(|w| ..)` method takes [pdruncfg0::W](pdruncfg0::W) writer structure"]
1181impl crate::Writable for PDRUNCFG0 {}
1182#[doc = "Power configuration register"]
1183pub mod pdruncfg0;
1184#[doc = "Power configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfg1](pdruncfg1) module"]
1185pub type PDRUNCFG1 = crate::Reg<u32, _PDRUNCFG1>;
1186#[allow(missing_docs)]
1187#[doc(hidden)]
1188pub struct _PDRUNCFG1;
1189#[doc = "`read()` method returns [pdruncfg1::R](pdruncfg1::R) reader structure"]
1190impl crate::Readable for PDRUNCFG1 {}
1191#[doc = "`write(|w| ..)` method takes [pdruncfg1::W](pdruncfg1::W) writer structure"]
1192impl crate::Writable for PDRUNCFG1 {}
1193#[doc = "Power configuration register"]
1194pub mod pdruncfg1;
1195#[doc = "Power configuration set register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfgset0](pdruncfgset0) module"]
1196pub type PDRUNCFGSET0 = crate::Reg<u32, _PDRUNCFGSET0>;
1197#[allow(missing_docs)]
1198#[doc(hidden)]
1199pub struct _PDRUNCFGSET0;
1200#[doc = "`read()` method returns [pdruncfgset0::R](pdruncfgset0::R) reader structure"]
1201impl crate::Readable for PDRUNCFGSET0 {}
1202#[doc = "`write(|w| ..)` method takes [pdruncfgset0::W](pdruncfgset0::W) writer structure"]
1203impl crate::Writable for PDRUNCFGSET0 {}
1204#[doc = "Power configuration set register"]
1205pub mod pdruncfgset0;
1206#[doc = "Power configuration set register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfgset1](pdruncfgset1) module"]
1207pub type PDRUNCFGSET1 = crate::Reg<u32, _PDRUNCFGSET1>;
1208#[allow(missing_docs)]
1209#[doc(hidden)]
1210pub struct _PDRUNCFGSET1;
1211#[doc = "`read()` method returns [pdruncfgset1::R](pdruncfgset1::R) reader structure"]
1212impl crate::Readable for PDRUNCFGSET1 {}
1213#[doc = "`write(|w| ..)` method takes [pdruncfgset1::W](pdruncfgset1::W) writer structure"]
1214impl crate::Writable for PDRUNCFGSET1 {}
1215#[doc = "Power configuration set register"]
1216pub mod pdruncfgset1;
1217#[doc = "Power configuration clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfgclr0](pdruncfgclr0) module"]
1218pub type PDRUNCFGCLR0 = crate::Reg<u32, _PDRUNCFGCLR0>;
1219#[allow(missing_docs)]
1220#[doc(hidden)]
1221pub struct _PDRUNCFGCLR0;
1222#[doc = "`read()` method returns [pdruncfgclr0::R](pdruncfgclr0::R) reader structure"]
1223impl crate::Readable for PDRUNCFGCLR0 {}
1224#[doc = "`write(|w| ..)` method takes [pdruncfgclr0::W](pdruncfgclr0::W) writer structure"]
1225impl crate::Writable for PDRUNCFGCLR0 {}
1226#[doc = "Power configuration clear register"]
1227pub mod pdruncfgclr0;
1228#[doc = "Power configuration clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdruncfgclr1](pdruncfgclr1) module"]
1229pub type PDRUNCFGCLR1 = crate::Reg<u32, _PDRUNCFGCLR1>;
1230#[allow(missing_docs)]
1231#[doc(hidden)]
1232pub struct _PDRUNCFGCLR1;
1233#[doc = "`read()` method returns [pdruncfgclr1::R](pdruncfgclr1::R) reader structure"]
1234impl crate::Readable for PDRUNCFGCLR1 {}
1235#[doc = "`write(|w| ..)` method takes [pdruncfgclr1::W](pdruncfgclr1::W) writer structure"]
1236impl crate::Writable for PDRUNCFGCLR1 {}
1237#[doc = "Power configuration clear register"]
1238pub mod pdruncfgclr1;
1239#[doc = "Start logic 0 wake-up enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [starter0](starter0) module"]
1240pub type STARTER0 = crate::Reg<u32, _STARTER0>;
1241#[allow(missing_docs)]
1242#[doc(hidden)]
1243pub struct _STARTER0;
1244#[doc = "`read()` method returns [starter0::R](starter0::R) reader structure"]
1245impl crate::Readable for STARTER0 {}
1246#[doc = "`write(|w| ..)` method takes [starter0::W](starter0::W) writer structure"]
1247impl crate::Writable for STARTER0 {}
1248#[doc = "Start logic 0 wake-up enable register"]
1249pub mod starter0;
1250#[doc = "Start logic 0 wake-up enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [starter1](starter1) module"]
1251pub type STARTER1 = crate::Reg<u32, _STARTER1>;
1252#[allow(missing_docs)]
1253#[doc(hidden)]
1254pub struct _STARTER1;
1255#[doc = "`read()` method returns [starter1::R](starter1::R) reader structure"]
1256impl crate::Readable for STARTER1 {}
1257#[doc = "`write(|w| ..)` method takes [starter1::W](starter1::W) writer structure"]
1258impl crate::Writable for STARTER1 {}
1259#[doc = "Start logic 0 wake-up enable register"]
1260pub mod starter1;
1261#[doc = "Set bits in STARTER\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [starterset](starterset) module"]
1262pub type STARTERSET = crate::Reg<u32, _STARTERSET>;
1263#[allow(missing_docs)]
1264#[doc(hidden)]
1265pub struct _STARTERSET;
1266#[doc = "`write(|w| ..)` method takes [starterset::W](starterset::W) writer structure"]
1267impl crate::Writable for STARTERSET {}
1268#[doc = "Set bits in STARTER"]
1269pub mod starterset;
1270#[doc = "Clear bits in STARTER0\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [starterclr](starterclr) module"]
1271pub type STARTERCLR = crate::Reg<u32, _STARTERCLR>;
1272#[allow(missing_docs)]
1273#[doc(hidden)]
1274pub struct _STARTERCLR;
1275#[doc = "`write(|w| ..)` method takes [starterclr::W](starterclr::W) writer structure"]
1276impl crate::Writable for STARTERCLR {}
1277#[doc = "Clear bits in STARTER0"]
1278pub mod starterclr;
1279#[doc = "Configures special cases of hardware wake-up\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hwwake](hwwake) module"]
1280pub type HWWAKE = crate::Reg<u32, _HWWAKE>;
1281#[allow(missing_docs)]
1282#[doc(hidden)]
1283pub struct _HWWAKE;
1284#[doc = "`read()` method returns [hwwake::R](hwwake::R) reader structure"]
1285impl crate::Readable for HWWAKE {}
1286#[doc = "`write(|w| ..)` method takes [hwwake::W](hwwake::W) writer structure"]
1287impl crate::Writable for HWWAKE {}
1288#[doc = "Configures special cases of hardware wake-up"]
1289pub mod hwwake;
1290#[doc = "Auto Clock-Gate Override Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [autocgor](autocgor) module"]
1291pub type AUTOCGOR = crate::Reg<u32, _AUTOCGOR>;
1292#[allow(missing_docs)]
1293#[doc(hidden)]
1294pub struct _AUTOCGOR;
1295#[doc = "`read()` method returns [autocgor::R](autocgor::R) reader structure"]
1296impl crate::Readable for AUTOCGOR {}
1297#[doc = "`write(|w| ..)` method takes [autocgor::W](autocgor::W) writer structure"]
1298impl crate::Writable for AUTOCGOR {}
1299#[doc = "Auto Clock-Gate Override Register"]
1300pub mod autocgor;
1301#[doc = "JTAG ID code register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jtagidcode](jtagidcode) module"]
1302pub type JTAGIDCODE = crate::Reg<u32, _JTAGIDCODE>;
1303#[allow(missing_docs)]
1304#[doc(hidden)]
1305pub struct _JTAGIDCODE;
1306#[doc = "`read()` method returns [jtagidcode::R](jtagidcode::R) reader structure"]
1307impl crate::Readable for JTAGIDCODE {}
1308#[doc = "JTAG ID code register"]
1309pub mod jtagidcode;
1310#[doc = "Part ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [device_id0](device_id0) module"]
1311pub type DEVICE_ID0 = crate::Reg<u32, _DEVICE_ID0>;
1312#[allow(missing_docs)]
1313#[doc(hidden)]
1314pub struct _DEVICE_ID0;
1315#[doc = "`read()` method returns [device_id0::R](device_id0::R) reader structure"]
1316impl crate::Readable for DEVICE_ID0 {}
1317#[doc = "Part ID register"]
1318pub mod device_id0;
1319#[doc = "Boot ROM and die revision register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [device_id1](device_id1) module"]
1320pub type DEVICE_ID1 = crate::Reg<u32, _DEVICE_ID1>;
1321#[allow(missing_docs)]
1322#[doc(hidden)]
1323pub struct _DEVICE_ID1;
1324#[doc = "`read()` method returns [device_id1::R](device_id1::R) reader structure"]
1325impl crate::Readable for DEVICE_ID1 {}
1326#[doc = "Boot ROM and die revision register"]
1327pub mod device_id1;
1328#[doc = "Brown-Out Detect control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodctrl](bodctrl) module"]
1329pub type BODCTRL = crate::Reg<u32, _BODCTRL>;
1330#[allow(missing_docs)]
1331#[doc(hidden)]
1332pub struct _BODCTRL;
1333#[doc = "`read()` method returns [bodctrl::R](bodctrl::R) reader structure"]
1334impl crate::Readable for BODCTRL {}
1335#[doc = "`write(|w| ..)` method takes [bodctrl::W](bodctrl::W) writer structure"]
1336impl crate::Writable for BODCTRL {}
1337#[doc = "Brown-Out Detect control"]
1338pub mod bodctrl;