lpc54606_pac/spifi0/
climit.rs

1#[doc = "Reader of register CLIMIT"]
2pub type R = crate::R<u32, super::CLIMIT>;
3#[doc = "Writer for register CLIMIT"]
4pub type W = crate::W<u32, super::CLIMIT>;
5#[doc = "Register CLIMIT `reset()`'s with value 0x0800_0000"]
6impl crate::ResetValue for super::CLIMIT {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0800_0000
11    }
12}
13#[doc = "Reader of field `CLIMIT`"]
14pub type CLIMIT_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `CLIMIT`"]
16pub struct CLIMIT_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CLIMIT_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:31 - Zero-based upper limit of cacheable memory"]
29    #[inline(always)]
30    pub fn climit(&self) -> CLIMIT_R {
31        CLIMIT_R::new((self.bits & 0xffff_ffff) as u32)
32    }
33}
34impl W {
35    #[doc = "Bits 0:31 - Zero-based upper limit of cacheable memory"]
36    #[inline(always)]
37    pub fn climit(&mut self) -> CLIMIT_W {
38        CLIMIT_W { w: self }
39    }
40}
lpc54606_pac/spifi0/climit.rs

lpc54606_pac/spifi0/
climit.rs
