lpc54606_pac/i2s0/
fifointenset.rs

1#[doc = "Reader of register FIFOINTENSET"]
2pub type R = crate::R<u32, super::FIFOINTENSET>;
3#[doc = "Writer for register FIFOINTENSET"]
4pub type W = crate::W<u32, super::FIFOINTENSET>;
5#[doc = "Register FIFOINTENSET `reset()`'s with value 0"]
6impl crate::ResetValue for super::FIFOINTENSET {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum TXERR_A {
16    #[doc = "0: No interrupt will be generated for a transmit error."]
17    DISABLED = 0,
18    #[doc = "1: An interrupt will be generated when a transmit error occurs."]
19    ENABLED = 1,
20}
21impl From<TXERR_A> for bool {
22    #[inline(always)]
23    fn from(variant: TXERR_A) -> Self {
24        variant as u8 != 0
25    }
26}
27#[doc = "Reader of field `TXERR`"]
28pub type TXERR_R = crate::R<bool, TXERR_A>;
29impl TXERR_R {
30    #[doc = r"Get enumerated values variant"]
31    #[inline(always)]
32    pub fn variant(&self) -> TXERR_A {
33        match self.bits {
34            false => TXERR_A::DISABLED,
35            true => TXERR_A::ENABLED,
36        }
37    }
38    #[doc = "Checks if the value of the field is `DISABLED`"]
39    #[inline(always)]
40    pub fn is_disabled(&self) -> bool {
41        *self == TXERR_A::DISABLED
42    }
43    #[doc = "Checks if the value of the field is `ENABLED`"]
44    #[inline(always)]
45    pub fn is_enabled(&self) -> bool {
46        *self == TXERR_A::ENABLED
47    }
48}
49#[doc = "Write proxy for field `TXERR`"]
50pub struct TXERR_W<'a> {
51    w: &'a mut W,
52}
53impl<'a> TXERR_W<'a> {
54    #[doc = r"Writes `variant` to the field"]
55    #[inline(always)]
56    pub fn variant(self, variant: TXERR_A) -> &'a mut W {
57        {
58            self.bit(variant.into())
59        }
60    }
61    #[doc = "No interrupt will be generated for a transmit error."]
62    #[inline(always)]
63    pub fn disabled(self) -> &'a mut W {
64        self.variant(TXERR_A::DISABLED)
65    }
66    #[doc = "An interrupt will be generated when a transmit error occurs."]
67    #[inline(always)]
68    pub fn enabled(self) -> &'a mut W {
69        self.variant(TXERR_A::ENABLED)
70    }
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
85        self.w
86    }
87}
88#[doc = "Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\n\nValue on reset: 0"]
89#[derive(Clone, Copy, Debug, PartialEq)]
90pub enum RXERR_A {
91    #[doc = "0: No interrupt will be generated for a receive error."]
92    DISABLED = 0,
93    #[doc = "1: An interrupt will be generated when a receive error occurs."]
94    ENABLED = 1,
95}
96impl From<RXERR_A> for bool {
97    #[inline(always)]
98    fn from(variant: RXERR_A) -> Self {
99        variant as u8 != 0
100    }
101}
102#[doc = "Reader of field `RXERR`"]
103pub type RXERR_R = crate::R<bool, RXERR_A>;
104impl RXERR_R {
105    #[doc = r"Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> RXERR_A {
108        match self.bits {
109            false => RXERR_A::DISABLED,
110            true => RXERR_A::ENABLED,
111        }
112    }
113    #[doc = "Checks if the value of the field is `DISABLED`"]
114    #[inline(always)]
115    pub fn is_disabled(&self) -> bool {
116        *self == RXERR_A::DISABLED
117    }
118    #[doc = "Checks if the value of the field is `ENABLED`"]
119    #[inline(always)]
120    pub fn is_enabled(&self) -> bool {
121        *self == RXERR_A::ENABLED
122    }
123}
124#[doc = "Write proxy for field `RXERR`"]
125pub struct RXERR_W<'a> {
126    w: &'a mut W,
127}
128impl<'a> RXERR_W<'a> {
129    #[doc = r"Writes `variant` to the field"]
130    #[inline(always)]
131    pub fn variant(self, variant: RXERR_A) -> &'a mut W {
132        {
133            self.bit(variant.into())
134        }
135    }
136    #[doc = "No interrupt will be generated for a receive error."]
137    #[inline(always)]
138    pub fn disabled(self) -> &'a mut W {
139        self.variant(RXERR_A::DISABLED)
140    }
141    #[doc = "An interrupt will be generated when a receive error occurs."]
142    #[inline(always)]
143    pub fn enabled(self) -> &'a mut W {
144        self.variant(RXERR_A::ENABLED)
145    }
146    #[doc = r"Sets the field bit"]
147    #[inline(always)]
148    pub fn set_bit(self) -> &'a mut W {
149        self.bit(true)
150    }
151    #[doc = r"Clears the field bit"]
152    #[inline(always)]
153    pub fn clear_bit(self) -> &'a mut W {
154        self.bit(false)
155    }
156    #[doc = r"Writes raw bits to the field"]
157    #[inline(always)]
158    pub fn bit(self, value: bool) -> &'a mut W {
159        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
160        self.w
161    }
162}
163#[doc = "Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\n\nValue on reset: 0"]
164#[derive(Clone, Copy, Debug, PartialEq)]
165pub enum TXLVL_A {
166    #[doc = "0: No interrupt will be generated based on the TX FIFO level."]
167    DISABLED = 0,
168    #[doc = "1: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register."]
169    ENABLED = 1,
170}
171impl From<TXLVL_A> for bool {
172    #[inline(always)]
173    fn from(variant: TXLVL_A) -> Self {
174        variant as u8 != 0
175    }
176}
177#[doc = "Reader of field `TXLVL`"]
178pub type TXLVL_R = crate::R<bool, TXLVL_A>;
179impl TXLVL_R {
180    #[doc = r"Get enumerated values variant"]
181    #[inline(always)]
182    pub fn variant(&self) -> TXLVL_A {
183        match self.bits {
184            false => TXLVL_A::DISABLED,
185            true => TXLVL_A::ENABLED,
186        }
187    }
188    #[doc = "Checks if the value of the field is `DISABLED`"]
189    #[inline(always)]
190    pub fn is_disabled(&self) -> bool {
191        *self == TXLVL_A::DISABLED
192    }
193    #[doc = "Checks if the value of the field is `ENABLED`"]
194    #[inline(always)]
195    pub fn is_enabled(&self) -> bool {
196        *self == TXLVL_A::ENABLED
197    }
198}
199#[doc = "Write proxy for field `TXLVL`"]
200pub struct TXLVL_W<'a> {
201    w: &'a mut W,
202}
203impl<'a> TXLVL_W<'a> {
204    #[doc = r"Writes `variant` to the field"]
205    #[inline(always)]
206    pub fn variant(self, variant: TXLVL_A) -> &'a mut W {
207        {
208            self.bit(variant.into())
209        }
210    }
211    #[doc = "No interrupt will be generated based on the TX FIFO level."]
212    #[inline(always)]
213    pub fn disabled(self) -> &'a mut W {
214        self.variant(TXLVL_A::DISABLED)
215    }
216    #[doc = "If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register."]
217    #[inline(always)]
218    pub fn enabled(self) -> &'a mut W {
219        self.variant(TXLVL_A::ENABLED)
220    }
221    #[doc = r"Sets the field bit"]
222    #[inline(always)]
223    pub fn set_bit(self) -> &'a mut W {
224        self.bit(true)
225    }
226    #[doc = r"Clears the field bit"]
227    #[inline(always)]
228    pub fn clear_bit(self) -> &'a mut W {
229        self.bit(false)
230    }
231    #[doc = r"Writes raw bits to the field"]
232    #[inline(always)]
233    pub fn bit(self, value: bool) -> &'a mut W {
234        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
235        self.w
236    }
237}
238#[doc = "Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\n\nValue on reset: 0"]
239#[derive(Clone, Copy, Debug, PartialEq)]
240pub enum RXLVL_A {
241    #[doc = "0: No interrupt will be generated based on the RX FIFO level."]
242    DISABLED = 0,
243    #[doc = "1: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register."]
244    ENABLED = 1,
245}
246impl From<RXLVL_A> for bool {
247    #[inline(always)]
248    fn from(variant: RXLVL_A) -> Self {
249        variant as u8 != 0
250    }
251}
252#[doc = "Reader of field `RXLVL`"]
253pub type RXLVL_R = crate::R<bool, RXLVL_A>;
254impl RXLVL_R {
255    #[doc = r"Get enumerated values variant"]
256    #[inline(always)]
257    pub fn variant(&self) -> RXLVL_A {
258        match self.bits {
259            false => RXLVL_A::DISABLED,
260            true => RXLVL_A::ENABLED,
261        }
262    }
263    #[doc = "Checks if the value of the field is `DISABLED`"]
264    #[inline(always)]
265    pub fn is_disabled(&self) -> bool {
266        *self == RXLVL_A::DISABLED
267    }
268    #[doc = "Checks if the value of the field is `ENABLED`"]
269    #[inline(always)]
270    pub fn is_enabled(&self) -> bool {
271        *self == RXLVL_A::ENABLED
272    }
273}
274#[doc = "Write proxy for field `RXLVL`"]
275pub struct RXLVL_W<'a> {
276    w: &'a mut W,
277}
278impl<'a> RXLVL_W<'a> {
279    #[doc = r"Writes `variant` to the field"]
280    #[inline(always)]
281    pub fn variant(self, variant: RXLVL_A) -> &'a mut W {
282        {
283            self.bit(variant.into())
284        }
285    }
286    #[doc = "No interrupt will be generated based on the RX FIFO level."]
287    #[inline(always)]
288    pub fn disabled(self) -> &'a mut W {
289        self.variant(RXLVL_A::DISABLED)
290    }
291    #[doc = "If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register."]
292    #[inline(always)]
293    pub fn enabled(self) -> &'a mut W {
294        self.variant(RXLVL_A::ENABLED)
295    }
296    #[doc = r"Sets the field bit"]
297    #[inline(always)]
298    pub fn set_bit(self) -> &'a mut W {
299        self.bit(true)
300    }
301    #[doc = r"Clears the field bit"]
302    #[inline(always)]
303    pub fn clear_bit(self) -> &'a mut W {
304        self.bit(false)
305    }
306    #[doc = r"Writes raw bits to the field"]
307    #[inline(always)]
308    pub fn bit(self, value: bool) -> &'a mut W {
309        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
310        self.w
311    }
312}
313impl R {
314    #[doc = "Bit 0 - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register."]
315    #[inline(always)]
316    pub fn txerr(&self) -> TXERR_R {
317        TXERR_R::new((self.bits & 0x01) != 0)
318    }
319    #[doc = "Bit 1 - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register."]
320    #[inline(always)]
321    pub fn rxerr(&self) -> RXERR_R {
322        RXERR_R::new(((self.bits >> 1) & 0x01) != 0)
323    }
324    #[doc = "Bit 2 - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register."]
325    #[inline(always)]
326    pub fn txlvl(&self) -> TXLVL_R {
327        TXLVL_R::new(((self.bits >> 2) & 0x01) != 0)
328    }
329    #[doc = "Bit 3 - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register."]
330    #[inline(always)]
331    pub fn rxlvl(&self) -> RXLVL_R {
332        RXLVL_R::new(((self.bits >> 3) & 0x01) != 0)
333    }
334}
335impl W {
336    #[doc = "Bit 0 - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register."]
337    #[inline(always)]
338    pub fn txerr(&mut self) -> TXERR_W {
339        TXERR_W { w: self }
340    }
341    #[doc = "Bit 1 - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register."]
342    #[inline(always)]
343    pub fn rxerr(&mut self) -> RXERR_W {
344        RXERR_W { w: self }
345    }
346    #[doc = "Bit 2 - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register."]
347    #[inline(always)]
348    pub fn txlvl(&mut self) -> TXLVL_W {
349        TXLVL_W { w: self }
350    }
351    #[doc = "Bit 3 - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register."]
352    #[inline(always)]
353    pub fn rxlvl(&mut self) -> RXLVL_W {
354        RXLVL_W { w: self }
355    }
356}
lpc54606_pac/i2s0/fifointenset.rs

lpc54606_pac/i2s0/
fifointenset.rs
