lpc54606_pac/dma0/
intenclr0.rs

1#[doc = "Writer for register INTENCLR0"]
2pub type W = crate::W<u32, super::INTENCLR0>;
3#[doc = "Register INTENCLR0 `reset()`'s with value 0"]
4impl crate::ResetValue for super::INTENCLR0 {
5    type Type = u32;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `CLR`"]
12pub struct CLR_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> CLR_W<'a> {
16    #[doc = r"Writes raw bits to the field"]
17    #[inline(always)]
18    pub unsafe fn bits(self, value: u32) -> &'a mut W {
19        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
20        self.w
21    }
22}
23impl W {
24    #[doc = "Bits 0:31 - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."]
25    #[inline(always)]
26    pub fn clr(&mut self) -> CLR_W {
27        CLR_W { w: self }
28    }
29}