Module lpc43xx::cgu
[−]
[src]
Clock Generation Unit (CGU)
Modules
| base_apb1_clk |
Output stage BASE_APB1_CLK control register |
| base_apb3_clk |
Output stage BASE_APB3_CLK control register |
| base_audio_clk |
Output stage 25 control register for base clock BASE_AUDIO_CLK |
| base_cgu_out0_clk |
Output stage 25 control register for base clock BASE_CGU_OUT0_CLK |
| base_cgu_out1_clk |
Output stage 25 control register for base clock BASE_CGU_OUT1_CLK |
| base_lcd_clk |
Output stage BASE_LCD_CLK control register |
| base_m4_clk |
Output stage BASE_M4_CLK control register |
| base_out_clk |
Output stage 20 control register for base clock BASE_OUT_CLK |
| base_periph_clk |
Output stage 2 control register for base clock BASE_PERIPH_CLK |
| base_phy_rx_clk |
Output stage BASE_PHY_RX_CLK control register |
| base_phy_tx_clk |
Output stage BASE_PHY_TX_CLK control register |
| base_safe_clk |
Output stage 0 control register for base clock BASE_SAFE_CLK |
| base_sdio_clk |
Output stage BASE_SDIO_CLK control register |
| base_spi_clk |
Output stage BASE_SPI_CLK control register |
| base_spifi_clk |
Output stage BASE_SPIFI_CLK control register |
| base_ssp0_clk |
Output stage BASE_SSP0_CLK control register |
| base_ssp1_clk |
Output stage BASE_SSP1_CLK control register |
| base_uart0_clk |
Output stage BASE_UART0_CLK control register |
| base_uart1_clk |
Output stage BASE_UART1_CLK control register |
| base_uart2_clk |
Output stage BASE_UART2_CLK control register |
| base_uart3_clk |
Output stage BASE_UART3_CLK control register |
| base_usb0_clk |
Output stage 1 control register for base clock BASE_USB0_CLK |
| base_usb1_clk |
Output stage 3 control register for base clock BASE_USB1_CLK |
| freq_mon |
Frequency monitor register |
| idiva_ctrl |
Integer divider A control register |
| idivb_ctrl |
Integer divider B control register |
| idivc_ctrl |
Integer divider C control register |
| idivd_ctrl |
Integer divider D control register |
| idive_ctrl |
Integer divider E control register |
| pll0audio_ctrl |
PLL0AUDIO control register |
| pll0audio_frac |
PLL0AUDIO fractional divider register |
| pll0audio_mdiv |
PLL0AUDIO M-divider register |
| pll0audio_np_div |
PLL0AUDIO N/P-divider register |
| pll0audio_stat |
PLL0AUDIO status register |
| pll0usb_ctrl |
PLL0USB control register |
| pll0usb_mdiv |
PLL0USB M-divider register |
| pll0usb_np_div |
PLL0USB N/P-divider register |
| pll0usb_stat |
PLL0USB status register |
| pll1_ctrl |
PLL1 control register |
| pll1_stat |
PLL1 status register |
| xtal_osc_ctrl |
Crystal oscillator control register |
Structs
| BASE_APB1_CLK |
Output stage BASE_APB1_CLK control register |
| BASE_APB3_CLK |
Output stage BASE_APB3_CLK control register |
| BASE_AUDIO_CLK |
Output stage 25 control register for base clock BASE_AUDIO_CLK |
| BASE_CGU_OUT0_CLK |
Output stage 25 control register for base clock BASE_CGU_OUT0_CLK |
| BASE_CGU_OUT1_CLK |
Output stage 25 control register for base clock BASE_CGU_OUT1_CLK |
| BASE_LCD_CLK |
Output stage BASE_LCD_CLK control register |
| BASE_M4_CLK |
Output stage BASE_M4_CLK control register |
| BASE_OUT_CLK |
Output stage 20 control register for base clock BASE_OUT_CLK |
| BASE_PERIPH_CLK |
Output stage 2 control register for base clock BASE_PERIPH_CLK |
| BASE_PHY_RX_CLK |
Output stage BASE_PHY_RX_CLK control register |
| BASE_PHY_TX_CLK |
Output stage BASE_PHY_TX_CLK control register |
| BASE_SAFE_CLK |
Output stage 0 control register for base clock BASE_SAFE_CLK |
| BASE_SDIO_CLK |
Output stage BASE_SDIO_CLK control register |
| BASE_SPIFI_CLK |
Output stage BASE_SPIFI_CLK control register |
| BASE_SPI_CLK |
Output stage BASE_SPI_CLK control register |
| BASE_SSP0_CLK |
Output stage BASE_SSP0_CLK control register |
| BASE_SSP1_CLK |
Output stage BASE_SSP1_CLK control register |
| BASE_UART0_CLK |
Output stage BASE_UART0_CLK control register |
| BASE_UART1_CLK |
Output stage BASE_UART1_CLK control register |
| BASE_UART2_CLK |
Output stage BASE_UART2_CLK control register |
| BASE_UART3_CLK |
Output stage BASE_UART3_CLK control register |
| BASE_USB0_CLK |
Output stage 1 control register for base clock BASE_USB0_CLK |
| BASE_USB1_CLK |
Output stage 3 control register for base clock BASE_USB1_CLK |
| FREQ_MON |
Frequency monitor register |
| IDIVA_CTRL |
Integer divider A control register |
| IDIVB_CTRL |
Integer divider B control register |
| IDIVC_CTRL |
Integer divider C control register |
| IDIVD_CTRL |
Integer divider D control register |
| IDIVE_CTRL |
Integer divider E control register |
| PLL0AUDIO_CTRL |
PLL0AUDIO control register |
| PLL0AUDIO_FRAC |
PLL0AUDIO fractional divider register |
| PLL0AUDIO_MDIV |
PLL0AUDIO M-divider register |
| PLL0AUDIO_NP_DIV |
PLL0AUDIO N/P-divider register |
| PLL0AUDIO_STAT |
PLL0AUDIO status register |
| PLL0USB_CTRL |
PLL0USB control register |
| PLL0USB_MDIV |
PLL0USB M-divider register |
| PLL0USB_NP_DIV |
PLL0USB N/P-divider register |
| PLL0USB_STAT |
PLL0USB status register |
| PLL1_CTRL |
PLL1 control register |
| PLL1_STAT |
PLL1 status register |
| RegisterBlock |
Register block |
| XTAL_OSC_CTRL |
Crystal oscillator control register |