Module lpc43xx::cgu::base_out_clk [] [src]

Output stage 20 control register for base clock BASE_OUT_CLK

Structs

R

Value read from the register

W

Value to write to the register

_AUTOBLOCKW

Proxy

_CLK_SELW

Proxy

_PDW

Proxy

Enums

AUTOBLOCKR

Possible values of the field AUTOBLOCK

AUTOBLOCKW

Values that can be written to the field AUTOBLOCK

CLK_SELR

Possible values of the field CLK_SEL

CLK_SELW

Values that can be written to the field CLK_SEL

PDR

Possible values of the field PD

PDW

Values that can be written to the field PD