Struct lpc176x_5x::spi::cr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn bitenable(&self) -> BITENABLER

Bit 2 - The SPI controller sends and receives 8 bits of data per transfer.

pub fn cpha(&self) -> CPHAR

Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.

pub fn cpol(&self) -> CPOLR

Bit 4 - Clock polarity control.

pub fn mstr(&self) -> MSTRR

Bit 5 - Master mode select.

pub fn lsbf(&self) -> LSBFR

Bit 6 - LSB First controls which direction each byte is shifted when transferred.

pub fn spie(&self) -> SPIER

Bit 7 - Serial peripheral interrupt enable.

pub fn bits_(&self) -> BITSR

Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer: