Struct lpc176x_5x::i2s::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dao: DAO,
    pub dai: DAI,
    pub txfifo: TXFIFO,
    pub rxfifo: RXFIFO,
    pub state: STATE,
    pub dma1: DMA1,
    pub dma2: DMA2,
    pub irq: IRQ,
    pub txrate: TXRATE,
    pub rxrate: RXRATE,
    pub txbitrate: TXBITRATE,
    pub rxbitrate: RXBITRATE,
    pub txmode: TXMODE,
    pub rxmode: RXMODE,
}

Register block

Fields

dao: DAO

0x00 - I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.

dai: DAI

0x04 - I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.

txfifo: TXFIFO

0x08 - I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.

rxfifo: RXFIFO

0x0c - I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.

state: STATE

0x10 - I2S Status Feedback Register. Contains status information about the I2S interface.

dma1: DMA1

0x14 - I2S DMA Configuration Register 1. Contains control information for DMA request 1.

dma2: DMA2

0x18 - I2S DMA Configuration Register 2. Contains control information for DMA request 2.

irq: IRQ

0x1c - I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.

txrate: TXRATE

0x20 - I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.

rxrate: RXRATE

0x24 - I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.

txbitrate: TXBITRATE

0x28 - I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.

rxbitrate: RXBITRATE

0x2c - I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.

txmode: TXMODE

0x30 - I2S Transmit mode control.

rxmode: RXMODE

0x34 - I2S Receive mode control.