[−][src]Module lpc176x_5x::i2c0::scll
SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
Structs
R | Value read from the register |
SCLLR | Value of the field |
W | Value to write to the register |
_SCLLW | Proxy |