lpc13xx_pac/lpc1313/
syscon.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - System memory remap"]
5    pub sysmemremap: SYSMEMREMAP,
6    #[doc = "0x04 - Peripheral reset control"]
7    pub presetctrl: PRESETCTRL,
8    #[doc = "0x08 - System PLL control"]
9    pub syspllctrl: SYSPLLCTRL,
10    #[doc = "0x0c - System PLL status"]
11    pub syspllstat: SYSPLLSTAT,
12    #[doc = "0x10 - USB PLL control"]
13    pub usbpllctrl: USBPLLCTRL,
14    #[doc = "0x14 - USB PLL status"]
15    pub usbpllstat: USBPLLSTAT,
16    _reserved6: [u8; 0x08],
17    #[doc = "0x20 - System oscillator control"]
18    pub sysoscctrl: SYSOSCCTRL,
19    #[doc = "0x24 - Watchdog oscillator control"]
20    pub wdtoscctrl: WDTOSCCTRL,
21    #[doc = "0x28 - IRC control"]
22    pub ircctrl: IRCCTRL,
23    _reserved9: [u8; 0x04],
24    #[doc = "0x30 - System reset status register"]
25    pub sysresstat: SYSRESSTAT,
26    _reserved10: [u8; 0x0c],
27    #[doc = "0x40 - System PLL clock source select"]
28    pub syspllclksel: SYSPLLCLKSEL,
29    #[doc = "0x44 - System PLL clock source update enable"]
30    pub syspllclkuen: SYSPLLCLKUEN,
31    #[doc = "0x48 - USB PLL clock source select"]
32    pub usbpllclksel: USBPLLCLKSEL,
33    #[doc = "0x4c - USB PLL clock source update enable"]
34    pub usbpllclkuen: USBPLLCLKUEN,
35    _reserved14: [u8; 0x20],
36    #[doc = "0x70 - Main clock source select"]
37    pub mainclksel: MAINCLKSEL,
38    #[doc = "0x74 - Main clock source update enable"]
39    pub mainclkuen: MAINCLKUEN,
40    #[doc = "0x78 - System AHB clock divider"]
41    pub sysahbclkdiv: SYSAHBCLKDIV,
42    _reserved17: [u8; 0x04],
43    #[doc = "0x80 - System AHB clock control"]
44    pub sysahbclkctrl: SYSAHBCLKCTRL,
45    _reserved18: [u8; 0x10],
46    #[doc = "0x94 - SSP clock divder"]
47    pub ssp0clkdiv: SSP0CLKDIV,
48    #[doc = "0x98 - UART clock divder"]
49    pub uartclkdiv: UARTCLKDIV,
50    #[doc = "0x9c - SPISP1 clock divder"]
51    pub ssp1clkdiv: SSP1CLKDIV,
52    _reserved21: [u8; 0x0c],
53    #[doc = "0xac - ARM trace clock divider"]
54    pub traceclkdiv: TRACECLKDIV,
55    #[doc = "0xb0 - SYSTICK clock divder"]
56    pub systickclkdiv: SYSTICKCLKDIV,
57    _reserved23: [u8; 0x0c],
58    #[doc = "0xc0 - USB clock source select"]
59    pub usbclksel: USBCLKSEL,
60    #[doc = "0xc4 - USB clock source update enable"]
61    pub usbclkuen: USBCLKUEN,
62    #[doc = "0xc8 - USB clock source divider"]
63    pub usbclkdiv: USBCLKDIV,
64    _reserved26: [u8; 0x04],
65    #[doc = "0xd0 - WDT clock source select"]
66    pub wdtclksel: WDTCLKSEL,
67    #[doc = "0xd4 - WDT clock source update enable"]
68    pub wdtclkuen: WDTCLKUEN,
69    #[doc = "0xd8 - WDT clock divider"]
70    pub wdtclkdiv: WDTCLKDIV,
71    _reserved29: [u8; 0x04],
72    #[doc = "0xe0 - CLKOUT clock source select"]
73    pub clkoutclksel: CLKOUTCLKSEL,
74    #[doc = "0xe4 - CLKOUT clock source update enable"]
75    pub clkoutuen: CLKOUTUEN,
76    #[doc = "0xe8 - CLKOUT clock divider"]
77    pub clkoutdiv: CLKOUTDIV,
78    _reserved32: [u8; 0x14],
79    #[doc = "0x100 - POR captured PIO status 0"]
80    pub pioporcap0: PIOPORCAP0,
81    #[doc = "0x104 - POR captured PIO status 1"]
82    pub pioporcap1: PIOPORCAP1,
83    _reserved34: [u8; 0x48],
84    #[doc = "0x150 - BOD control"]
85    pub bodctrl: BODCTRL,
86    #[doc = "0x154 - System tick counter calibration"]
87    pub systckcal: SYSTCKCAL,
88    _reserved36: [u8; 0xa8],
89    #[doc = "0x200 - Start logic edge control register 0; bottom 32 interrupts"]
90    pub startaprp0: STARTAPRP0,
91    #[doc = "0x204 - Start logic signal enable register 0; bottom 32 interrupts"]
92    pub starterp0: STARTERP0,
93    #[doc = "0x208 - Start logic reset register 0; bottom 32 interrupts"]
94    pub startrsrp0clr: STARTRSRP0CLR,
95    #[doc = "0x20c - Start logic status register 0; bottom 32 interrupts"]
96    pub startsrp0: STARTSRP0,
97    #[doc = "0x210 - Start logic edge control register 1; top 8 interrupts"]
98    pub startaprp1: STARTAPRP1,
99    #[doc = "0x214 - Start logic signal enable register 1; top 8 interrupts"]
100    pub starterp1: STARTERP1,
101    #[doc = "0x218 - Start logic reset register 1; top 8 interrupts"]
102    pub startrsrp1clr: STARTRSRP1CLR,
103    #[doc = "0x21c - Start logic status register 1; top 8 interrupts"]
104    pub startsrp1: STARTSRP1,
105    _reserved44: [u8; 0x10],
106    #[doc = "0x230 - Power-down states in Deep-sleep mode"]
107    pub pdsleepcfg: PDSLEEPCFG,
108    #[doc = "0x234 - Power-down states after wake-up from Deep-sleep mode"]
109    pub pdawakecfg: PDAWAKECFG,
110    #[doc = "0x238 - Power-down configuration register"]
111    pub pdruncfg: PDRUNCFG,
112    _reserved47: [u8; 0x01b8],
113    #[doc = "0x3f4 - Device ID"]
114    pub device_id: DEVICE_ID,
115}
116#[doc = "SYSMEMREMAP (rw) register accessor: an alias for `Reg<SYSMEMREMAP_SPEC>`"]
117pub type SYSMEMREMAP = crate::Reg<sysmemremap::SYSMEMREMAP_SPEC>;
118#[doc = "System memory remap"]
119pub mod sysmemremap;
120#[doc = "PRESETCTRL (rw) register accessor: an alias for `Reg<PRESETCTRL_SPEC>`"]
121pub type PRESETCTRL = crate::Reg<presetctrl::PRESETCTRL_SPEC>;
122#[doc = "Peripheral reset control"]
123pub mod presetctrl;
124#[doc = "SYSPLLCTRL (rw) register accessor: an alias for `Reg<SYSPLLCTRL_SPEC>`"]
125pub type SYSPLLCTRL = crate::Reg<syspllctrl::SYSPLLCTRL_SPEC>;
126#[doc = "System PLL control"]
127pub mod syspllctrl;
128#[doc = "SYSPLLSTAT (r) register accessor: an alias for `Reg<SYSPLLSTAT_SPEC>`"]
129pub type SYSPLLSTAT = crate::Reg<syspllstat::SYSPLLSTAT_SPEC>;
130#[doc = "System PLL status"]
131pub mod syspllstat;
132#[doc = "USBPLLCTRL (rw) register accessor: an alias for `Reg<USBPLLCTRL_SPEC>`"]
133pub type USBPLLCTRL = crate::Reg<usbpllctrl::USBPLLCTRL_SPEC>;
134#[doc = "USB PLL control"]
135pub mod usbpllctrl;
136#[doc = "USBPLLSTAT (r) register accessor: an alias for `Reg<USBPLLSTAT_SPEC>`"]
137pub type USBPLLSTAT = crate::Reg<usbpllstat::USBPLLSTAT_SPEC>;
138#[doc = "USB PLL status"]
139pub mod usbpllstat;
140#[doc = "SYSOSCCTRL (rw) register accessor: an alias for `Reg<SYSOSCCTRL_SPEC>`"]
141pub type SYSOSCCTRL = crate::Reg<sysoscctrl::SYSOSCCTRL_SPEC>;
142#[doc = "System oscillator control"]
143pub mod sysoscctrl;
144#[doc = "WDTOSCCTRL (rw) register accessor: an alias for `Reg<WDTOSCCTRL_SPEC>`"]
145pub type WDTOSCCTRL = crate::Reg<wdtoscctrl::WDTOSCCTRL_SPEC>;
146#[doc = "Watchdog oscillator control"]
147pub mod wdtoscctrl;
148#[doc = "IRCCTRL (rw) register accessor: an alias for `Reg<IRCCTRL_SPEC>`"]
149pub type IRCCTRL = crate::Reg<ircctrl::IRCCTRL_SPEC>;
150#[doc = "IRC control"]
151pub mod ircctrl;
152#[doc = "SYSRESSTAT (r) register accessor: an alias for `Reg<SYSRESSTAT_SPEC>`"]
153pub type SYSRESSTAT = crate::Reg<sysresstat::SYSRESSTAT_SPEC>;
154#[doc = "System reset status register"]
155pub mod sysresstat;
156#[doc = "SYSPLLCLKSEL (rw) register accessor: an alias for `Reg<SYSPLLCLKSEL_SPEC>`"]
157pub type SYSPLLCLKSEL = crate::Reg<syspllclksel::SYSPLLCLKSEL_SPEC>;
158#[doc = "System PLL clock source select"]
159pub mod syspllclksel;
160#[doc = "SYSPLLCLKUEN (rw) register accessor: an alias for `Reg<SYSPLLCLKUEN_SPEC>`"]
161pub type SYSPLLCLKUEN = crate::Reg<syspllclkuen::SYSPLLCLKUEN_SPEC>;
162#[doc = "System PLL clock source update enable"]
163pub mod syspllclkuen;
164#[doc = "USBPLLCLKSEL (rw) register accessor: an alias for `Reg<USBPLLCLKSEL_SPEC>`"]
165pub type USBPLLCLKSEL = crate::Reg<usbpllclksel::USBPLLCLKSEL_SPEC>;
166#[doc = "USB PLL clock source select"]
167pub mod usbpllclksel;
168#[doc = "USBPLLCLKUEN (rw) register accessor: an alias for `Reg<USBPLLCLKUEN_SPEC>`"]
169pub type USBPLLCLKUEN = crate::Reg<usbpllclkuen::USBPLLCLKUEN_SPEC>;
170#[doc = "USB PLL clock source update enable"]
171pub mod usbpllclkuen;
172#[doc = "MAINCLKSEL (rw) register accessor: an alias for `Reg<MAINCLKSEL_SPEC>`"]
173pub type MAINCLKSEL = crate::Reg<mainclksel::MAINCLKSEL_SPEC>;
174#[doc = "Main clock source select"]
175pub mod mainclksel;
176#[doc = "MAINCLKUEN (rw) register accessor: an alias for `Reg<MAINCLKUEN_SPEC>`"]
177pub type MAINCLKUEN = crate::Reg<mainclkuen::MAINCLKUEN_SPEC>;
178#[doc = "Main clock source update enable"]
179pub mod mainclkuen;
180#[doc = "SYSAHBCLKDIV (rw) register accessor: an alias for `Reg<SYSAHBCLKDIV_SPEC>`"]
181pub type SYSAHBCLKDIV = crate::Reg<sysahbclkdiv::SYSAHBCLKDIV_SPEC>;
182#[doc = "System AHB clock divider"]
183pub mod sysahbclkdiv;
184#[doc = "SYSAHBCLKCTRL (rw) register accessor: an alias for `Reg<SYSAHBCLKCTRL_SPEC>`"]
185pub type SYSAHBCLKCTRL = crate::Reg<sysahbclkctrl::SYSAHBCLKCTRL_SPEC>;
186#[doc = "System AHB clock control"]
187pub mod sysahbclkctrl;
188#[doc = "SSP0CLKDIV (rw) register accessor: an alias for `Reg<SSP0CLKDIV_SPEC>`"]
189pub type SSP0CLKDIV = crate::Reg<ssp0clkdiv::SSP0CLKDIV_SPEC>;
190#[doc = "SSP clock divder"]
191pub mod ssp0clkdiv;
192#[doc = "UARTCLKDIV (rw) register accessor: an alias for `Reg<UARTCLKDIV_SPEC>`"]
193pub type UARTCLKDIV = crate::Reg<uartclkdiv::UARTCLKDIV_SPEC>;
194#[doc = "UART clock divder"]
195pub mod uartclkdiv;
196#[doc = "SSP1CLKDIV (rw) register accessor: an alias for `Reg<SSP1CLKDIV_SPEC>`"]
197pub type SSP1CLKDIV = crate::Reg<ssp1clkdiv::SSP1CLKDIV_SPEC>;
198#[doc = "SPISP1 clock divder"]
199pub mod ssp1clkdiv;
200#[doc = "TRACECLKDIV (rw) register accessor: an alias for `Reg<TRACECLKDIV_SPEC>`"]
201pub type TRACECLKDIV = crate::Reg<traceclkdiv::TRACECLKDIV_SPEC>;
202#[doc = "ARM trace clock divider"]
203pub mod traceclkdiv;
204#[doc = "SYSTICKCLKDIV (rw) register accessor: an alias for `Reg<SYSTICKCLKDIV_SPEC>`"]
205pub type SYSTICKCLKDIV = crate::Reg<systickclkdiv::SYSTICKCLKDIV_SPEC>;
206#[doc = "SYSTICK clock divder"]
207pub mod systickclkdiv;
208#[doc = "USBCLKSEL (rw) register accessor: an alias for `Reg<USBCLKSEL_SPEC>`"]
209pub type USBCLKSEL = crate::Reg<usbclksel::USBCLKSEL_SPEC>;
210#[doc = "USB clock source select"]
211pub mod usbclksel;
212#[doc = "USBCLKUEN (rw) register accessor: an alias for `Reg<USBCLKUEN_SPEC>`"]
213pub type USBCLKUEN = crate::Reg<usbclkuen::USBCLKUEN_SPEC>;
214#[doc = "USB clock source update enable"]
215pub mod usbclkuen;
216#[doc = "USBCLKDIV (rw) register accessor: an alias for `Reg<USBCLKDIV_SPEC>`"]
217pub type USBCLKDIV = crate::Reg<usbclkdiv::USBCLKDIV_SPEC>;
218#[doc = "USB clock source divider"]
219pub mod usbclkdiv;
220#[doc = "WDTCLKSEL (rw) register accessor: an alias for `Reg<WDTCLKSEL_SPEC>`"]
221pub type WDTCLKSEL = crate::Reg<wdtclksel::WDTCLKSEL_SPEC>;
222#[doc = "WDT clock source select"]
223pub mod wdtclksel;
224#[doc = "WDTCLKUEN (rw) register accessor: an alias for `Reg<WDTCLKUEN_SPEC>`"]
225pub type WDTCLKUEN = crate::Reg<wdtclkuen::WDTCLKUEN_SPEC>;
226#[doc = "WDT clock source update enable"]
227pub mod wdtclkuen;
228#[doc = "WDTCLKDIV (rw) register accessor: an alias for `Reg<WDTCLKDIV_SPEC>`"]
229pub type WDTCLKDIV = crate::Reg<wdtclkdiv::WDTCLKDIV_SPEC>;
230#[doc = "WDT clock divider"]
231pub mod wdtclkdiv;
232#[doc = "CLKOUTCLKSEL (rw) register accessor: an alias for `Reg<CLKOUTCLKSEL_SPEC>`"]
233pub type CLKOUTCLKSEL = crate::Reg<clkoutclksel::CLKOUTCLKSEL_SPEC>;
234#[doc = "CLKOUT clock source select"]
235pub mod clkoutclksel;
236#[doc = "CLKOUTUEN (rw) register accessor: an alias for `Reg<CLKOUTUEN_SPEC>`"]
237pub type CLKOUTUEN = crate::Reg<clkoutuen::CLKOUTUEN_SPEC>;
238#[doc = "CLKOUT clock source update enable"]
239pub mod clkoutuen;
240#[doc = "CLKOUTDIV (rw) register accessor: an alias for `Reg<CLKOUTDIV_SPEC>`"]
241pub type CLKOUTDIV = crate::Reg<clkoutdiv::CLKOUTDIV_SPEC>;
242#[doc = "CLKOUT clock divider"]
243pub mod clkoutdiv;
244#[doc = "PIOPORCAP0 (r) register accessor: an alias for `Reg<PIOPORCAP0_SPEC>`"]
245pub type PIOPORCAP0 = crate::Reg<pioporcap0::PIOPORCAP0_SPEC>;
246#[doc = "POR captured PIO status 0"]
247pub mod pioporcap0;
248#[doc = "PIOPORCAP1 (r) register accessor: an alias for `Reg<PIOPORCAP1_SPEC>`"]
249pub type PIOPORCAP1 = crate::Reg<pioporcap1::PIOPORCAP1_SPEC>;
250#[doc = "POR captured PIO status 1"]
251pub mod pioporcap1;
252#[doc = "BODCTRL (rw) register accessor: an alias for `Reg<BODCTRL_SPEC>`"]
253pub type BODCTRL = crate::Reg<bodctrl::BODCTRL_SPEC>;
254#[doc = "BOD control"]
255pub mod bodctrl;
256#[doc = "SYSTCKCAL (rw) register accessor: an alias for `Reg<SYSTCKCAL_SPEC>`"]
257pub type SYSTCKCAL = crate::Reg<systckcal::SYSTCKCAL_SPEC>;
258#[doc = "System tick counter calibration"]
259pub mod systckcal;
260#[doc = "STARTAPRP0 (rw) register accessor: an alias for `Reg<STARTAPRP0_SPEC>`"]
261pub type STARTAPRP0 = crate::Reg<startaprp0::STARTAPRP0_SPEC>;
262#[doc = "Start logic edge control register 0; bottom 32 interrupts"]
263pub mod startaprp0;
264#[doc = "STARTERP0 (rw) register accessor: an alias for `Reg<STARTERP0_SPEC>`"]
265pub type STARTERP0 = crate::Reg<starterp0::STARTERP0_SPEC>;
266#[doc = "Start logic signal enable register 0; bottom 32 interrupts"]
267pub mod starterp0;
268#[doc = "STARTRSRP0CLR (w) register accessor: an alias for `Reg<STARTRSRP0CLR_SPEC>`"]
269pub type STARTRSRP0CLR = crate::Reg<startrsrp0clr::STARTRSRP0CLR_SPEC>;
270#[doc = "Start logic reset register 0; bottom 32 interrupts"]
271pub mod startrsrp0clr;
272#[doc = "STARTSRP0 (r) register accessor: an alias for `Reg<STARTSRP0_SPEC>`"]
273pub type STARTSRP0 = crate::Reg<startsrp0::STARTSRP0_SPEC>;
274#[doc = "Start logic status register 0; bottom 32 interrupts"]
275pub mod startsrp0;
276#[doc = "STARTAPRP1 (rw) register accessor: an alias for `Reg<STARTAPRP1_SPEC>`"]
277pub type STARTAPRP1 = crate::Reg<startaprp1::STARTAPRP1_SPEC>;
278#[doc = "Start logic edge control register 1; top 8 interrupts"]
279pub mod startaprp1;
280#[doc = "STARTERP1 (rw) register accessor: an alias for `Reg<STARTERP1_SPEC>`"]
281pub type STARTERP1 = crate::Reg<starterp1::STARTERP1_SPEC>;
282#[doc = "Start logic signal enable register 1; top 8 interrupts"]
283pub mod starterp1;
284#[doc = "STARTRSRP1CLR (w) register accessor: an alias for `Reg<STARTRSRP1CLR_SPEC>`"]
285pub type STARTRSRP1CLR = crate::Reg<startrsrp1clr::STARTRSRP1CLR_SPEC>;
286#[doc = "Start logic reset register 1; top 8 interrupts"]
287pub mod startrsrp1clr;
288#[doc = "STARTSRP1 (r) register accessor: an alias for `Reg<STARTSRP1_SPEC>`"]
289pub type STARTSRP1 = crate::Reg<startsrp1::STARTSRP1_SPEC>;
290#[doc = "Start logic status register 1; top 8 interrupts"]
291pub mod startsrp1;
292#[doc = "PDSLEEPCFG (rw) register accessor: an alias for `Reg<PDSLEEPCFG_SPEC>`"]
293pub type PDSLEEPCFG = crate::Reg<pdsleepcfg::PDSLEEPCFG_SPEC>;
294#[doc = "Power-down states in Deep-sleep mode"]
295pub mod pdsleepcfg;
296#[doc = "PDAWAKECFG (rw) register accessor: an alias for `Reg<PDAWAKECFG_SPEC>`"]
297pub type PDAWAKECFG = crate::Reg<pdawakecfg::PDAWAKECFG_SPEC>;
298#[doc = "Power-down states after wake-up from Deep-sleep mode"]
299pub mod pdawakecfg;
300#[doc = "PDRUNCFG (rw) register accessor: an alias for `Reg<PDRUNCFG_SPEC>`"]
301pub type PDRUNCFG = crate::Reg<pdruncfg::PDRUNCFG_SPEC>;
302#[doc = "Power-down configuration register"]
303pub mod pdruncfg;
304#[doc = "DEVICE_ID (r) register accessor: an alias for `Reg<DEVICE_ID_SPEC>`"]
305pub type DEVICE_ID = crate::Reg<device_id::DEVICE_ID_SPEC>;
306#[doc = "Device ID"]
307pub mod device_id;