lpc13xx_pac/lpc1343/syscon/
syspllctrl.rs

1#[doc = "Register `SYSPLLCTRL` reader"]
2pub struct R(crate::R<SYSPLLCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYSPLLCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYSPLLCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYSPLLCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYSPLLCTRL` writer"]
17pub struct W(crate::W<SYSPLLCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYSPLLCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYSPLLCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYSPLLCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MSEL` reader - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."]
38pub type MSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `MSEL` writer - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."]
40pub type MSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SYSPLLCTRL_SPEC, u8, u8, 5, O>;
41#[doc = "Field `PSEL` reader - Post divider ratio P. The division ratio is 2 x P."]
42pub type PSEL_R = crate::FieldReader<u8, PSEL_A>;
43#[doc = "Post divider ratio P. The division ratio is 2 x P.\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq)]
45#[repr(u8)]
46pub enum PSEL_A {
47    #[doc = "0: P = 1"]
48    P_EQ_1 = 0,
49    #[doc = "1: P = 2"]
50    P_EQ_2 = 1,
51    #[doc = "2: P = 4"]
52    P_EQ_4 = 2,
53    #[doc = "3: P = 8"]
54    P_EQ_8 = 3,
55}
56impl From<PSEL_A> for u8 {
57    #[inline(always)]
58    fn from(variant: PSEL_A) -> Self {
59        variant as _
60    }
61}
62impl PSEL_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> PSEL_A {
66        match self.bits {
67            0 => PSEL_A::P_EQ_1,
68            1 => PSEL_A::P_EQ_2,
69            2 => PSEL_A::P_EQ_4,
70            3 => PSEL_A::P_EQ_8,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Checks if the value of the field is `P_EQ_1`"]
75    #[inline(always)]
76    pub fn is_p_eq_1(&self) -> bool {
77        *self == PSEL_A::P_EQ_1
78    }
79    #[doc = "Checks if the value of the field is `P_EQ_2`"]
80    #[inline(always)]
81    pub fn is_p_eq_2(&self) -> bool {
82        *self == PSEL_A::P_EQ_2
83    }
84    #[doc = "Checks if the value of the field is `P_EQ_4`"]
85    #[inline(always)]
86    pub fn is_p_eq_4(&self) -> bool {
87        *self == PSEL_A::P_EQ_4
88    }
89    #[doc = "Checks if the value of the field is `P_EQ_8`"]
90    #[inline(always)]
91    pub fn is_p_eq_8(&self) -> bool {
92        *self == PSEL_A::P_EQ_8
93    }
94}
95#[doc = "Field `PSEL` writer - Post divider ratio P. The division ratio is 2 x P."]
96pub type PSEL_W<'a, const O: u8> =
97    crate::FieldWriterSafe<'a, u32, SYSPLLCTRL_SPEC, u8, PSEL_A, 2, O>;
98impl<'a, const O: u8> PSEL_W<'a, O> {
99    #[doc = "P = 1"]
100    #[inline(always)]
101    pub fn p_eq_1(self) -> &'a mut W {
102        self.variant(PSEL_A::P_EQ_1)
103    }
104    #[doc = "P = 2"]
105    #[inline(always)]
106    pub fn p_eq_2(self) -> &'a mut W {
107        self.variant(PSEL_A::P_EQ_2)
108    }
109    #[doc = "P = 4"]
110    #[inline(always)]
111    pub fn p_eq_4(self) -> &'a mut W {
112        self.variant(PSEL_A::P_EQ_4)
113    }
114    #[doc = "P = 8"]
115    #[inline(always)]
116    pub fn p_eq_8(self) -> &'a mut W {
117        self.variant(PSEL_A::P_EQ_8)
118    }
119}
120impl R {
121    #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."]
122    #[inline(always)]
123    pub fn msel(&self) -> MSEL_R {
124        MSEL_R::new((self.bits & 0x1f) as u8)
125    }
126    #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."]
127    #[inline(always)]
128    pub fn psel(&self) -> PSEL_R {
129        PSEL_R::new(((self.bits >> 5) & 3) as u8)
130    }
131}
132impl W {
133    #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."]
134    #[inline(always)]
135    pub fn msel(&mut self) -> MSEL_W<0> {
136        MSEL_W::new(self)
137    }
138    #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."]
139    #[inline(always)]
140    pub fn psel(&mut self) -> PSEL_W<5> {
141        PSEL_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.0.bits(bits);
147        self
148    }
149}
150#[doc = "System PLL control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllctrl](index.html) module"]
151pub struct SYSPLLCTRL_SPEC;
152impl crate::RegisterSpec for SYSPLLCTRL_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [syspllctrl::R](R) reader structure"]
156impl crate::Readable for SYSPLLCTRL_SPEC {
157    type Reader = R;
158}
159#[doc = "`write(|w| ..)` method takes [syspllctrl::W](W) writer structure"]
160impl crate::Writable for SYSPLLCTRL_SPEC {
161    type Writer = W;
162}
163#[doc = "`reset()` method sets SYSPLLCTRL to value 0"]
164impl crate::Resettable for SYSPLLCTRL_SPEC {
165    #[inline(always)]
166    fn reset_value() -> Self::Ux {
167        0
168    }
169}
lpc13xx_pac/lpc1343/syscon/syspllctrl.rs

lpc13xx_pac/lpc1343/syscon/
syspllctrl.rs
