lpc13xx_pac/lpc1313/usb/
devintctrl.rs1#[doc = "Register `DEVINTCTRL` writer"]
2pub struct W(crate::W<DEVINTCTRL_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<DEVINTCTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<DEVINTCTRL_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<DEVINTCTRL_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `FRAME_CLR` writer - Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
23pub type FRAME_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
24#[doc = "Field `EP0_CLR` writer - USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
25pub type EP0_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
26#[doc = "Field `EP1_CLR` writer - USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
27pub type EP1_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
28#[doc = "Field `EP2_CLR` writer - USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
29pub type EP2_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
30#[doc = "Field `EP3_CLR` writer - USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
31pub type EP3_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
32#[doc = "Field `EP4_CLR` writer - USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
33pub type EP4_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
34#[doc = "Field `EP5_CLR` writer - USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
35pub type EP5_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
36#[doc = "Field `EP6_CLR` writer - USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
37pub type EP6_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
38#[doc = "Field `EP7_CLR` writer - USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
39pub type EP7_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
40#[doc = "Field `DEV_STAT_CLR` writer - Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
41pub type DEV_STAT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
42#[doc = "Field `CC_EMPTY_CLR` writer - The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
43pub type CC_EMPTY_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
44#[doc = "Field `CD_FULL_CLR` writer - Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
45pub type CD_FULL_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
46#[doc = "Field `RXENDPKT_CLR` writer - The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
47pub type RXENDPKT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
48#[doc = "Field `TXENDPKT_CLR` writer - The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
49pub type TXENDPKT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINTCTRL_SPEC, bool, O>;
50impl W {
51 #[doc = "Bit 0 - Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
52 #[inline(always)]
53 pub fn frame_clr(&mut self) -> FRAME_CLR_W<0> {
54 FRAME_CLR_W::new(self)
55 }
56 #[doc = "Bit 1 - USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
57 #[inline(always)]
58 pub fn ep0_clr(&mut self) -> EP0_CLR_W<1> {
59 EP0_CLR_W::new(self)
60 }
61 #[doc = "Bit 2 - USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
62 #[inline(always)]
63 pub fn ep1_clr(&mut self) -> EP1_CLR_W<2> {
64 EP1_CLR_W::new(self)
65 }
66 #[doc = "Bit 3 - USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
67 #[inline(always)]
68 pub fn ep2_clr(&mut self) -> EP2_CLR_W<3> {
69 EP2_CLR_W::new(self)
70 }
71 #[doc = "Bit 4 - USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
72 #[inline(always)]
73 pub fn ep3_clr(&mut self) -> EP3_CLR_W<4> {
74 EP3_CLR_W::new(self)
75 }
76 #[doc = "Bit 5 - USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
77 #[inline(always)]
78 pub fn ep4_clr(&mut self) -> EP4_CLR_W<5> {
79 EP4_CLR_W::new(self)
80 }
81 #[doc = "Bit 6 - USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
82 #[inline(always)]
83 pub fn ep5_clr(&mut self) -> EP5_CLR_W<6> {
84 EP5_CLR_W::new(self)
85 }
86 #[doc = "Bit 7 - USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
87 #[inline(always)]
88 pub fn ep6_clr(&mut self) -> EP6_CLR_W<7> {
89 EP6_CLR_W::new(self)
90 }
91 #[doc = "Bit 8 - USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
92 #[inline(always)]
93 pub fn ep7_clr(&mut self) -> EP7_CLR_W<8> {
94 EP7_CLR_W::new(self)
95 }
96 #[doc = "Bit 9 - Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
97 #[inline(always)]
98 pub fn dev_stat_clr(&mut self) -> DEV_STAT_CLR_W<9> {
99 DEV_STAT_CLR_W::new(self)
100 }
101 #[doc = "Bit 10 - The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
102 #[inline(always)]
103 pub fn cc_empty_clr(&mut self) -> CC_EMPTY_CLR_W<10> {
104 CC_EMPTY_CLR_W::new(self)
105 }
106 #[doc = "Bit 11 - Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
107 #[inline(always)]
108 pub fn cd_full_clr(&mut self) -> CD_FULL_CLR_W<11> {
109 CD_FULL_CLR_W::new(self)
110 }
111 #[doc = "Bit 12 - The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
112 #[inline(always)]
113 pub fn rxendpkt_clr(&mut self) -> RXENDPKT_CLR_W<12> {
114 RXENDPKT_CLR_W::new(self)
115 }
116 #[doc = "Bit 13 - The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared."]
117 #[inline(always)]
118 pub fn txendpkt_clr(&mut self) -> TXENDPKT_CLR_W<13> {
119 TXENDPKT_CLR_W::new(self)
120 }
121 #[doc = "Writes raw bits to the register."]
122 #[inline(always)]
123 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
124 self.0.bits(bits);
125 self
126 }
127}
128#[doc = "USB Device Interrupt Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devintctrl](index.html) module"]
129pub struct DEVINTCTRL_SPEC;
130impl crate::RegisterSpec for DEVINTCTRL_SPEC {
131 type Ux = u32;
132}
133#[doc = "`write(|w| ..)` method takes [devintctrl::W](W) writer structure"]
134impl crate::Writable for DEVINTCTRL_SPEC {
135 type Writer = W;
136}
137#[doc = "`reset()` method sets DEVINTCTRL to value 0"]
138impl crate::Resettable for DEVINTCTRL_SPEC {
139 #[inline(always)]
140 fn reset_value() -> Self::Ux {
141 0
142 }
143}