pub struct R { /* private fields */ }
Expand description

Value read from the register

Implementations§

Value of the register as raw bits

Bit 0 - Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.

Bit 1 - Enables clock for ROM.

Bit 2 - Enables clock for RAM.

Bit 3 - Enables clock for flash register interface.

Bit 4 - Enables clock for flash array access.

Bit 5 - Enables clock for I2C.

Bit 6 - Enables clock for GPIO port registers.

Bit 7 - Enables clock for 16-bit counter/timer 0.

Bit 8 - Enables clock for 16-bit counter/timer 1.

Bit 9 - Enables clock for 32-bit counter/timer 0.

Bit 10 - Enables clock for 32-bit counter/timer 1.

Bit 11 - Enables clock for SSP0.

Bit 12 - Enables clock for UART.

Bit 13 - Enables clock for ADC.

Bit 14 - Enables clock to the USB register interface.

Bit 15 - Enables clock for WWDT.

Bit 16 - Enables clock for I/O configuration block.

Bit 18 - Enables clock for SSP1.

Bit 19 - Enables clock to GPIO Pin interrupts register interface.

Bit 23 - Enables clock to GPIO GROUP0 interrupt register interface.

Bit 24 - Enables clock to GPIO GROUP1 interrupt register interface.

Bit 26 - Enables SRAM1 block at address 0x2000 0000. See Section 3.1 for availability of this bit.

Bit 27 - Enables USB SRAM block at address 0x2000 4000.

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Returns the argument unchanged.

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The type returned in the event of a conversion error.
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