1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::LCR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `WLS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum WLSR {
48 #[doc = "5-bit character length."]
49 _5_BIT_CHARACTER_LENG,
50 #[doc = "6-bit character length."]
51 _6_BIT_CHARACTER_LENG,
52 #[doc = "7-bit character length."]
53 _7_BIT_CHARACTER_LENG,
54 #[doc = "8-bit character length."]
55 _8_BIT_CHARACTER_LENG,
56}
57impl WLSR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 WLSR::_5_BIT_CHARACTER_LENG => 0,
63 WLSR::_6_BIT_CHARACTER_LENG => 1,
64 WLSR::_7_BIT_CHARACTER_LENG => 2,
65 WLSR::_8_BIT_CHARACTER_LENG => 3,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> WLSR {
72 match value {
73 0 => WLSR::_5_BIT_CHARACTER_LENG,
74 1 => WLSR::_6_BIT_CHARACTER_LENG,
75 2 => WLSR::_7_BIT_CHARACTER_LENG,
76 3 => WLSR::_8_BIT_CHARACTER_LENG,
77 _ => unreachable!(),
78 }
79 }
80 #[doc = "Checks if the value of the field is `_5_BIT_CHARACTER_LENG`"]
81 #[inline]
82 pub fn is_5_bit_character_leng(&self) -> bool {
83 *self == WLSR::_5_BIT_CHARACTER_LENG
84 }
85 #[doc = "Checks if the value of the field is `_6_BIT_CHARACTER_LENG`"]
86 #[inline]
87 pub fn is_6_bit_character_leng(&self) -> bool {
88 *self == WLSR::_6_BIT_CHARACTER_LENG
89 }
90 #[doc = "Checks if the value of the field is `_7_BIT_CHARACTER_LENG`"]
91 #[inline]
92 pub fn is_7_bit_character_leng(&self) -> bool {
93 *self == WLSR::_7_BIT_CHARACTER_LENG
94 }
95 #[doc = "Checks if the value of the field is `_8_BIT_CHARACTER_LENG`"]
96 #[inline]
97 pub fn is_8_bit_character_leng(&self) -> bool {
98 *self == WLSR::_8_BIT_CHARACTER_LENG
99 }
100}
101#[doc = "Possible values of the field `SBS`"]
102#[derive(Clone, Copy, Debug, PartialEq)]
103pub enum SBSR {
104 #[doc = "1 stop bit."]
105 _1_STOP_BIT,
106 #[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
107 _2_STOP_BITS_1_5_IF,
108}
109impl SBSR {
110 #[doc = r" Returns `true` if the bit is clear (0)"]
111 #[inline]
112 pub fn bit_is_clear(&self) -> bool {
113 !self.bit()
114 }
115 #[doc = r" Returns `true` if the bit is set (1)"]
116 #[inline]
117 pub fn bit_is_set(&self) -> bool {
118 self.bit()
119 }
120 #[doc = r" Value of the field as raw bits"]
121 #[inline]
122 pub fn bit(&self) -> bool {
123 match *self {
124 SBSR::_1_STOP_BIT => false,
125 SBSR::_2_STOP_BITS_1_5_IF => true,
126 }
127 }
128 #[allow(missing_docs)]
129 #[doc(hidden)]
130 #[inline]
131 pub fn _from(value: bool) -> SBSR {
132 match value {
133 false => SBSR::_1_STOP_BIT,
134 true => SBSR::_2_STOP_BITS_1_5_IF,
135 }
136 }
137 #[doc = "Checks if the value of the field is `_1_STOP_BIT`"]
138 #[inline]
139 pub fn is_1_stop_bit(&self) -> bool {
140 *self == SBSR::_1_STOP_BIT
141 }
142 #[doc = "Checks if the value of the field is `_2_STOP_BITS_1_5_IF`"]
143 #[inline]
144 pub fn is_2_stop_bits_1_5_if(&self) -> bool {
145 *self == SBSR::_2_STOP_BITS_1_5_IF
146 }
147}
148#[doc = "Possible values of the field `PE`"]
149#[derive(Clone, Copy, Debug, PartialEq)]
150pub enum PER {
151 #[doc = "Disable parity generation and checking."]
152 DISABLED,
153 #[doc = "Enable parity generation and checking."]
154 ENABLED,
155}
156impl PER {
157 #[doc = r" Returns `true` if the bit is clear (0)"]
158 #[inline]
159 pub fn bit_is_clear(&self) -> bool {
160 !self.bit()
161 }
162 #[doc = r" Returns `true` if the bit is set (1)"]
163 #[inline]
164 pub fn bit_is_set(&self) -> bool {
165 self.bit()
166 }
167 #[doc = r" Value of the field as raw bits"]
168 #[inline]
169 pub fn bit(&self) -> bool {
170 match *self {
171 PER::DISABLED => false,
172 PER::ENABLED => true,
173 }
174 }
175 #[allow(missing_docs)]
176 #[doc(hidden)]
177 #[inline]
178 pub fn _from(value: bool) -> PER {
179 match value {
180 false => PER::DISABLED,
181 true => PER::ENABLED,
182 }
183 }
184 #[doc = "Checks if the value of the field is `DISABLED`"]
185 #[inline]
186 pub fn is_disabled(&self) -> bool {
187 *self == PER::DISABLED
188 }
189 #[doc = "Checks if the value of the field is `ENABLED`"]
190 #[inline]
191 pub fn is_enabled(&self) -> bool {
192 *self == PER::ENABLED
193 }
194}
195#[doc = "Possible values of the field `PS`"]
196#[derive(Clone, Copy, Debug, PartialEq)]
197pub enum PSR {
198 #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
199 ODD,
200 #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
201 EVEN,
202 #[doc = "Forced 1 stick parity."]
203 FORCED_1_STICK,
204 #[doc = "Forced 0 stick parity."]
205 FORCED_0_STICK,
206}
207impl PSR {
208 #[doc = r" Value of the field as raw bits"]
209 #[inline]
210 pub fn bits(&self) -> u8 {
211 match *self {
212 PSR::ODD => 0,
213 PSR::EVEN => 1,
214 PSR::FORCED_1_STICK => 2,
215 PSR::FORCED_0_STICK => 3,
216 }
217 }
218 #[allow(missing_docs)]
219 #[doc(hidden)]
220 #[inline]
221 pub fn _from(value: u8) -> PSR {
222 match value {
223 0 => PSR::ODD,
224 1 => PSR::EVEN,
225 2 => PSR::FORCED_1_STICK,
226 3 => PSR::FORCED_0_STICK,
227 _ => unreachable!(),
228 }
229 }
230 #[doc = "Checks if the value of the field is `ODD`"]
231 #[inline]
232 pub fn is_odd(&self) -> bool {
233 *self == PSR::ODD
234 }
235 #[doc = "Checks if the value of the field is `EVEN`"]
236 #[inline]
237 pub fn is_even(&self) -> bool {
238 *self == PSR::EVEN
239 }
240 #[doc = "Checks if the value of the field is `FORCED_1_STICK`"]
241 #[inline]
242 pub fn is_forced_1_stick(&self) -> bool {
243 *self == PSR::FORCED_1_STICK
244 }
245 #[doc = "Checks if the value of the field is `FORCED_0_STICK`"]
246 #[inline]
247 pub fn is_forced_0_stick(&self) -> bool {
248 *self == PSR::FORCED_0_STICK
249 }
250}
251#[doc = "Possible values of the field `BC`"]
252#[derive(Clone, Copy, Debug, PartialEq)]
253pub enum BCR {
254 #[doc = "Disable break transmission."]
255 DISABLE_BREAK_TRANSM,
256 #[doc = "Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR\\[6\\] is active high."]
257 ENABLE_BREAK_TRANSMI,
258}
259impl BCR {
260 #[doc = r" Returns `true` if the bit is clear (0)"]
261 #[inline]
262 pub fn bit_is_clear(&self) -> bool {
263 !self.bit()
264 }
265 #[doc = r" Returns `true` if the bit is set (1)"]
266 #[inline]
267 pub fn bit_is_set(&self) -> bool {
268 self.bit()
269 }
270 #[doc = r" Value of the field as raw bits"]
271 #[inline]
272 pub fn bit(&self) -> bool {
273 match *self {
274 BCR::DISABLE_BREAK_TRANSM => false,
275 BCR::ENABLE_BREAK_TRANSMI => true,
276 }
277 }
278 #[allow(missing_docs)]
279 #[doc(hidden)]
280 #[inline]
281 pub fn _from(value: bool) -> BCR {
282 match value {
283 false => BCR::DISABLE_BREAK_TRANSM,
284 true => BCR::ENABLE_BREAK_TRANSMI,
285 }
286 }
287 #[doc = "Checks if the value of the field is `DISABLE_BREAK_TRANSM`"]
288 #[inline]
289 pub fn is_disable_break_transm(&self) -> bool {
290 *self == BCR::DISABLE_BREAK_TRANSM
291 }
292 #[doc = "Checks if the value of the field is `ENABLE_BREAK_TRANSMI`"]
293 #[inline]
294 pub fn is_enable_break_transmi(&self) -> bool {
295 *self == BCR::ENABLE_BREAK_TRANSMI
296 }
297}
298#[doc = "Possible values of the field `DLAB`"]
299#[derive(Clone, Copy, Debug, PartialEq)]
300pub enum DLABR {
301 #[doc = "Disable access to Divisor Latches."]
302 DISABLE_ACCESS_TO_DI,
303 #[doc = "Enable access to Divisor Latches."]
304 ENABLE_ACCESS_TO_DIV,
305}
306impl DLABR {
307 #[doc = r" Returns `true` if the bit is clear (0)"]
308 #[inline]
309 pub fn bit_is_clear(&self) -> bool {
310 !self.bit()
311 }
312 #[doc = r" Returns `true` if the bit is set (1)"]
313 #[inline]
314 pub fn bit_is_set(&self) -> bool {
315 self.bit()
316 }
317 #[doc = r" Value of the field as raw bits"]
318 #[inline]
319 pub fn bit(&self) -> bool {
320 match *self {
321 DLABR::DISABLE_ACCESS_TO_DI => false,
322 DLABR::ENABLE_ACCESS_TO_DIV => true,
323 }
324 }
325 #[allow(missing_docs)]
326 #[doc(hidden)]
327 #[inline]
328 pub fn _from(value: bool) -> DLABR {
329 match value {
330 false => DLABR::DISABLE_ACCESS_TO_DI,
331 true => DLABR::ENABLE_ACCESS_TO_DIV,
332 }
333 }
334 #[doc = "Checks if the value of the field is `DISABLE_ACCESS_TO_DI`"]
335 #[inline]
336 pub fn is_disable_access_to_di(&self) -> bool {
337 *self == DLABR::DISABLE_ACCESS_TO_DI
338 }
339 #[doc = "Checks if the value of the field is `ENABLE_ACCESS_TO_DIV`"]
340 #[inline]
341 pub fn is_enable_access_to_div(&self) -> bool {
342 *self == DLABR::ENABLE_ACCESS_TO_DIV
343 }
344}
345#[doc = "Values that can be written to the field `WLS`"]
346pub enum WLSW {
347 #[doc = "5-bit character length."]
348 _5_BIT_CHARACTER_LENG,
349 #[doc = "6-bit character length."]
350 _6_BIT_CHARACTER_LENG,
351 #[doc = "7-bit character length."]
352 _7_BIT_CHARACTER_LENG,
353 #[doc = "8-bit character length."]
354 _8_BIT_CHARACTER_LENG,
355}
356impl WLSW {
357 #[allow(missing_docs)]
358 #[doc(hidden)]
359 #[inline]
360 pub fn _bits(&self) -> u8 {
361 match *self {
362 WLSW::_5_BIT_CHARACTER_LENG => 0,
363 WLSW::_6_BIT_CHARACTER_LENG => 1,
364 WLSW::_7_BIT_CHARACTER_LENG => 2,
365 WLSW::_8_BIT_CHARACTER_LENG => 3,
366 }
367 }
368}
369#[doc = r" Proxy"]
370pub struct _WLSW<'a> {
371 w: &'a mut W,
372}
373impl<'a> _WLSW<'a> {
374 #[doc = r" Writes `variant` to the field"]
375 #[inline]
376 pub fn variant(self, variant: WLSW) -> &'a mut W {
377 {
378 self.bits(variant._bits())
379 }
380 }
381 #[doc = "5-bit character length."]
382 #[inline]
383 pub fn _5_bit_character_leng(self) -> &'a mut W {
384 self.variant(WLSW::_5_BIT_CHARACTER_LENG)
385 }
386 #[doc = "6-bit character length."]
387 #[inline]
388 pub fn _6_bit_character_leng(self) -> &'a mut W {
389 self.variant(WLSW::_6_BIT_CHARACTER_LENG)
390 }
391 #[doc = "7-bit character length."]
392 #[inline]
393 pub fn _7_bit_character_leng(self) -> &'a mut W {
394 self.variant(WLSW::_7_BIT_CHARACTER_LENG)
395 }
396 #[doc = "8-bit character length."]
397 #[inline]
398 pub fn _8_bit_character_leng(self) -> &'a mut W {
399 self.variant(WLSW::_8_BIT_CHARACTER_LENG)
400 }
401 #[doc = r" Writes raw bits to the field"]
402 #[inline]
403 pub fn bits(self, value: u8) -> &'a mut W {
404 const MASK: u8 = 3;
405 const OFFSET: u8 = 0;
406 self.w.bits &= !((MASK as u32) << OFFSET);
407 self.w.bits |= ((value & MASK) as u32) << OFFSET;
408 self.w
409 }
410}
411#[doc = "Values that can be written to the field `SBS`"]
412pub enum SBSW {
413 #[doc = "1 stop bit."]
414 _1_STOP_BIT,
415 #[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
416 _2_STOP_BITS_1_5_IF,
417}
418impl SBSW {
419 #[allow(missing_docs)]
420 #[doc(hidden)]
421 #[inline]
422 pub fn _bits(&self) -> bool {
423 match *self {
424 SBSW::_1_STOP_BIT => false,
425 SBSW::_2_STOP_BITS_1_5_IF => true,
426 }
427 }
428}
429#[doc = r" Proxy"]
430pub struct _SBSW<'a> {
431 w: &'a mut W,
432}
433impl<'a> _SBSW<'a> {
434 #[doc = r" Writes `variant` to the field"]
435 #[inline]
436 pub fn variant(self, variant: SBSW) -> &'a mut W {
437 {
438 self.bit(variant._bits())
439 }
440 }
441 #[doc = "1 stop bit."]
442 #[inline]
443 pub fn _1_stop_bit(self) -> &'a mut W {
444 self.variant(SBSW::_1_STOP_BIT)
445 }
446 #[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
447 #[inline]
448 pub fn _2_stop_bits_1_5_if(self) -> &'a mut W {
449 self.variant(SBSW::_2_STOP_BITS_1_5_IF)
450 }
451 #[doc = r" Sets the field bit"]
452 pub fn set_bit(self) -> &'a mut W {
453 self.bit(true)
454 }
455 #[doc = r" Clears the field bit"]
456 pub fn clear_bit(self) -> &'a mut W {
457 self.bit(false)
458 }
459 #[doc = r" Writes raw bits to the field"]
460 #[inline]
461 pub fn bit(self, value: bool) -> &'a mut W {
462 const MASK: bool = true;
463 const OFFSET: u8 = 2;
464 self.w.bits &= !((MASK as u32) << OFFSET);
465 self.w.bits |= ((value & MASK) as u32) << OFFSET;
466 self.w
467 }
468}
469#[doc = "Values that can be written to the field `PE`"]
470pub enum PEW {
471 #[doc = "Disable parity generation and checking."]
472 DISABLED,
473 #[doc = "Enable parity generation and checking."]
474 ENABLED,
475}
476impl PEW {
477 #[allow(missing_docs)]
478 #[doc(hidden)]
479 #[inline]
480 pub fn _bits(&self) -> bool {
481 match *self {
482 PEW::DISABLED => false,
483 PEW::ENABLED => true,
484 }
485 }
486}
487#[doc = r" Proxy"]
488pub struct _PEW<'a> {
489 w: &'a mut W,
490}
491impl<'a> _PEW<'a> {
492 #[doc = r" Writes `variant` to the field"]
493 #[inline]
494 pub fn variant(self, variant: PEW) -> &'a mut W {
495 {
496 self.bit(variant._bits())
497 }
498 }
499 #[doc = "Disable parity generation and checking."]
500 #[inline]
501 pub fn disabled(self) -> &'a mut W {
502 self.variant(PEW::DISABLED)
503 }
504 #[doc = "Enable parity generation and checking."]
505 #[inline]
506 pub fn enabled(self) -> &'a mut W {
507 self.variant(PEW::ENABLED)
508 }
509 #[doc = r" Sets the field bit"]
510 pub fn set_bit(self) -> &'a mut W {
511 self.bit(true)
512 }
513 #[doc = r" Clears the field bit"]
514 pub fn clear_bit(self) -> &'a mut W {
515 self.bit(false)
516 }
517 #[doc = r" Writes raw bits to the field"]
518 #[inline]
519 pub fn bit(self, value: bool) -> &'a mut W {
520 const MASK: bool = true;
521 const OFFSET: u8 = 3;
522 self.w.bits &= !((MASK as u32) << OFFSET);
523 self.w.bits |= ((value & MASK) as u32) << OFFSET;
524 self.w
525 }
526}
527#[doc = "Values that can be written to the field `PS`"]
528pub enum PSW {
529 #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
530 ODD,
531 #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
532 EVEN,
533 #[doc = "Forced 1 stick parity."]
534 FORCED_1_STICK,
535 #[doc = "Forced 0 stick parity."]
536 FORCED_0_STICK,
537}
538impl PSW {
539 #[allow(missing_docs)]
540 #[doc(hidden)]
541 #[inline]
542 pub fn _bits(&self) -> u8 {
543 match *self {
544 PSW::ODD => 0,
545 PSW::EVEN => 1,
546 PSW::FORCED_1_STICK => 2,
547 PSW::FORCED_0_STICK => 3,
548 }
549 }
550}
551#[doc = r" Proxy"]
552pub struct _PSW<'a> {
553 w: &'a mut W,
554}
555impl<'a> _PSW<'a> {
556 #[doc = r" Writes `variant` to the field"]
557 #[inline]
558 pub fn variant(self, variant: PSW) -> &'a mut W {
559 {
560 self.bits(variant._bits())
561 }
562 }
563 #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
564 #[inline]
565 pub fn odd(self) -> &'a mut W {
566 self.variant(PSW::ODD)
567 }
568 #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
569 #[inline]
570 pub fn even(self) -> &'a mut W {
571 self.variant(PSW::EVEN)
572 }
573 #[doc = "Forced 1 stick parity."]
574 #[inline]
575 pub fn forced_1_stick(self) -> &'a mut W {
576 self.variant(PSW::FORCED_1_STICK)
577 }
578 #[doc = "Forced 0 stick parity."]
579 #[inline]
580 pub fn forced_0_stick(self) -> &'a mut W {
581 self.variant(PSW::FORCED_0_STICK)
582 }
583 #[doc = r" Writes raw bits to the field"]
584 #[inline]
585 pub fn bits(self, value: u8) -> &'a mut W {
586 const MASK: u8 = 3;
587 const OFFSET: u8 = 4;
588 self.w.bits &= !((MASK as u32) << OFFSET);
589 self.w.bits |= ((value & MASK) as u32) << OFFSET;
590 self.w
591 }
592}
593#[doc = "Values that can be written to the field `BC`"]
594pub enum BCW {
595 #[doc = "Disable break transmission."]
596 DISABLE_BREAK_TRANSM,
597 #[doc = "Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR\\[6\\] is active high."]
598 ENABLE_BREAK_TRANSMI,
599}
600impl BCW {
601 #[allow(missing_docs)]
602 #[doc(hidden)]
603 #[inline]
604 pub fn _bits(&self) -> bool {
605 match *self {
606 BCW::DISABLE_BREAK_TRANSM => false,
607 BCW::ENABLE_BREAK_TRANSMI => true,
608 }
609 }
610}
611#[doc = r" Proxy"]
612pub struct _BCW<'a> {
613 w: &'a mut W,
614}
615impl<'a> _BCW<'a> {
616 #[doc = r" Writes `variant` to the field"]
617 #[inline]
618 pub fn variant(self, variant: BCW) -> &'a mut W {
619 {
620 self.bit(variant._bits())
621 }
622 }
623 #[doc = "Disable break transmission."]
624 #[inline]
625 pub fn disable_break_transm(self) -> &'a mut W {
626 self.variant(BCW::DISABLE_BREAK_TRANSM)
627 }
628 #[doc = "Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR\\[6\\] is active high."]
629 #[inline]
630 pub fn enable_break_transmi(self) -> &'a mut W {
631 self.variant(BCW::ENABLE_BREAK_TRANSMI)
632 }
633 #[doc = r" Sets the field bit"]
634 pub fn set_bit(self) -> &'a mut W {
635 self.bit(true)
636 }
637 #[doc = r" Clears the field bit"]
638 pub fn clear_bit(self) -> &'a mut W {
639 self.bit(false)
640 }
641 #[doc = r" Writes raw bits to the field"]
642 #[inline]
643 pub fn bit(self, value: bool) -> &'a mut W {
644 const MASK: bool = true;
645 const OFFSET: u8 = 6;
646 self.w.bits &= !((MASK as u32) << OFFSET);
647 self.w.bits |= ((value & MASK) as u32) << OFFSET;
648 self.w
649 }
650}
651#[doc = "Values that can be written to the field `DLAB`"]
652pub enum DLABW {
653 #[doc = "Disable access to Divisor Latches."]
654 DISABLE_ACCESS_TO_DI,
655 #[doc = "Enable access to Divisor Latches."]
656 ENABLE_ACCESS_TO_DIV,
657}
658impl DLABW {
659 #[allow(missing_docs)]
660 #[doc(hidden)]
661 #[inline]
662 pub fn _bits(&self) -> bool {
663 match *self {
664 DLABW::DISABLE_ACCESS_TO_DI => false,
665 DLABW::ENABLE_ACCESS_TO_DIV => true,
666 }
667 }
668}
669#[doc = r" Proxy"]
670pub struct _DLABW<'a> {
671 w: &'a mut W,
672}
673impl<'a> _DLABW<'a> {
674 #[doc = r" Writes `variant` to the field"]
675 #[inline]
676 pub fn variant(self, variant: DLABW) -> &'a mut W {
677 {
678 self.bit(variant._bits())
679 }
680 }
681 #[doc = "Disable access to Divisor Latches."]
682 #[inline]
683 pub fn disable_access_to_di(self) -> &'a mut W {
684 self.variant(DLABW::DISABLE_ACCESS_TO_DI)
685 }
686 #[doc = "Enable access to Divisor Latches."]
687 #[inline]
688 pub fn enable_access_to_div(self) -> &'a mut W {
689 self.variant(DLABW::ENABLE_ACCESS_TO_DIV)
690 }
691 #[doc = r" Sets the field bit"]
692 pub fn set_bit(self) -> &'a mut W {
693 self.bit(true)
694 }
695 #[doc = r" Clears the field bit"]
696 pub fn clear_bit(self) -> &'a mut W {
697 self.bit(false)
698 }
699 #[doc = r" Writes raw bits to the field"]
700 #[inline]
701 pub fn bit(self, value: bool) -> &'a mut W {
702 const MASK: bool = true;
703 const OFFSET: u8 = 7;
704 self.w.bits &= !((MASK as u32) << OFFSET);
705 self.w.bits |= ((value & MASK) as u32) << OFFSET;
706 self.w
707 }
708}
709impl R {
710 #[doc = r" Value of the register as raw bits"]
711 #[inline]
712 pub fn bits(&self) -> u32 {
713 self.bits
714 }
715 #[doc = "Bits 0:1 - Word Length Select"]
716 #[inline]
717 pub fn wls(&self) -> WLSR {
718 WLSR::_from({
719 const MASK: u8 = 3;
720 const OFFSET: u8 = 0;
721 ((self.bits >> OFFSET) & MASK as u32) as u8
722 })
723 }
724 #[doc = "Bit 2 - Stop Bit Select"]
725 #[inline]
726 pub fn sbs(&self) -> SBSR {
727 SBSR::_from({
728 const MASK: bool = true;
729 const OFFSET: u8 = 2;
730 ((self.bits >> OFFSET) & MASK as u32) != 0
731 })
732 }
733 #[doc = "Bit 3 - Parity Enable"]
734 #[inline]
735 pub fn pe(&self) -> PER {
736 PER::_from({
737 const MASK: bool = true;
738 const OFFSET: u8 = 3;
739 ((self.bits >> OFFSET) & MASK as u32) != 0
740 })
741 }
742 #[doc = "Bits 4:5 - Parity Select"]
743 #[inline]
744 pub fn ps(&self) -> PSR {
745 PSR::_from({
746 const MASK: u8 = 3;
747 const OFFSET: u8 = 4;
748 ((self.bits >> OFFSET) & MASK as u32) as u8
749 })
750 }
751 #[doc = "Bit 6 - Break Control"]
752 #[inline]
753 pub fn bc(&self) -> BCR {
754 BCR::_from({
755 const MASK: bool = true;
756 const OFFSET: u8 = 6;
757 ((self.bits >> OFFSET) & MASK as u32) != 0
758 })
759 }
760 #[doc = "Bit 7 - Divisor Latch Access Bit"]
761 #[inline]
762 pub fn dlab(&self) -> DLABR {
763 DLABR::_from({
764 const MASK: bool = true;
765 const OFFSET: u8 = 7;
766 ((self.bits >> OFFSET) & MASK as u32) != 0
767 })
768 }
769}
770impl W {
771 #[doc = r" Reset value of the register"]
772 #[inline]
773 pub fn reset_value() -> W {
774 W { bits: 0 }
775 }
776 #[doc = r" Writes raw bits to the register"]
777 #[inline]
778 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
779 self.bits = bits;
780 self
781 }
782 #[doc = "Bits 0:1 - Word Length Select"]
783 #[inline]
784 pub fn wls(&mut self) -> _WLSW {
785 _WLSW { w: self }
786 }
787 #[doc = "Bit 2 - Stop Bit Select"]
788 #[inline]
789 pub fn sbs(&mut self) -> _SBSW {
790 _SBSW { w: self }
791 }
792 #[doc = "Bit 3 - Parity Enable"]
793 #[inline]
794 pub fn pe(&mut self) -> _PEW {
795 _PEW { w: self }
796 }
797 #[doc = "Bits 4:5 - Parity Select"]
798 #[inline]
799 pub fn ps(&mut self) -> _PSW {
800 _PSW { w: self }
801 }
802 #[doc = "Bit 6 - Break Control"]
803 #[inline]
804 pub fn bc(&mut self) -> _BCW {
805 _BCW { w: self }
806 }
807 #[doc = "Bit 7 - Divisor Latch Access Bit"]
808 #[inline]
809 pub fn dlab(&mut self) -> _DLABW {
810 _DLABW { w: self }
811 }
812}