1#[doc = "Register `INTSTAT` reader"]
2pub struct R(crate::pac::generic::R<INTSTAT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::pac::generic::R<INTSTAT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::pac::generic::R<INTSTAT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::pac::generic::R<INTSTAT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `INTSTAT` writer"]
17pub struct W(crate::pac::generic::W<INTSTAT_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::pac::generic::W<INTSTAT_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::pac::generic::W<INTSTAT_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::pac::generic::W<INTSTAT_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `EP0OUT` reader - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it."]
38pub struct EP0OUT_R(crate::pac::generic::FieldReader<bool, bool>);
39impl EP0OUT_R {
40 #[inline(always)]
41 pub(crate) fn new(bits: bool) -> Self {
42 EP0OUT_R(crate::pac::generic::FieldReader::new(bits))
43 }
44}
45impl core::ops::Deref for EP0OUT_R {
46 type Target = crate::pac::generic::FieldReader<bool, bool>;
47 #[inline(always)]
48 fn deref(&self) -> &Self::Target {
49 &self.0
50 }
51}
52#[doc = "Field `EP0OUT` writer - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it."]
53pub struct EP0OUT_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> EP0OUT_W<'a> {
57 #[doc = r"Sets the field bit"]
58 #[inline(always)]
59 pub fn set_bit(self) -> &'a mut W {
60 self.bit(true)
61 }
62 #[doc = r"Clears the field bit"]
63 #[inline(always)]
64 pub fn clear_bit(self) -> &'a mut W {
65 self.bit(false)
66 }
67 #[doc = r"Writes raw bits to the field"]
68 #[inline(always)]
69 pub fn bit(self, value: bool) -> &'a mut W {
70 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71 self.w
72 }
73}
74#[doc = "Field `EP0IN` reader - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it."]
75pub struct EP0IN_R(crate::pac::generic::FieldReader<bool, bool>);
76impl EP0IN_R {
77 #[inline(always)]
78 pub(crate) fn new(bits: bool) -> Self {
79 EP0IN_R(crate::pac::generic::FieldReader::new(bits))
80 }
81}
82impl core::ops::Deref for EP0IN_R {
83 type Target = crate::pac::generic::FieldReader<bool, bool>;
84 #[inline(always)]
85 fn deref(&self) -> &Self::Target {
86 &self.0
87 }
88}
89#[doc = "Field `EP0IN` writer - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it."]
90pub struct EP0IN_W<'a> {
91 w: &'a mut W,
92}
93impl<'a> EP0IN_W<'a> {
94 #[doc = r"Sets the field bit"]
95 #[inline(always)]
96 pub fn set_bit(self) -> &'a mut W {
97 self.bit(true)
98 }
99 #[doc = r"Clears the field bit"]
100 #[inline(always)]
101 pub fn clear_bit(self) -> &'a mut W {
102 self.bit(false)
103 }
104 #[doc = r"Writes raw bits to the field"]
105 #[inline(always)]
106 pub fn bit(self, value: bool) -> &'a mut W {
107 self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
108 self.w
109 }
110}
111#[doc = "Field `EP1OUT` reader - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it."]
112pub struct EP1OUT_R(crate::pac::generic::FieldReader<bool, bool>);
113impl EP1OUT_R {
114 #[inline(always)]
115 pub(crate) fn new(bits: bool) -> Self {
116 EP1OUT_R(crate::pac::generic::FieldReader::new(bits))
117 }
118}
119impl core::ops::Deref for EP1OUT_R {
120 type Target = crate::pac::generic::FieldReader<bool, bool>;
121 #[inline(always)]
122 fn deref(&self) -> &Self::Target {
123 &self.0
124 }
125}
126#[doc = "Field `EP1OUT` writer - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it."]
127pub struct EP1OUT_W<'a> {
128 w: &'a mut W,
129}
130impl<'a> EP1OUT_W<'a> {
131 #[doc = r"Sets the field bit"]
132 #[inline(always)]
133 pub fn set_bit(self) -> &'a mut W {
134 self.bit(true)
135 }
136 #[doc = r"Clears the field bit"]
137 #[inline(always)]
138 pub fn clear_bit(self) -> &'a mut W {
139 self.bit(false)
140 }
141 #[doc = r"Writes raw bits to the field"]
142 #[inline(always)]
143 pub fn bit(self, value: bool) -> &'a mut W {
144 self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
145 self.w
146 }
147}
148#[doc = "Field `EP1IN` reader - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it."]
149pub struct EP1IN_R(crate::pac::generic::FieldReader<bool, bool>);
150impl EP1IN_R {
151 #[inline(always)]
152 pub(crate) fn new(bits: bool) -> Self {
153 EP1IN_R(crate::pac::generic::FieldReader::new(bits))
154 }
155}
156impl core::ops::Deref for EP1IN_R {
157 type Target = crate::pac::generic::FieldReader<bool, bool>;
158 #[inline(always)]
159 fn deref(&self) -> &Self::Target {
160 &self.0
161 }
162}
163#[doc = "Field `EP1IN` writer - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it."]
164pub struct EP1IN_W<'a> {
165 w: &'a mut W,
166}
167impl<'a> EP1IN_W<'a> {
168 #[doc = r"Sets the field bit"]
169 #[inline(always)]
170 pub fn set_bit(self) -> &'a mut W {
171 self.bit(true)
172 }
173 #[doc = r"Clears the field bit"]
174 #[inline(always)]
175 pub fn clear_bit(self) -> &'a mut W {
176 self.bit(false)
177 }
178 #[doc = r"Writes raw bits to the field"]
179 #[inline(always)]
180 pub fn bit(self, value: bool) -> &'a mut W {
181 self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
182 self.w
183 }
184}
185#[doc = "Field `EP2OUT` reader - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it."]
186pub struct EP2OUT_R(crate::pac::generic::FieldReader<bool, bool>);
187impl EP2OUT_R {
188 #[inline(always)]
189 pub(crate) fn new(bits: bool) -> Self {
190 EP2OUT_R(crate::pac::generic::FieldReader::new(bits))
191 }
192}
193impl core::ops::Deref for EP2OUT_R {
194 type Target = crate::pac::generic::FieldReader<bool, bool>;
195 #[inline(always)]
196 fn deref(&self) -> &Self::Target {
197 &self.0
198 }
199}
200#[doc = "Field `EP2OUT` writer - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it."]
201pub struct EP2OUT_W<'a> {
202 w: &'a mut W,
203}
204impl<'a> EP2OUT_W<'a> {
205 #[doc = r"Sets the field bit"]
206 #[inline(always)]
207 pub fn set_bit(self) -> &'a mut W {
208 self.bit(true)
209 }
210 #[doc = r"Clears the field bit"]
211 #[inline(always)]
212 pub fn clear_bit(self) -> &'a mut W {
213 self.bit(false)
214 }
215 #[doc = r"Writes raw bits to the field"]
216 #[inline(always)]
217 pub fn bit(self, value: bool) -> &'a mut W {
218 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
219 self.w
220 }
221}
222#[doc = "Field `EP2IN` reader - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it."]
223pub struct EP2IN_R(crate::pac::generic::FieldReader<bool, bool>);
224impl EP2IN_R {
225 #[inline(always)]
226 pub(crate) fn new(bits: bool) -> Self {
227 EP2IN_R(crate::pac::generic::FieldReader::new(bits))
228 }
229}
230impl core::ops::Deref for EP2IN_R {
231 type Target = crate::pac::generic::FieldReader<bool, bool>;
232 #[inline(always)]
233 fn deref(&self) -> &Self::Target {
234 &self.0
235 }
236}
237#[doc = "Field `EP2IN` writer - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it."]
238pub struct EP2IN_W<'a> {
239 w: &'a mut W,
240}
241impl<'a> EP2IN_W<'a> {
242 #[doc = r"Sets the field bit"]
243 #[inline(always)]
244 pub fn set_bit(self) -> &'a mut W {
245 self.bit(true)
246 }
247 #[doc = r"Clears the field bit"]
248 #[inline(always)]
249 pub fn clear_bit(self) -> &'a mut W {
250 self.bit(false)
251 }
252 #[doc = r"Writes raw bits to the field"]
253 #[inline(always)]
254 pub fn bit(self, value: bool) -> &'a mut W {
255 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
256 self.w
257 }
258}
259#[doc = "Field `EP3OUT` reader - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it."]
260pub struct EP3OUT_R(crate::pac::generic::FieldReader<bool, bool>);
261impl EP3OUT_R {
262 #[inline(always)]
263 pub(crate) fn new(bits: bool) -> Self {
264 EP3OUT_R(crate::pac::generic::FieldReader::new(bits))
265 }
266}
267impl core::ops::Deref for EP3OUT_R {
268 type Target = crate::pac::generic::FieldReader<bool, bool>;
269 #[inline(always)]
270 fn deref(&self) -> &Self::Target {
271 &self.0
272 }
273}
274#[doc = "Field `EP3OUT` writer - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it."]
275pub struct EP3OUT_W<'a> {
276 w: &'a mut W,
277}
278impl<'a> EP3OUT_W<'a> {
279 #[doc = r"Sets the field bit"]
280 #[inline(always)]
281 pub fn set_bit(self) -> &'a mut W {
282 self.bit(true)
283 }
284 #[doc = r"Clears the field bit"]
285 #[inline(always)]
286 pub fn clear_bit(self) -> &'a mut W {
287 self.bit(false)
288 }
289 #[doc = r"Writes raw bits to the field"]
290 #[inline(always)]
291 pub fn bit(self, value: bool) -> &'a mut W {
292 self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
293 self.w
294 }
295}
296#[doc = "Field `EP3IN` reader - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it."]
297pub struct EP3IN_R(crate::pac::generic::FieldReader<bool, bool>);
298impl EP3IN_R {
299 #[inline(always)]
300 pub(crate) fn new(bits: bool) -> Self {
301 EP3IN_R(crate::pac::generic::FieldReader::new(bits))
302 }
303}
304impl core::ops::Deref for EP3IN_R {
305 type Target = crate::pac::generic::FieldReader<bool, bool>;
306 #[inline(always)]
307 fn deref(&self) -> &Self::Target {
308 &self.0
309 }
310}
311#[doc = "Field `EP3IN` writer - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it."]
312pub struct EP3IN_W<'a> {
313 w: &'a mut W,
314}
315impl<'a> EP3IN_W<'a> {
316 #[doc = r"Sets the field bit"]
317 #[inline(always)]
318 pub fn set_bit(self) -> &'a mut W {
319 self.bit(true)
320 }
321 #[doc = r"Clears the field bit"]
322 #[inline(always)]
323 pub fn clear_bit(self) -> &'a mut W {
324 self.bit(false)
325 }
326 #[doc = r"Writes raw bits to the field"]
327 #[inline(always)]
328 pub fn bit(self, value: bool) -> &'a mut W {
329 self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
330 self.w
331 }
332}
333#[doc = "Field `EP4OUT` reader - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it."]
334pub struct EP4OUT_R(crate::pac::generic::FieldReader<bool, bool>);
335impl EP4OUT_R {
336 #[inline(always)]
337 pub(crate) fn new(bits: bool) -> Self {
338 EP4OUT_R(crate::pac::generic::FieldReader::new(bits))
339 }
340}
341impl core::ops::Deref for EP4OUT_R {
342 type Target = crate::pac::generic::FieldReader<bool, bool>;
343 #[inline(always)]
344 fn deref(&self) -> &Self::Target {
345 &self.0
346 }
347}
348#[doc = "Field `EP4OUT` writer - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it."]
349pub struct EP4OUT_W<'a> {
350 w: &'a mut W,
351}
352impl<'a> EP4OUT_W<'a> {
353 #[doc = r"Sets the field bit"]
354 #[inline(always)]
355 pub fn set_bit(self) -> &'a mut W {
356 self.bit(true)
357 }
358 #[doc = r"Clears the field bit"]
359 #[inline(always)]
360 pub fn clear_bit(self) -> &'a mut W {
361 self.bit(false)
362 }
363 #[doc = r"Writes raw bits to the field"]
364 #[inline(always)]
365 pub fn bit(self, value: bool) -> &'a mut W {
366 self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
367 self.w
368 }
369}
370#[doc = "Field `EP4IN` reader - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it."]
371pub struct EP4IN_R(crate::pac::generic::FieldReader<bool, bool>);
372impl EP4IN_R {
373 #[inline(always)]
374 pub(crate) fn new(bits: bool) -> Self {
375 EP4IN_R(crate::pac::generic::FieldReader::new(bits))
376 }
377}
378impl core::ops::Deref for EP4IN_R {
379 type Target = crate::pac::generic::FieldReader<bool, bool>;
380 #[inline(always)]
381 fn deref(&self) -> &Self::Target {
382 &self.0
383 }
384}
385#[doc = "Field `EP4IN` writer - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it."]
386pub struct EP4IN_W<'a> {
387 w: &'a mut W,
388}
389impl<'a> EP4IN_W<'a> {
390 #[doc = r"Sets the field bit"]
391 #[inline(always)]
392 pub fn set_bit(self) -> &'a mut W {
393 self.bit(true)
394 }
395 #[doc = r"Clears the field bit"]
396 #[inline(always)]
397 pub fn clear_bit(self) -> &'a mut W {
398 self.bit(false)
399 }
400 #[doc = r"Writes raw bits to the field"]
401 #[inline(always)]
402 pub fn bit(self, value: bool) -> &'a mut W {
403 self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
404 self.w
405 }
406}
407#[doc = "Field `FRAME_INT` reader - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it."]
408pub struct FRAME_INT_R(crate::pac::generic::FieldReader<bool, bool>);
409impl FRAME_INT_R {
410 #[inline(always)]
411 pub(crate) fn new(bits: bool) -> Self {
412 FRAME_INT_R(crate::pac::generic::FieldReader::new(bits))
413 }
414}
415impl core::ops::Deref for FRAME_INT_R {
416 type Target = crate::pac::generic::FieldReader<bool, bool>;
417 #[inline(always)]
418 fn deref(&self) -> &Self::Target {
419 &self.0
420 }
421}
422#[doc = "Field `FRAME_INT` writer - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it."]
423pub struct FRAME_INT_W<'a> {
424 w: &'a mut W,
425}
426impl<'a> FRAME_INT_W<'a> {
427 #[doc = r"Sets the field bit"]
428 #[inline(always)]
429 pub fn set_bit(self) -> &'a mut W {
430 self.bit(true)
431 }
432 #[doc = r"Clears the field bit"]
433 #[inline(always)]
434 pub fn clear_bit(self) -> &'a mut W {
435 self.bit(false)
436 }
437 #[doc = r"Writes raw bits to the field"]
438 #[inline(always)]
439 pub fn bit(self, value: bool) -> &'a mut W {
440 self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
441 self.w
442 }
443}
444#[doc = "Field `DEV_INT` reader - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it."]
445pub struct DEV_INT_R(crate::pac::generic::FieldReader<bool, bool>);
446impl DEV_INT_R {
447 #[inline(always)]
448 pub(crate) fn new(bits: bool) -> Self {
449 DEV_INT_R(crate::pac::generic::FieldReader::new(bits))
450 }
451}
452impl core::ops::Deref for DEV_INT_R {
453 type Target = crate::pac::generic::FieldReader<bool, bool>;
454 #[inline(always)]
455 fn deref(&self) -> &Self::Target {
456 &self.0
457 }
458}
459#[doc = "Field `DEV_INT` writer - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it."]
460pub struct DEV_INT_W<'a> {
461 w: &'a mut W,
462}
463impl<'a> DEV_INT_W<'a> {
464 #[doc = r"Sets the field bit"]
465 #[inline(always)]
466 pub fn set_bit(self) -> &'a mut W {
467 self.bit(true)
468 }
469 #[doc = r"Clears the field bit"]
470 #[inline(always)]
471 pub fn clear_bit(self) -> &'a mut W {
472 self.bit(false)
473 }
474 #[doc = r"Writes raw bits to the field"]
475 #[inline(always)]
476 pub fn bit(self, value: bool) -> &'a mut W {
477 self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
478 self.w
479 }
480}
481impl R {
482 #[doc = "Bit 0 - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it."]
483 #[inline(always)]
484 pub fn ep0out(&self) -> EP0OUT_R {
485 EP0OUT_R::new((self.bits & 0x01) != 0)
486 }
487 #[doc = "Bit 1 - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it."]
488 #[inline(always)]
489 pub fn ep0in(&self) -> EP0IN_R {
490 EP0IN_R::new(((self.bits >> 1) & 0x01) != 0)
491 }
492 #[doc = "Bit 2 - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it."]
493 #[inline(always)]
494 pub fn ep1out(&self) -> EP1OUT_R {
495 EP1OUT_R::new(((self.bits >> 2) & 0x01) != 0)
496 }
497 #[doc = "Bit 3 - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it."]
498 #[inline(always)]
499 pub fn ep1in(&self) -> EP1IN_R {
500 EP1IN_R::new(((self.bits >> 3) & 0x01) != 0)
501 }
502 #[doc = "Bit 4 - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it."]
503 #[inline(always)]
504 pub fn ep2out(&self) -> EP2OUT_R {
505 EP2OUT_R::new(((self.bits >> 4) & 0x01) != 0)
506 }
507 #[doc = "Bit 5 - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it."]
508 #[inline(always)]
509 pub fn ep2in(&self) -> EP2IN_R {
510 EP2IN_R::new(((self.bits >> 5) & 0x01) != 0)
511 }
512 #[doc = "Bit 6 - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it."]
513 #[inline(always)]
514 pub fn ep3out(&self) -> EP3OUT_R {
515 EP3OUT_R::new(((self.bits >> 6) & 0x01) != 0)
516 }
517 #[doc = "Bit 7 - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it."]
518 #[inline(always)]
519 pub fn ep3in(&self) -> EP3IN_R {
520 EP3IN_R::new(((self.bits >> 7) & 0x01) != 0)
521 }
522 #[doc = "Bit 8 - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it."]
523 #[inline(always)]
524 pub fn ep4out(&self) -> EP4OUT_R {
525 EP4OUT_R::new(((self.bits >> 8) & 0x01) != 0)
526 }
527 #[doc = "Bit 9 - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it."]
528 #[inline(always)]
529 pub fn ep4in(&self) -> EP4IN_R {
530 EP4IN_R::new(((self.bits >> 9) & 0x01) != 0)
531 }
532 #[doc = "Bit 30 - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it."]
533 #[inline(always)]
534 pub fn frame_int(&self) -> FRAME_INT_R {
535 FRAME_INT_R::new(((self.bits >> 30) & 0x01) != 0)
536 }
537 #[doc = "Bit 31 - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it."]
538 #[inline(always)]
539 pub fn dev_int(&self) -> DEV_INT_R {
540 DEV_INT_R::new(((self.bits >> 31) & 0x01) != 0)
541 }
542}
543impl W {
544 #[doc = "Bit 0 - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it."]
545 #[inline(always)]
546 pub fn ep0out(&mut self) -> EP0OUT_W {
547 EP0OUT_W { w: self }
548 }
549 #[doc = "Bit 1 - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it."]
550 #[inline(always)]
551 pub fn ep0in(&mut self) -> EP0IN_W {
552 EP0IN_W { w: self }
553 }
554 #[doc = "Bit 2 - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it."]
555 #[inline(always)]
556 pub fn ep1out(&mut self) -> EP1OUT_W {
557 EP1OUT_W { w: self }
558 }
559 #[doc = "Bit 3 - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it."]
560 #[inline(always)]
561 pub fn ep1in(&mut self) -> EP1IN_W {
562 EP1IN_W { w: self }
563 }
564 #[doc = "Bit 4 - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it."]
565 #[inline(always)]
566 pub fn ep2out(&mut self) -> EP2OUT_W {
567 EP2OUT_W { w: self }
568 }
569 #[doc = "Bit 5 - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it."]
570 #[inline(always)]
571 pub fn ep2in(&mut self) -> EP2IN_W {
572 EP2IN_W { w: self }
573 }
574 #[doc = "Bit 6 - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it."]
575 #[inline(always)]
576 pub fn ep3out(&mut self) -> EP3OUT_W {
577 EP3OUT_W { w: self }
578 }
579 #[doc = "Bit 7 - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it."]
580 #[inline(always)]
581 pub fn ep3in(&mut self) -> EP3IN_W {
582 EP3IN_W { w: self }
583 }
584 #[doc = "Bit 8 - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it."]
585 #[inline(always)]
586 pub fn ep4out(&mut self) -> EP4OUT_W {
587 EP4OUT_W { w: self }
588 }
589 #[doc = "Bit 9 - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it."]
590 #[inline(always)]
591 pub fn ep4in(&mut self) -> EP4IN_W {
592 EP4IN_W { w: self }
593 }
594 #[doc = "Bit 30 - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it."]
595 #[inline(always)]
596 pub fn frame_int(&mut self) -> FRAME_INT_W {
597 FRAME_INT_W { w: self }
598 }
599 #[doc = "Bit 31 - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it."]
600 #[inline(always)]
601 pub fn dev_int(&mut self) -> DEV_INT_W {
602 DEV_INT_W { w: self }
603 }
604 #[doc = "Writes raw bits to the register."]
605 #[inline(always)]
606 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
607 self.0.bits(bits);
608 self
609 }
610}
611#[doc = "USB interrupt status register\n\nThis register you can [`read`](crate::pac::generic::generic::Reg::read), [`write_with_zero`](crate::pac::generic::generic::Reg::write_with_zero), [`reset`](crate::pac::generic::generic::Reg::reset), [`write`](crate::pac::generic::generic::Reg::write), [`modify`](crate::pac::generic::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstat](index.html) module"]
612pub struct INTSTAT_SPEC;
613impl crate::pac::generic::RegisterSpec for INTSTAT_SPEC {
614 type Ux = u32;
615}
616#[doc = "`read()` method returns [intstat::R](R) reader structure"]
617impl crate::pac::generic::Readable for INTSTAT_SPEC {
618 type Reader = R;
619}
620#[doc = "`write(|w| ..)` method takes [intstat::W](W) writer structure"]
621impl crate::pac::generic::Writable for INTSTAT_SPEC {
622 type Writer = W;
623}
624#[doc = "`reset()` method sets INTSTAT to value 0"]
625impl crate::pac::generic::Resettable for INTSTAT_SPEC {
626 #[inline(always)]
627 fn reset_value() -> Self::Ux {
628 0
629 }
630}