xen/ctrl/event/arch/x86/
regs.rs

1use xen_sys::vm_event_regs_x86;
2
3use super::super::super::{VmEventRegs, VmEventSelectorReg};
4
5#[derive(Debug)]
6pub struct VmEventRegsX86 {
7    pub rax: u64,
8    pub rcx: u64,
9    pub rdx: u64,
10    pub rbx: u64,
11    pub rsp: u64,
12    pub rbp: u64,
13    pub rsi: u64,
14    pub rdi: u64,
15    pub r8: u64,
16    pub r9: u64,
17    pub r10: u64,
18    pub r11: u64,
19    pub r12: u64,
20    pub r13: u64,
21    pub r14: u64,
22    pub r15: u64,
23    pub rflags: u64,
24    pub dr6: u64,
25    pub dr7: u64,
26    pub rip: u64,
27    pub cr0: u64,
28    pub cr2: u64,
29    pub cr3: u64,
30    pub cr4: u64,
31    pub sysenter_cs: u64,
32    pub sysenter_esp: u64,
33    pub sysenter_eip: u64,
34    pub msr_efer: u64,
35    pub msr_star: u64,
36    pub msr_lstar: u64,
37    pub gdtr_base: u64,
38
39    // When VM_EVENT_FLAG_NESTED_P2M is set, this event comes from a nested
40    // VM.  npt_base is the guest physical address of the L1 hypervisors
41    // EPT/NPT tables for the nested guest.
42    //
43    // All bits outside of architectural address ranges are reserved for
44    // future metadata.
45    pub npt_base: u64,
46
47    // Current position in the vmtrace buffer, or ~0 if vmtrace is not active.
48    //
49    // For Intel Processor Trace, it is the upper half of MSR_RTIT_OUTPUT_MASK.
50    pub vmtrace_pos: u64,
51
52    pub cs_base: u32,
53    pub ss_base: u32,
54    pub ds_base: u32,
55    pub es_base: u32,
56    pub fs_base: u64,
57    pub gs_base: u64,
58    pub cs: VmEventSelectorReg,
59    pub ss: VmEventSelectorReg,
60    pub ds: VmEventSelectorReg,
61    pub es: VmEventSelectorReg,
62    pub fs: VmEventSelectorReg,
63    pub gs: VmEventSelectorReg,
64    pub shadow_gs: u64,
65    pub gdtr_limit: u16,
66    pub cs_sel: u16,
67    pub ss_sel: u16,
68    pub ds_sel: u16,
69    pub es_sel: u16,
70    pub fs_sel: u16,
71    pub gs_sel: u16,
72}
73
74impl From<vm_event_regs_x86> for VmEventRegsX86 {
75    fn from(value: vm_event_regs_x86) -> Self {
76        Self {
77            rax: value.rax,
78            rcx: value.rcx,
79            rdx: value.rdx,
80            rbx: value.rbx,
81            rsp: value.rsp,
82            rbp: value.rbp,
83            rsi: value.rsi,
84            rdi: value.rdi,
85            r8: value.r8,
86            r9: value.r9,
87            r10: value.r10,
88            r11: value.r11,
89            r12: value.r12,
90            r13: value.r13,
91            r14: value.r14,
92            r15: value.r15,
93            rflags: value.rflags,
94            dr6: value.dr6,
95            dr7: value.dr7,
96            rip: value.rip,
97            cr0: value.cr0,
98            cr2: value.cr2,
99            cr3: value.cr3,
100            cr4: value.cr4,
101            sysenter_cs: value.sysenter_cs,
102            sysenter_esp: value.sysenter_esp,
103            sysenter_eip: value.sysenter_eip,
104            msr_efer: value.msr_efer,
105            msr_star: value.msr_star,
106            msr_lstar: value.msr_lstar,
107            gdtr_base: value.gdtr_base,
108            npt_base: value.npt_base,
109            vmtrace_pos: value.vmtrace_pos,
110            cs_base: value.cs_base,
111            ss_base: value.ss_base,
112            ds_base: value.ds_base,
113            es_base: value.es_base,
114            fs_base: value.fs_base,
115            gs_base: value.gs_base,
116            cs: value.cs.into(),
117            ss: value.ss.into(),
118            ds: value.ds.into(),
119            es: value.es.into(),
120            fs: value.fs.into(),
121            gs: value.gs.into(),
122            shadow_gs: value.shadow_gs,
123            gdtr_limit: value.gdtr_limit,
124            cs_sel: value.cs_sel,
125            ss_sel: value.ss_sel,
126            ds_sel: value.ds_sel,
127            es_sel: value.es_sel,
128            fs_sel: value.fs_sel,
129            gs_sel: value.gs_sel,
130        }
131    }
132}
133
134impl From<VmEventRegsX86> for vm_event_regs_x86 {
135    fn from(value: VmEventRegsX86) -> Self {
136        Self {
137            rax: value.rax,
138            rcx: value.rcx,
139            rdx: value.rdx,
140            rbx: value.rbx,
141            rsp: value.rsp,
142            rbp: value.rbp,
143            rsi: value.rsi,
144            rdi: value.rdi,
145            r8: value.r8,
146            r9: value.r9,
147            r10: value.r10,
148            r11: value.r11,
149            r12: value.r12,
150            r13: value.r13,
151            r14: value.r14,
152            r15: value.r15,
153            rflags: value.rflags,
154            dr6: value.dr6,
155            dr7: value.dr7,
156            rip: value.rip,
157            cr0: value.cr0,
158            cr2: value.cr2,
159            cr3: value.cr3,
160            cr4: value.cr4,
161            sysenter_cs: value.sysenter_cs,
162            sysenter_esp: value.sysenter_esp,
163            sysenter_eip: value.sysenter_eip,
164            msr_efer: value.msr_efer,
165            msr_star: value.msr_star,
166            msr_lstar: value.msr_lstar,
167            gdtr_base: value.gdtr_base,
168            npt_base: value.npt_base,
169            vmtrace_pos: value.vmtrace_pos,
170            cs_base: value.cs_base,
171            ss_base: value.ss_base,
172            ds_base: value.ds_base,
173            es_base: value.es_base,
174            fs_base: value.fs_base,
175            gs_base: value.gs_base,
176            cs: value.cs.into(),
177            ss: value.ss.into(),
178            ds: value.ds.into(),
179            es: value.es.into(),
180            fs: value.fs.into(),
181            gs: value.gs.into(),
182            shadow_gs: value.shadow_gs,
183            gdtr_limit: value.gdtr_limit,
184            cs_sel: value.cs_sel,
185            ss_sel: value.ss_sel,
186            ds_sel: value.ds_sel,
187            es_sel: value.es_sel,
188            fs_sel: value.fs_sel,
189            gs_sel: value.gs_sel,
190            _pad: Default::default(),
191        }
192    }
193}
194
195impl From<vm_event_regs_x86> for VmEventRegs {
196    fn from(value: vm_event_regs_x86) -> Self {
197        Self::X86(value.into())
198    }
199}
200
201impl From<VmEventRegs> for vm_event_regs_x86 {
202    fn from(value: VmEventRegs) -> Self {
203        match value {
204            VmEventRegs::X86(regs) => regs.into(),
205        }
206    }
207}
xen/ctrl/event/arch/x86/regs.rs

xen/ctrl/event/arch/x86/
regs.rs
