librsmsx/
lib.rs

1pub mod dev;
2pub mod libs;
3pub mod prelude;
4
5#[cfg(test)]
6mod tests {
7
8    use std::{cell::RefCell, rc::Rc};
9
10    use super::prelude::*;
11
12    fn check_cycles(ar: &[u8]) -> isize {
13        let ppi = Rc::new(RefCell::new(PPI::new()));
14        let mut memory = Memory::new(ppi.clone());
15        for (i, item) in ar.iter().enumerate() {
16            memory.write_byte(i as u16, *item);
17        }
18        let psg = PSG::new(SoundType::None, None);
19        let vdp = Rc::new(RefCell::new(Vdp::new(GraphicsType::None, false)));
20        let ports = Ports::new(vdp.clone(), ppi.clone(), psg);
21        let mut cpu_z80 = Z80::new(memory, ports);
22        cpu_z80.reboot();
23        cpu_z80.reset_cycles();
24
25        // while !cpu_z80.is_halted() {
26        //     cpu_z80.do_opcode()
27        // }
28        cpu_z80.run_test();
29
30        cpu_z80.get_cycles() as isize
31    }
32
33    #[test]
34    fn test1() {
35        // LD A, 0 (8 cycles)
36        // HALT    (5 cycles)
37        let ar = [0x3e, 0x00, 0x76];
38        let nc = check_cycles(&ar);
39        assert_eq!(nc, 13);
40    }
41
42    #[test]
43    fn test2() {
44        // LD A, 0  (8 cycles)
45        // JP Z, 1  (11 cycles)
46        // HALT     (5 cycles)
47        let ar = [0x3e, 0x00, 0xca, 0x00, 0x00, 0x76];
48        let nc = check_cycles(&ar);
49        assert_eq!(nc, 24);
50    }
51
52    #[test]
53    fn test3() {
54        //     LD B, 5  (8 cycles)
55        // xx: INC A    (5 cycles)
56        //     DJNZ xx  (14/9 cycles)
57        //     HALT     (5 cycles)
58        let ar = [0x06, 0x05, 0x3c, 0x10, 0xfd, 0x76];
59        let nc = check_cycles(&ar);
60        assert_eq!(nc, 103);
61    }
62}
librsmsx/lib.rs

librsmsx/
lib.rs
