libreda_structural_verilog/
lib.rs

1// Copyright (c) 2020-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! This crate provides serialization and deserialization of netlists into the Verilog format used
7//! by Yosys. Reader and writer implement the `NetlistReader` and `NetlistWriter` traits of the LibrEDA data base.
8//!
9//! # Examples
10//!
11//! ## Read a netlist
12//!
13//! A typical netlist uses standard-cells from a library, hence the standard-cells definitions
14//! are not contained in the netlist itself but in an other file.
15//!
16//! In this example, the library netlist is read first such that all standard-cell definitions are loaded
17//! Then the netlist with the actual circuit is loaded.
18//!
19//! ```
20//! use std::fs::File;
21//! use libreda_db::prelude::*;
22//! use libreda_structural_verilog::StructuralVerilogReader;
23//!
24//! // Locations of the library and the netlist.
25//! let library_path = "./tests/test_data/standard_cells.v";
26//! let file_path = "./tests/test_data/my_chip_45_nl.v";
27//! let mut f_library = File::open(library_path).unwrap();
28//! let mut f_netlist = File::open(file_path).unwrap();
29//!
30//! // Create an empty netlist that will be populated from files.
31//! let mut netlist = Chip::new();
32//!
33//! // Create a reader that reads only cell definitions but does not care about
34//! // the internals of the cell.
35//! let library_reader = StructuralVerilogReader::new()
36//!         .load_blackboxes(true);
37//!
38//! // Read the library.
39//! library_reader.read_into_netlist(&mut f_library, &mut netlist).expect("Error while reading library.");
40//!
41//! // Read the netlist with a default reader (does not load black-boxes but populates the cells with content).
42//! let reader = StructuralVerilogReader::new();
43//! reader.read_into_netlist(&mut f_netlist, &mut netlist).expect("Error while reading netlist.");
44//! ```
45
46#![deny(missing_docs)]
47#![deny(unused_imports)]
48
49mod ast;
50mod reader;
51mod writer;
52
53pub use reader::{ParseError, StructuralVerilogReader};
54pub use writer::{StructuralVerilogWriter, VerilogWriteError};
libreda_structural_verilog/lib.rs

libreda_structural_verilog/
lib.rs
