libreda_sta/traits/
timing_library.rs

1// Copyright (c) 2021-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! Trait definitions for accessing timing data.
7//!
8//! * [`TimingLibrary`] Abstraction over timing data.
9
10use uom::si::f64::{Capacitance, Time};
11
12use super::{cell_constraint_model::CellConstraintArc, CellDelayArc};
13
14/// Type of a signal edge. Either rising (0->1), falling (1->0).
15///
16/// See also [`SignalTransition`] which also allows an unspecified signal transition.
17#[derive(Copy, Clone, Debug, Hash, Eq, PartialEq)]
18pub enum RiseFall {
19    /// Rising edge.
20    Rise = 0,
21    /// Falling edge.
22    Fall = 1,
23}
24
25/// Type of a signal edge. Either rising (0->1), falling (1->0) or both of them.
26#[derive(Copy, Clone, Debug, Hash, Eq, PartialEq)]
27pub enum SignalTransition {
28    /// One specific polarity.
29    Unipolar(RiseFall),
30    /// Both types, rising and falling edge.
31    Bipolar,
32}
33
34impl From<RiseFall> for SignalTransition {
35    fn from(p: RiseFall) -> Self {
36        Self::Unipolar(p)
37    }
38}
39
40/// Type of a timing constraint.
41#[derive(Copy, Clone, Debug, Hash, Eq, PartialEq)]
42pub enum SetupHold {
43    /// Signal must remain stable after the related event.
44    Hold,
45    /// Signal must remain stable before the related event.
46    Setup,
47}
48
49/// Bundled arguments for specifying delay arcs.
50#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
51pub struct DelayArcArg<'a, CellId, PinId> {
52    /// Cell.
53    pub cell: &'a CellId,
54    /// Specification of the arc.
55    pub arc: &'a CellDelayArc<PinId>,
56}
57
58/// Bundled arguments for specifying constraint arcs.
59#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
60pub struct ConstraintArcArg<'a, CellId, PinId> {
61    /// Cell.
62    pub cell: &'a CellId,
63    /// Specification of the arc.
64    pub arc: &'a CellConstraintArc<PinId>,
65}
66
67/// Query cell delays and setup/hold constraints.
68// TODO: Consider to remove this trait.
69pub trait TimingLibrary {
70    /// ID type for cells.
71    type CellId;
72    /// ID type for pins.
73    type PinId;
74
75    // fn get_input_capacitance(&self, cell: &str, pin: &str) -> Option<f64>;
76
77    /// Get the transition time (slew) of an output pin.
78    /// The transition time is dependent on the input transition time `input_slew` and the capacitive load
79    /// at the output pin `output_capacitance`.
80    fn get_slew(
81        &self,
82        arc: DelayArcArg<Self::CellId, Self::PinId>,
83        input_slew: Time,
84        output_capacitance: Capacitance,
85    ) -> Option<Time>;
86
87    /// Get the signal propagation time from the `related_pin` to the `output_pin`.
88    /// The delay is dependent on the input transition time `input_slew` and the capacitive load
89    /// at the output pin `output_capacitance`.
90    fn get_cell_delay(
91        &self,
92        arc: DelayArcArg<Self::CellId, Self::PinId>,
93        input_slew: Time,
94        output_capacitance: Capacitance,
95    ) -> Option<Time>;
96
97    /// Get the a constraint between edges of two input signals.
98    /// The 'constrained' edge is usually some data signal with is constrained
99    /// by a clock signal (also called 'related' edge).
100    ///
101    /// * `constrained_edge_polarity`: Polarity of the constrained edge.
102    /// * `edge_polarity`: Polarity of the related edge.
103    fn get_hold_constraint(
104        &self,
105        arc: ConstraintArcArg<Self::CellId, Self::PinId>,
106        related_pin_transition: Time,
107        constrained_pin_transition: Time,
108        output_load: Capacitance,
109    ) -> Option<Time>;
110
111    /// Get the a constraint between edges of two input signals.
112    /// The 'constrained' edge is usually some data signal with is constrained
113    /// by a clock signal (also called 'related' edge).
114    ///
115    /// * `constrained_edge_polarity`: Polarity of the constrained edge.
116    /// * `edge_polarity`: Polarity of the related edge.
117    fn get_setup_constraint(
118        &self,
119        arc: ConstraintArcArg<Self::CellId, Self::PinId>,
120        related_pin_transition: Time,
121        constrained_pin_transition: Time,
122        output_load: Capacitance,
123    ) -> Option<Time>;
124}
libreda_sta/traits/timing_library.rs

libreda_sta/traits/
timing_library.rs
