libreda_sta/traits/
timing_base.rs

1// Copyright (c) 2021-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! Define base types used for static timing analysis.
7
8use crate::{traits::LoadBase, RiseFall};
9
10use blanket::blanket;
11use libreda_logic::logic_value::Logic3;
12
13/// Defines the concept of signals (e.g.  slew rates and actual arrival times) and output loads (e.g. load capacitance).
14#[blanket(derive(Ref))]
15pub trait TimingBase: LoadBase {
16    /// Representation of signals at input or output pins.
17    /// In case of the Non-linear delay model (NLDM) this could be a bundle of the slew rate
18    /// and the delay but also the polarity of the signal.
19    /// But this type could as well also be a statistical representation of a signal, e.g. a probability
20    /// distribution of arrival times.
21    type Signal: Signal<LogicValue = Self::LogicValue>;
22
23    /// Type of logic value.
24    /// Typically this might be a three-valued type which represents logical `0`, `1` and 'unknown'.
25    /// The default is typically 'unknown'.
26    /// This is used to specify static input signals when evaluating cell delays or constraints.
27    type LogicValue: Copy
28        + Clone
29        + std::fmt::Debug
30        + Default
31        + Sync
32        + Send
33        + From<bool>
34        + TryInto<bool>;
35}
36
37/// Representation of signals at input or output pins.
38//#[blanket(derive(Ref))]
39pub trait Signal: Clone + std::fmt::Debug + Sync + Send {
40    /// Type of logic value.
41    /// Typically this might be a three-valued type which represents logical `0`, `1` and 'unknown'.
42    /// The default is typically 'unknown'.
43    /// This is used to specify static input signals when evaluating cell delays or constraints.
44    type LogicValue: Copy + Clone + std::fmt::Debug + Default + Sync + Send;
45
46    /// Get the target value of a signal.
47    fn logic_value(&self) -> Self::LogicValue;
48
49    /// Get the possible type of transition for this signal.
50    fn transition_type(&self) -> SignalTransitionType;
51
52    /// Change or specify the edge polarity of the transition.
53    // TODO: this should not be necessary, remove it
54    fn with_transition_type(self, trans: SignalTransitionType) -> Self;
55}
56
57/// Possible types of binary signal transitions.
58#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
59pub enum SignalTransitionType {
60    /// Signal is at constant (LOW, HIGH or unknown). No transition.
61    Constant(Logic3),
62    /// Signal transitions from LOW to HIGH.
63    Rise,
64    /// Signal transitions from HIGH to LOW.
65    Fall,
66    /// Signal might or might not transition.
67    Any,
68}
69
70impl From<RiseFall> for SignalTransitionType {
71    fn from(value: RiseFall) -> Self {
72        match value {
73            RiseFall::Rise => Self::Rise,
74            RiseFall::Fall => Self::Fall,
75        }
76    }
77}
78
79impl SignalTransitionType {
80    /// Transition type after logically inverting the signal.
81    pub fn inverted(&self) -> Self {
82        use SignalTransitionType::*;
83        match self {
84            Constant(c) => Constant(!*c),
85            Rise => Fall,
86            Fall => Rise,
87            Any => Any,
88        }
89    }
90
91    /// Test if the signal is known to have a constant value.
92    pub fn is_constant(&self) -> bool {
93        matches!(self, Self::Constant(_))
94    }
95}
libreda_sta/traits/timing_base.rs

libreda_sta/traits/
timing_base.rs
