libreda_sta/traits/
cell_delay_model.rs

1// Copyright (c) 2021-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! Abstraction of the cell delay computation.
7
8use super::delay_base::DelayBase;
9use crate::{traits::CellModel, RiseFall};
10use libreda_db::prelude::NetlistIds;
11
12use blanket::blanket;
13
14/// A delay arc within a cell.
15#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
16pub struct CellDelayArc<PinId> {
17    /// Input pin of the delay arc and it's signal edge polarity.
18    pub input_pin: (PinId, RiseFall),
19    /// Output pin of the delay arc and it's signal edge polarity.
20    pub output_pin: (PinId, RiseFall),
21}
22
23// TODO: remove commented code
24// /// Collection of possible output signals.
25// #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug, Default)]
26// pub enum OutputSignals<S> {
27//     #[default]
28//     None,
29//     Constant(Logic3),
30//     Rise(S),
31//     Fall(S),
32//     RiseFall(S, S),
33// }
34
35// impl<S> OutputSignals<S> {
36//     pub fn map<S2>(self, f: impl Fn(S) -> S2) -> OutputSignals<S2> {
37//         use OutputSignals::*;
38//         match self {
39//             None => None,
40//             Constant(c) => Constant(c),
41//             Rise(s) => Rise(f(s)),
42//             Fall(s) => Fall(f(s)),
43//             RiseFall(s1, s2) => RiseFall(f(s1), f(s2)),
44//         }
45//     }
46
47//     pub fn rise(&self) -> Option<&S> {
48//         match &self {
49//             Self::Rise(s) | Self::RiseFall(s, _) => Some(s),
50//             _ => None,
51//         }
52//     }
53
54//     pub fn fall(&self) -> Option<&S> {
55//         match &self {
56//             Self::Fall(s) | Self::RiseFall(_, s) => Some(s),
57//             _ => None,
58//         }
59//     }
60// }
61
62/// Define the computation of the cell delay.
63/// A combinational delay from an input `i` to an output `o` should depend on
64/// * what is attached to the output `o` (the load),
65/// * on what signal arrives at input `i`
66/// * and on the state of the other inputs.
67#[blanket(derive(Ref))]
68pub trait CellDelayModel<N: NetlistIds>: CellModel<N> + DelayBase {
69    /// Propagate a signal from the `input_pin` to the `output_pin`.
70    /// This is used as a more general form of computing the cell delay.
71    /// The `input_pin` and the `output_pin` must be pins of the same cell.
72    ///
73    /// # Parameters
74    /// `other_inputs`: Values at other input pins. If a value is not specified, this implies the default (for example 'unkown').
75    ///
76    /// Returns the output signal or `None` if there is no delay arc from the selected input to selected output.
77    fn cell_output(
78        &self,
79        netlist: &N,
80        arc: &CellDelayArc<N::PinId>,
81        input_signal: &Self::Signal,
82        output_load: &Self::Load,
83        other_inputs: &impl Fn(&N::PinId) -> Option<Self::LogicValue>,
84    ) -> Option<Self::Signal>;
85
86    /// Iterate over the output pins of all delay arcs starting at `related_pin`.
87    fn delay_arcs(
88        &self,
89        netlist: &N,
90        cell_id: &N::CellId,
91    ) -> impl Iterator<Item = CellDelayArc<N::PinId>> + '_;
92}
libreda_sta/traits/cell_delay_model.rs

libreda_sta/traits/
cell_delay_model.rs
