libreda_sta/traits/
mod.rs

1// Copyright (c) 2021-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! Traits for abstracting timing models.
7//!
8//! * [`crate::traits::TimingBase`] defines the concept of signals (e.g.  slew rates and actual arrival times) and output loads (e.g. load capacitance).
9//! * [`crate::traits::DelayBase`] defines the concept of delays between an input signal and an output signal.
10//! * [`crate::traits::CellDelayModel`] defines how delays through a cell can be looked-up. This is then typically implemented by
11//! a timing library such as liberty.
12//! * [`crate::traits::InterconnectDelayModel`] define how interconnect delays can be looked-up.
13//! * [`crate::traits::ConstraintBase`] define the concept of constraints and required signals (e.g. required arrival times).
14//! * [`crate::traits::CellConstraintModel`] define how constraint arcs within cells can be looked-up.
15//!
16//! Types for actual signals, output loads, delays, required signals and constraints are kept abstract.
17//! The idea is to be able to use the same architecture for simple timing models such as the non-linear delay model (NLDM)
18//! but also for more complicated methods like statistical timing analysis. In the latter case a signal
19//! type would for example not only consist of a delay and a slew rate but represent a probability distribution thereof.
20
21pub mod cell_constraint_model;
22pub mod cell_delay_model;
23pub mod cell_load_model;
24pub mod cell_logic_model;
25pub mod cell_model;
26pub mod constraint_base;
27pub mod delay_base;
28pub mod interconnect_delay_model;
29pub mod interconnect_load_model;
30pub mod load_base;
31pub mod timing_base;
32
33pub(crate) mod timing_library;
34
35pub use cell_constraint_model::*;
36pub use cell_delay_model::*;
37pub use cell_load_model::*;
38pub use cell_model::*;
39pub use constraint_base::*;
40pub use delay_base::*;
41pub use interconnect_delay_model::*;
42pub use interconnect_load_model::*;
43pub use load_base::*;
44pub use timing_base::*;
45
46use libreda_db::prelude as db;
47
48use crate::RiseFall;
49
50/// Enhance a netlist with timing queries.
51pub trait TimingQuery: db::NetlistIds {
52    /// Type which defines IDs of netlist components.
53    type NetlistIds: db::NetlistIds;
54
55    /// Type for the actual arrival times.
56    type ArrivalTime;
57    /// Type for required arrival times.
58    type RequiredArrivalTime;
59    /// Type for delays (time difference) such as slack.
60    type Slack: std::fmt::Debug;
61
62    /// Report arrival time.
63    /// Assumes prior call to `update_timing` if the netlist was modified. Might panic otherwise.
64    /// Returns an `Option` because some it is possible that no arrival time is defined (for example
65    /// for a floating part of the netlist which is not attached to a clock).
66    fn report_aat(
67        &self,
68        pin: db::TerminalId<Self::NetlistIds>,
69        edge_polarity: RiseFall,
70    ) -> Option<Self::ArrivalTime>;
71
72    /// Report required arrival time.
73    /// Assumes prior call to `update_timing` if the netlist was modified. Might panic otherwise.
74    fn report_rat(
75        &self,
76        pin: db::TerminalId<Self::NetlistIds>,
77        edge_polarity: RiseFall,
78    ) -> Option<Self::RequiredArrivalTime>;
79
80    /// Report slack (arrival time - required arrival time).
81    /// Assumes prior call to `update_timing` if the netlist was modified. Might panic otherwise.
82    fn report_slack(
83        &self,
84        pin: db::TerminalId<Self::NetlistIds>,
85        edge_polarity: RiseFall,
86    ) -> Option<Self::Slack>;
87
88    /// Report a list of worst paths.
89    fn report_timing(&self) -> Vec<()>;
90}
libreda_sta/traits/mod.rs

libreda_sta/traits/
mod.rs
