libreda_sta/traits/
cell_load_model.rs

1// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
2//
3// SPDX-License-Identifier: AGPL-3.0-or-later
4
5//! Abstraction for computation of electrical loads created by cell input pins.
6
7use crate::traits::{CellModel, LoadBase, TimingBase};
8use libreda_db::traits::NetlistIds;
9
10use blanket::blanket;
11
12/// Abstraction of electrical loads created by input pins.
13#[blanket(derive(Ref))]
14pub trait CellLoadModel<N: NetlistIds>: TimingBase + LoadBase + CellModel<N> {
15    /// Get the load created by a pin, typically its capacitance.
16    fn input_pin_load(
17        &self,
18        input_pin: &N::PinId,
19        other_inputs: &impl Fn(&N::PinId) -> Option<Self::LogicValue>,
20    ) -> Self::Load;
21
22    /// Return a value representing no load at all (zero capacitance for example).
23    fn zero(&self) -> Self::Load;
24}