libreda_sta/traits/
cell_logic_model.rs

1// SPDX-FileCopyrightText: 2023 Thomas Kramer <code@tkramer.ch>
2//
3// SPDX-License-Identifier: AGPL-3.0-or-later
4
5//! Trait for a cell library which provides logic views of the cells.
6
7use liberty_io::boolean::BooleanExpr;
8use libreda_db::traits::NetlistIds;
9use libreda_logic::truth_table::small_lut::SmallTruthTable;
10
11use super::CellModel;
12
13use blanket::blanket;
14
15/// Either a combinational/boolean function or a state-holding element.
16#[derive(Debug, Clone, Default)]
17#[non_exhaustive]
18pub enum OutputFunction<PinId> {
19    /// The output function of the pin is not known.
20    #[default]
21    Unknown,
22    /// Combinational logic: The value of the output pin is defined by a boolean function.
23    Comb(BooleanFn<PinId>),
24    /// Sequential logic: The value of the output pin is defined by a state-holding element.
25    Sequential(Sequential<PinId>),
26}
27
28/// Description of an output pin which is driven by a sequential circuit.
29#[derive(Clone, PartialEq, Eq, Hash, Debug)]
30pub struct Sequential<PinId> {
31    /// The sequential output is updated when at least one
32    /// of the boolean expressions transitions from `false` to `true`.
33    pub clocked_on: Vec<BooleanExpr<PinId>>,
34    /// TODO: Latches:
35    pub transparent_on: Vec<BooleanExpr<PinId>>,
36    //TODO pub data: BooleanExpr<PinOrState<PinId>>,
37    //TODO pub next_state: BooleanExpr<PinOrState<PinId>>,
38}
39
40/// A boolean input which can either be an input pin
41/// or an internal state. Used for storage elements such as flip-flops
42/// and latches.
43#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
44pub enum PinOrState<PinId> {
45    /// An input pin.
46    Pin(PinId),
47    /// An internal state bit.
48    State(usize),
49}
50
51/// Unateness describes a monotonic property of a boolean function.
52/// Usually, unateness is related to a specific input.
53#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
54pub enum Unateness {
55    /// A rising/falling edge at the input can cause both rising and falling edges at the output.
56    #[default]
57    None,
58    /// An edge at the input can only cause edges of the opposite polarity at the output.
59    Negative,
60    /// An edge at the input can only cause edges of the same polarity at the output.
61    Positive,
62}
63
64/// Representation of a boolean function.
65#[derive(Debug, Clone)]
66#[non_exhaustive]
67pub enum BooleanFn<PinId> {
68    /// Logic function with few inputs (6 or less).
69    Small(SmallTruthTable),
70    /// A boolean expression tree.
71    Expr(BooleanExpr<PinId>),
72}
73
74/// Provide logic abstraction of digital cells.
75#[blanket(derive(Ref))]
76pub trait LogicModel<N: NetlistIds>: CellModel<N> {
77    /// Get the logic function of a cell output pin.
78    fn pin_function(&self, output_pin: &N::PinId) -> &OutputFunction<N::PinId>;
79
80    /// Get the unateness of the timing arc.
81    fn timing_sense(
82        &self,
83        output_pin: &N::PinId,
84        related_pin: &N::PinId,
85        other_inputs: &impl Fn(&N::PinId) -> Option<bool>,
86    ) -> Unateness;
87}
libreda_sta/traits/cell_logic_model.rs

libreda_sta/traits/
cell_logic_model.rs
