Module libreda_sta::traits

Traits for abstracting timing models.

• crate::traits::TimingBase defines the concept of signals (e.g. slew rates and actual arrival times) and output loads (e.g. load capacitance).
• crate::traits::DelayBase defines the concept of delays between an input signal and an output signal.
• crate::traits::CellDelayModel defines how delays through a cell can be looked-up. This is then typically implemented by a timing library such as liberty.
• crate::traits::InterconnectDelayModel define how interconnect delays can be looked-up.
• crate::traits::ConstraintBase define the concept of constraints and required signals (e.g. required arrival times).
• crate::traits::CellConstraintModel define how constraint arcs within cells can be looked-up.

Types for actual signals, output loads, delays, required signals and constraints are kept abstract. The idea is to be able to use the same architecture for simple timing models such as the non-linear delay model (NDLM) but also for more complicated methods like statistical timing analysis. In the latter case a signal type would for example not only consist of a delay and a slew rate but represent a probability distribution thereof.

Re-exports

• pub use cell_constraint_model::*;
• pub use cell_delay_model::*;
• pub use cell_load_model::*;
• pub use cell_model::*;
• pub use constraint_base::*;
• pub use delay_base::*;
• pub use interconnect_delay_model::*;
• pub use interconnect_load_model::*;
• pub use load_base::*;
• pub use timing_base::*;

Modules

• cell_constraint_model
  Abstraction of the constraint time computation.
• cell_delay_model
  Abstraction of the cell delay computation.
• cell_load_model
  Abstraction for computation of electrical loads created by cell input pins.
• cell_logic_model
  Trait for a cell library which provides logic views of the cells.
• cell_model
  Base trait for cell delay and constraint models.
• constraint_base
  Abstraction of the constraint computation.
• delay_base
  Abstraction of the delay computation.
• interconnect_delay_model
  Abstraction of the interconnect delay computation.
• interconnect_load_model
  Abstraction of interconnects as electrical loads. For example, the load created by an interconnect could be modelled as a lumped capacitance.
• load_base
  Base trait used as an abstraction of electrical loads.
• timing_base
  Define base types used for static timing analysis.

Traits

• TimingQuery
  Enhance a netlist with timing queries.