Module libreda_sta::models

Model implementations (cell delay and constraints, interconnect delays).

Modules

• clock_tag
  Wrap delay/constraint models and add the capability to tag signals with an associated clock.
• ndlm_cell_delay
  Implementation of the CellDelayModel using the non-linear delay model (NDLM) with data from a liberty library.
• zero_interconnect_delay
  Dummy implementation of an interconnect delay model: The delay is always zero.