libreda_db/reference_access/
mod.rs

1// Copyright (c) 2020-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! # Experimental
7//! Wrappers around the [`trait@crate::traits::HierarchyBase`], [`trait@crate::traits::NetlistBase`], [`trait@crate::traits::LayoutBase`] and [`trait@crate::traits::L2NBase`] traits which
8//! provide more object like access methods.
9//!
10//! # Examples
11//!
12//! ```
13//! use libreda_db::prelude::*;
14//!
15//! // Create some netlist/layout.
16//! let mut chip = Chip::new();
17//! let top_id = chip.create_cell("TOP".into());
18//! let sub_id = chip.create_cell("SUB".into());
19//! let sub_inst1_id = chip.create_cell_instance(&top_id, &sub_id, Some("inst1".into()));
20//!
21//! // Create read-only object-like access.
22//! let top = chip.cell_ref(&top_id);
23//! // `top` can now be used like an object to navigate the cell hierarchy, layout and netlist.
24//! for subcell in top.each_cell_instance() {
25//!     println!("{} contains {:?} which is a {}", top.name(), subcell.name(), subcell.template().name());
26//! }
27//!
28//! // Also the netlist can be traversed in a similar way.
29//! for pin in top.each_pin() {
30//!     println!("Pin {} of {} is connected to net {:?}.",
31//!         pin.name(), top.name(), pin.net().and_then(|net| net.name())
32//!     );
33//! }
34//! ```
35
36mod hierarchy_reference_access;
37mod l2n_reference_access;
38mod layout_reference_access;
39mod netlist_reference_access;
40
41// Public exports.
42pub use hierarchy_reference_access::*;
43pub use layout_reference_access::*;
44pub use netlist_reference_access::*;
45
46#[test]
47fn test_chip_reference_access() {
48    use crate::chip::Chip;
49    use crate::prelude::*;
50
51    let mut chip = Chip::new();
52    let top = chip.create_cell("TOP".into());
53    chip.create_pin(&top, "A".into(), Direction::Input);
54    let sub = chip.create_cell("SUB".into());
55    chip.create_pin(&sub, "B".into(), Direction::Input);
56    let sub_inst1 = chip.create_cell_instance(&top, &sub, Some("inst1".into()));
57
58    let top_ref = chip.cell_ref(&top);
59    assert_eq!(&top_ref.id(), &top);
60
61    let sub_inst1_ref = chip.cell_instance_ref(&sub_inst1);
62    assert_eq!(&sub_inst1_ref.id(), &sub_inst1);
63    assert_eq!(sub_inst1_ref.parent().id(), top_ref.id());
64    assert_eq!(&sub_inst1_ref.template().id(), &sub);
65
66    // Access nets and pins.
67    assert_eq!(
68        top_ref.each_net().count(),
69        2,
70        "LOW and HIGH nets should be there."
71    );
72    assert_eq!(top_ref.each_pin().count(), 1);
73    assert_eq!(sub_inst1_ref.each_pin_instance().count(), 1);
74}
libreda_db/reference_access/mod.rs

libreda_db/reference_access/
mod.rs
