libreda_db/netlist/
direction.rs

1// Copyright (c) 2020-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! The type of a pin is specified by a signal direction.
7
8/// Signal type for pins.
9#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq, Default)]
10#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
11pub enum Direction {
12    /// No direction specified.
13    #[default]
14    None,
15    /// Data input.
16    Input,
17    /// Data output.
18    Output,
19    /// Input and output.
20    InOut,
21    /// Clock input.
22    Clock,
23    /// Power VDD.
24    Supply,
25    /// Power ground.
26    Ground,
27}
28
29impl Direction {
30    /// Check if this direction is 'input'.
31    pub fn is_input(&self) -> bool {
32        self == &Direction::Input
33    }
34    /// Check if this direction is 'output'.
35    pub fn is_output(&self) -> bool {
36        self == &Direction::Output
37    }
38
39    /// Check if this direciton is either 'Supply' or 'Ground'.
40    pub fn is_power(&self) -> bool {
41        matches!(self, Direction::Supply | Direction::Ground)
42    }
43}
libreda_db/netlist/direction.rs

libreda_db/netlist/
direction.rs
