Type Alias nvme_register_offsets 

pub type nvme_register_offsets = c_uint;

enum nvme_register_offsets - controller registers for all transports. This is the layout of BAR0/1 for PCIe, and properties for fabrics. @NVME_REG_CAP: Controller Capabilities @NVME_REG_VS: Version @NVME_REG_INTMS: Interrupt Mask Set @NVME_REG_INTMC: Interrupt Mask Clear @NVME_REG_CC: Controller Configuration @NVME_REG_CSTS: Controller Status @NVME_REG_NSSR: NVM Subsystem Reset @NVME_REG_AQA: Admin Queue Attributes @NVME_REG_ASQ: Admin SQ Base Address @NVME_REG_ACQ: Admin CQ Base Address @NVME_REG_CMBLOC: Controller Memory Buffer Location @NVME_REG_CMBSZ: Controller Memory Buffer Size @NVME_REG_BPINFO: Boot Partition Information @NVME_REG_BPRSEL: Boot Partition Read Select @NVME_REG_BPMBL: Boot Partition Memory Buffer Location @NVME_REG_CMBMSC: Controller Memory Buffer Memory Space Control @NVME_REG_CMBSTS: Controller Memory Buffer Status @NVME_REG_CMBEBS: Controller Memory Buffer Elasticity Buffer Size @NVME_REG_CMBSWTP: Controller Memory Buffer Sustained Write Throughput @NVME_REG_NSSD: NVM Subsystem Shutdown @NVME_REG_CRTO: Controller Ready Timeouts @NVME_REG_PMRCAP: Persistent Memory Capabilities @NVME_REG_PMRCTL: Persistent Memory Region Control @NVME_REG_PMRSTS: Persistent Memory Region Status @NVME_REG_PMREBS: Persistent Memory Region Elasticity Buffer Size @NVME_REG_PMRSWTP: Memory Region Sustained Write Throughput @NVME_REG_PMRMSCL: Persistent Memory Region Controller Memory Space Control Lower @NVME_REG_PMRMSCU: Persistent Memory Region Controller Memory Space Control Upper