Enum libftd2xx_cc1101::regs::GDOCfg [−][src]
#[repr(u8)]
pub enum GDOCfg {
Show variants
RxFifoThreshold,
RxFifoThresholdEmpty,
TxFifoThreshold,
TxFifoThresholdEmpty,
RxFifoOverflow,
TxFifoUnderflow,
SyncWord,
PacketReceived,
PreambleQualityReached,
ClearChannel,
LockDetected,
SerialClock,
SerialSynchronousData,
SerialAsynchronousData,
CarrierSense,
CrcOk,
RxHardData1,
RxHardData0,
PaPd,
LnaPd,
RxSymbolTick,
WorEvnt0,
WorEvnt1,
Clk256,
Clk32k,
ChipRdyN,
XOscStable,
HighZ,
HwTo0,
ClkXOsc1,
ClkXOsc1_5,
ClkXOsc2,
ClkXOsc3,
ClkXOsc4,
ClkXOsc6,
ClkXOsc8,
ClkXOsc12,
ClkXOsc16,
ClkXOsc24,
ClkXOsc32,
ClkXOsc48,
ClkXOsc64,
ClkXOsc96,
ClkXOsc128,
ClkXOsc192,
}Expand description
General Purpose / Test Output Control Pins Configuration
Selects GDOx pin signal
Variants
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO is drained below the same threshold.
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is reached. De-asserts when the RX FIFO is empty.
Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX FIFO is below the same threshold.
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below the TX FIFO threshold.
Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will also de-assert when a packet is discarded due to address or maximum length filtering or when the radio enters RXFIFO_OVERFLOW state. In TX the pin will de-assert if the TX FIFO underflows.
Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO.
Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.De-asserted when the chip re-enters RX state (MARCSTATE=0x0D) or the PQI gets below the programmed PQT value.
Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting).
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.In RX mode, data is set up on the falling edge by CC1101 when GDOx_INV=0. In TX mode, data is sampled by CC1101 on the rising edge of the serial clock when GDOx_INV=0.
Serial Synchronous Data Output. Used for synchronous serial mode.
Serial Data Output. Used for asynchronous serial mode.
Carrier sense. High if RSSI level is above threshold.Cleared when entering IDLE mode.
The last CRC comparison matched. Cleared when entering/restarting RX mode.
Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
Note: PA_PD willhave the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
Can be used together with RX_HARD_DATA for alternative serial RX output.
WOR_EVNT0
WOR_EVNT1
CLK_256
CLK_32k
CHIP_RDYn
XOSC_STABLE
High impedance (3-state)
HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch.
CLK_XOSC/1
CLK_XOSC/1.5
CLK_XOSC/2
CLK_XOSC/3
CLK_XOSC/4
CLK_XOSC/6
CLK_XOSC/8
CLK_XOSC/12
CLK_XOSC/16
CLK_XOSC/24
CLK_XOSC/32
CLK_XOSC/48
CLK_XOSC/64
CLK_XOSC/96
CLK_XOSC/128
CLK_XOSC/192
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for GDOCfgimpl UnwindSafe for GDOCfg