1#[repr(C)]
4#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
5pub struct __BindgenBitfieldUnit<Storage> {
6 storage: Storage,
7}
8impl<Storage> __BindgenBitfieldUnit<Storage> {
9 #[inline]
10 pub const fn new(storage: Storage) -> Self {
11 Self { storage }
12 }
13}
14impl<Storage> __BindgenBitfieldUnit<Storage>
15where
16 Storage: AsRef<[u8]> + AsMut<[u8]>,
17{
18 #[inline]
19 fn extract_bit(byte: u8, index: usize) -> bool {
20 let bit_index = if cfg!(target_endian = "big") {
21 7 - (index % 8)
22 } else {
23 index % 8
24 };
25 let mask = 1 << bit_index;
26 byte & mask == mask
27 }
28 #[inline]
29 pub fn get_bit(&self, index: usize) -> bool {
30 debug_assert!(index / 8 < self.storage.as_ref().len());
31 let byte_index = index / 8;
32 let byte = self.storage.as_ref()[byte_index];
33 Self::extract_bit(byte, index)
34 }
35 #[inline]
36 pub unsafe fn raw_get_bit(this: *const Self, index: usize) -> bool {
37 debug_assert!(index / 8 < core::mem::size_of::<Storage>());
38 let byte_index = index / 8;
39 let byte = unsafe {
40 *(core::ptr::addr_of!((*this).storage) as *const u8).offset(byte_index as isize)
41 };
42 Self::extract_bit(byte, index)
43 }
44 #[inline]
45 fn change_bit(byte: u8, index: usize, val: bool) -> u8 {
46 let bit_index = if cfg!(target_endian = "big") {
47 7 - (index % 8)
48 } else {
49 index % 8
50 };
51 let mask = 1 << bit_index;
52 if val { byte | mask } else { byte & !mask }
53 }
54 #[inline]
55 pub fn set_bit(&mut self, index: usize, val: bool) {
56 debug_assert!(index / 8 < self.storage.as_ref().len());
57 let byte_index = index / 8;
58 let byte = &mut self.storage.as_mut()[byte_index];
59 *byte = Self::change_bit(*byte, index, val);
60 }
61 #[inline]
62 pub unsafe fn raw_set_bit(this: *mut Self, index: usize, val: bool) {
63 debug_assert!(index / 8 < core::mem::size_of::<Storage>());
64 let byte_index = index / 8;
65 let byte = unsafe {
66 (core::ptr::addr_of_mut!((*this).storage) as *mut u8).offset(byte_index as isize)
67 };
68 unsafe { *byte = Self::change_bit(*byte, index, val) };
69 }
70 #[inline]
71 pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
72 debug_assert!(bit_width <= 64);
73 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
74 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
75 let mut val = 0;
76 for i in 0..(bit_width as usize) {
77 if self.get_bit(i + bit_offset) {
78 let index = if cfg!(target_endian = "big") {
79 bit_width as usize - 1 - i
80 } else {
81 i
82 };
83 val |= 1 << index;
84 }
85 }
86 val
87 }
88 #[inline]
89 pub unsafe fn raw_get(this: *const Self, bit_offset: usize, bit_width: u8) -> u64 {
90 debug_assert!(bit_width <= 64);
91 debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
92 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
93 let mut val = 0;
94 for i in 0..(bit_width as usize) {
95 if unsafe { Self::raw_get_bit(this, i + bit_offset) } {
96 let index = if cfg!(target_endian = "big") {
97 bit_width as usize - 1 - i
98 } else {
99 i
100 };
101 val |= 1 << index;
102 }
103 }
104 val
105 }
106 #[inline]
107 pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
108 debug_assert!(bit_width <= 64);
109 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
110 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
111 for i in 0..(bit_width as usize) {
112 let mask = 1 << i;
113 let val_bit_is_set = val & mask == mask;
114 let index = if cfg!(target_endian = "big") {
115 bit_width as usize - 1 - i
116 } else {
117 i
118 };
119 self.set_bit(index + bit_offset, val_bit_is_set);
120 }
121 }
122 #[inline]
123 pub unsafe fn raw_set(this: *mut Self, bit_offset: usize, bit_width: u8, val: u64) {
124 debug_assert!(bit_width <= 64);
125 debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
126 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
127 for i in 0..(bit_width as usize) {
128 let mask = 1 << i;
129 let val_bit_is_set = val & mask == mask;
130 let index = if cfg!(target_endian = "big") {
131 bit_width as usize - 1 - i
132 } else {
133 i
134 };
135 unsafe { Self::raw_set_bit(this, index + bit_offset, val_bit_is_set) };
136 }
137 }
138}
139#[repr(C)]
140#[derive(Default)]
141pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]);
142impl<T> __IncompleteArrayField<T> {
143 #[inline]
144 pub const fn new() -> Self {
145 __IncompleteArrayField(::core::marker::PhantomData, [])
146 }
147 #[inline]
148 pub fn as_ptr(&self) -> *const T {
149 self as *const _ as *const T
150 }
151 #[inline]
152 pub fn as_mut_ptr(&mut self) -> *mut T {
153 self as *mut _ as *mut T
154 }
155 #[inline]
156 pub unsafe fn as_slice(&self, len: usize) -> &[T] {
157 unsafe { ::core::slice::from_raw_parts(self.as_ptr(), len) }
158 }
159 #[inline]
160 pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] {
161 unsafe { ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len) }
162 }
163}
164impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> {
165 fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
166 fmt.write_str("__IncompleteArrayField")
167 }
168}
169pub const _SYS_TYPES_H: u32 = 1;
170pub const _FEATURES_H: u32 = 1;
171pub const _DEFAULT_SOURCE: u32 = 1;
172pub const __GLIBC_USE_ISOC2Y: u32 = 0;
173pub const __GLIBC_USE_ISOC23: u32 = 0;
174pub const __USE_ISOC11: u32 = 1;
175pub const __USE_ISOC99: u32 = 1;
176pub const __USE_ISOC95: u32 = 1;
177pub const __USE_POSIX_IMPLICITLY: u32 = 1;
178pub const _POSIX_SOURCE: u32 = 1;
179pub const _POSIX_C_SOURCE: u32 = 200809;
180pub const __USE_POSIX: u32 = 1;
181pub const __USE_POSIX2: u32 = 1;
182pub const __USE_POSIX199309: u32 = 1;
183pub const __USE_POSIX199506: u32 = 1;
184pub const __USE_XOPEN2K: u32 = 1;
185pub const __USE_XOPEN2K8: u32 = 1;
186pub const _ATFILE_SOURCE: u32 = 1;
187pub const __WORDSIZE: u32 = 64;
188pub const __WORDSIZE_TIME64_COMPAT32: u32 = 1;
189pub const __SYSCALL_WORDSIZE: u32 = 64;
190pub const __TIMESIZE: u32 = 64;
191pub const __USE_TIME_BITS64: u32 = 1;
192pub const __USE_MISC: u32 = 1;
193pub const __USE_ATFILE: u32 = 1;
194pub const __USE_FORTIFY_LEVEL: u32 = 0;
195pub const __GLIBC_USE_DEPRECATED_GETS: u32 = 0;
196pub const __GLIBC_USE_DEPRECATED_SCANF: u32 = 0;
197pub const __GLIBC_USE_C23_STRTOL: u32 = 0;
198pub const _STDC_PREDEF_H: u32 = 1;
199pub const __STDC_IEC_559__: u32 = 1;
200pub const __STDC_IEC_60559_BFP__: u32 = 201404;
201pub const __STDC_IEC_559_COMPLEX__: u32 = 1;
202pub const __STDC_IEC_60559_COMPLEX__: u32 = 201404;
203pub const __STDC_ISO_10646__: u32 = 201706;
204pub const __GNU_LIBRARY__: u32 = 6;
205pub const __GLIBC__: u32 = 2;
206pub const __GLIBC_MINOR__: u32 = 42;
207pub const _SYS_CDEFS_H: u32 = 1;
208pub const __glibc_c99_flexarr_available: u32 = 1;
209pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI: u32 = 0;
210pub const __HAVE_GENERIC_SELECTION: u32 = 1;
211pub const _BITS_TYPES_H: u32 = 1;
212pub const _BITS_TYPESIZES_H: u32 = 1;
213pub const __OFF_T_MATCHES_OFF64_T: u32 = 1;
214pub const __INO_T_MATCHES_INO64_T: u32 = 1;
215pub const __RLIM_T_MATCHES_RLIM64_T: u32 = 1;
216pub const __STATFS_MATCHES_STATFS64: u32 = 1;
217pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64: u32 = 1;
218pub const __FD_SETSIZE: u32 = 1024;
219pub const _BITS_TIME64_H: u32 = 1;
220pub const __clock_t_defined: u32 = 1;
221pub const __clockid_t_defined: u32 = 1;
222pub const __time_t_defined: u32 = 1;
223pub const __timer_t_defined: u32 = 1;
224pub const _BITS_STDINT_INTN_H: u32 = 1;
225pub const __BIT_TYPES_DEFINED__: u32 = 1;
226pub const _ENDIAN_H: u32 = 1;
227pub const _BITS_ENDIAN_H: u32 = 1;
228pub const __LITTLE_ENDIAN: u32 = 1234;
229pub const __BIG_ENDIAN: u32 = 4321;
230pub const __PDP_ENDIAN: u32 = 3412;
231pub const _BITS_ENDIANNESS_H: u32 = 1;
232pub const __BYTE_ORDER: u32 = 1234;
233pub const __FLOAT_WORD_ORDER: u32 = 1234;
234pub const LITTLE_ENDIAN: u32 = 1234;
235pub const BIG_ENDIAN: u32 = 4321;
236pub const PDP_ENDIAN: u32 = 3412;
237pub const BYTE_ORDER: u32 = 1234;
238pub const _BITS_BYTESWAP_H: u32 = 1;
239pub const _BITS_UINTN_IDENTITY_H: u32 = 1;
240pub const _SYS_SELECT_H: u32 = 1;
241pub const __sigset_t_defined: u32 = 1;
242pub const __timeval_defined: u32 = 1;
243pub const _STRUCT_TIMESPEC: u32 = 1;
244pub const FD_SETSIZE: u32 = 1024;
245pub const _BITS_PTHREADTYPES_COMMON_H: u32 = 1;
246pub const _THREAD_SHARED_TYPES_H: u32 = 1;
247pub const _BITS_PTHREADTYPES_ARCH_H: u32 = 1;
248pub const __SIZEOF_PTHREAD_MUTEX_T: u32 = 40;
249pub const __SIZEOF_PTHREAD_ATTR_T: u32 = 56;
250pub const __SIZEOF_PTHREAD_RWLOCK_T: u32 = 56;
251pub const __SIZEOF_PTHREAD_BARRIER_T: u32 = 32;
252pub const __SIZEOF_PTHREAD_MUTEXATTR_T: u32 = 4;
253pub const __SIZEOF_PTHREAD_COND_T: u32 = 48;
254pub const __SIZEOF_PTHREAD_CONDATTR_T: u32 = 4;
255pub const __SIZEOF_PTHREAD_RWLOCKATTR_T: u32 = 8;
256pub const __SIZEOF_PTHREAD_BARRIERATTR_T: u32 = 4;
257pub const _THREAD_MUTEX_INTERNAL_H: u32 = 1;
258pub const __PTHREAD_MUTEX_HAVE_PREV: u32 = 1;
259pub const __have_pthread_attr_t: u32 = 1;
260pub const _STDINT_H: u32 = 1;
261pub const __GLIBC_USE_LIB_EXT2: u32 = 0;
262pub const __GLIBC_USE_IEC_60559_BFP_EXT: u32 = 0;
263pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23: u32 = 0;
264pub const __GLIBC_USE_IEC_60559_EXT: u32 = 0;
265pub const __GLIBC_USE_IEC_60559_FUNCS_EXT: u32 = 0;
266pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23: u32 = 0;
267pub const __GLIBC_USE_IEC_60559_TYPES_EXT: u32 = 0;
268pub const _BITS_WCHAR_H: u32 = 1;
269pub const _BITS_STDINT_UINTN_H: u32 = 1;
270pub const _BITS_STDINT_LEAST_H: u32 = 1;
271pub const INT8_MIN: i32 = -128;
272pub const INT16_MIN: i32 = -32768;
273pub const INT32_MIN: i32 = -2147483648;
274pub const INT8_MAX: u32 = 127;
275pub const INT16_MAX: u32 = 32767;
276pub const INT32_MAX: u32 = 2147483647;
277pub const UINT8_MAX: u32 = 255;
278pub const UINT16_MAX: u32 = 65535;
279pub const UINT32_MAX: u32 = 4294967295;
280pub const INT_LEAST8_MIN: i32 = -128;
281pub const INT_LEAST16_MIN: i32 = -32768;
282pub const INT_LEAST32_MIN: i32 = -2147483648;
283pub const INT_LEAST8_MAX: u32 = 127;
284pub const INT_LEAST16_MAX: u32 = 32767;
285pub const INT_LEAST32_MAX: u32 = 2147483647;
286pub const UINT_LEAST8_MAX: u32 = 255;
287pub const UINT_LEAST16_MAX: u32 = 65535;
288pub const UINT_LEAST32_MAX: u32 = 4294967295;
289pub const INT_FAST8_MIN: i32 = -128;
290pub const INT_FAST16_MIN: i64 = -9223372036854775808;
291pub const INT_FAST32_MIN: i64 = -9223372036854775808;
292pub const INT_FAST8_MAX: u32 = 127;
293pub const INT_FAST16_MAX: u64 = 9223372036854775807;
294pub const INT_FAST32_MAX: u64 = 9223372036854775807;
295pub const UINT_FAST8_MAX: u32 = 255;
296pub const UINT_FAST16_MAX: i32 = -1;
297pub const UINT_FAST32_MAX: i32 = -1;
298pub const INTPTR_MIN: i64 = -9223372036854775808;
299pub const INTPTR_MAX: u64 = 9223372036854775807;
300pub const UINTPTR_MAX: i32 = -1;
301pub const PTRDIFF_MIN: i64 = -9223372036854775808;
302pub const PTRDIFF_MAX: u64 = 9223372036854775807;
303pub const SIG_ATOMIC_MIN: i32 = -2147483648;
304pub const SIG_ATOMIC_MAX: u32 = 2147483647;
305pub const SIZE_MAX: i32 = -1;
306pub const WINT_MIN: u32 = 0;
307pub const WINT_MAX: u32 = 4294967295;
308pub const __BITS_PER_LONG: u32 = 64;
309pub const __BITS_PER_LONG_LONG: u32 = 64;
310pub const _IOC_NRBITS: u32 = 8;
311pub const _IOC_TYPEBITS: u32 = 8;
312pub const _IOC_SIZEBITS: u32 = 14;
313pub const _IOC_DIRBITS: u32 = 2;
314pub const _IOC_NRMASK: u32 = 255;
315pub const _IOC_TYPEMASK: u32 = 255;
316pub const _IOC_SIZEMASK: u32 = 16383;
317pub const _IOC_DIRMASK: u32 = 3;
318pub const _IOC_NRSHIFT: u32 = 0;
319pub const _IOC_TYPESHIFT: u32 = 8;
320pub const _IOC_SIZESHIFT: u32 = 16;
321pub const _IOC_DIRSHIFT: u32 = 30;
322pub const _IOC_NONE: u32 = 0;
323pub const _IOC_WRITE: u32 = 1;
324pub const _IOC_READ: u32 = 2;
325pub const IOC_IN: u32 = 1073741824;
326pub const IOC_OUT: u32 = 2147483648;
327pub const IOC_INOUT: u32 = 3221225472;
328pub const IOCSIZE_MASK: u32 = 1073676288;
329pub const IOCSIZE_SHIFT: u32 = 16;
330pub const DRM_NAME: &[u8; 4] = b"drm\0";
331pub const DRM_MIN_ORDER: u32 = 5;
332pub const DRM_MAX_ORDER: u32 = 22;
333pub const DRM_RAM_PERCENT: u32 = 10;
334pub const _DRM_LOCK_HELD: u32 = 2147483648;
335pub const _DRM_LOCK_CONT: u32 = 1073741824;
336pub const _DRM_VBLANK_HIGH_CRTC_SHIFT: u32 = 1;
337pub const _DRM_PRE_MODESET: u32 = 1;
338pub const _DRM_POST_MODESET: u32 = 2;
339pub const DRM_CAP_DUMB_BUFFER: u32 = 1;
340pub const DRM_CAP_VBLANK_HIGH_CRTC: u32 = 2;
341pub const DRM_CAP_DUMB_PREFERRED_DEPTH: u32 = 3;
342pub const DRM_CAP_DUMB_PREFER_SHADOW: u32 = 4;
343pub const DRM_CAP_PRIME: u32 = 5;
344pub const DRM_PRIME_CAP_IMPORT: u32 = 1;
345pub const DRM_PRIME_CAP_EXPORT: u32 = 2;
346pub const DRM_CAP_TIMESTAMP_MONOTONIC: u32 = 6;
347pub const DRM_CAP_ASYNC_PAGE_FLIP: u32 = 7;
348pub const DRM_CAP_CURSOR_WIDTH: u32 = 8;
349pub const DRM_CAP_CURSOR_HEIGHT: u32 = 9;
350pub const DRM_CAP_ADDFB2_MODIFIERS: u32 = 16;
351pub const DRM_CAP_PAGE_FLIP_TARGET: u32 = 17;
352pub const DRM_CAP_CRTC_IN_VBLANK_EVENT: u32 = 18;
353pub const DRM_CAP_SYNCOBJ: u32 = 19;
354pub const DRM_CAP_SYNCOBJ_TIMELINE: u32 = 20;
355pub const DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP: u32 = 21;
356pub const DRM_CLIENT_CAP_STEREO_3D: u32 = 1;
357pub const DRM_CLIENT_CAP_UNIVERSAL_PLANES: u32 = 2;
358pub const DRM_CLIENT_CAP_ATOMIC: u32 = 3;
359pub const DRM_CLIENT_CAP_ASPECT_RATIO: u32 = 4;
360pub const DRM_CLIENT_CAP_WRITEBACK_CONNECTORS: u32 = 5;
361pub const DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT: u32 = 6;
362pub const DRM_SYNCOBJ_CREATE_SIGNALED: u32 = 1;
363pub const DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE: u32 = 1;
364pub const DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE: u32 = 1;
365pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL: u32 = 1;
366pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT: u32 = 2;
367pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE: u32 = 4;
368pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE: u32 = 8;
369pub const DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED: u32 = 1;
370pub const DRM_CRTC_SEQUENCE_RELATIVE: u32 = 1;
371pub const DRM_CRTC_SEQUENCE_NEXT_ON_MISS: u32 = 2;
372pub const DRM_CONNECTOR_NAME_LEN: u32 = 32;
373pub const DRM_DISPLAY_MODE_LEN: u32 = 32;
374pub const DRM_PROP_NAME_LEN: u32 = 32;
375pub const DRM_MODE_TYPE_BUILTIN: u32 = 1;
376pub const DRM_MODE_TYPE_CLOCK_C: u32 = 3;
377pub const DRM_MODE_TYPE_CRTC_C: u32 = 5;
378pub const DRM_MODE_TYPE_PREFERRED: u32 = 8;
379pub const DRM_MODE_TYPE_DEFAULT: u32 = 16;
380pub const DRM_MODE_TYPE_USERDEF: u32 = 32;
381pub const DRM_MODE_TYPE_DRIVER: u32 = 64;
382pub const DRM_MODE_TYPE_ALL: u32 = 104;
383pub const DRM_MODE_FLAG_PHSYNC: u32 = 1;
384pub const DRM_MODE_FLAG_NHSYNC: u32 = 2;
385pub const DRM_MODE_FLAG_PVSYNC: u32 = 4;
386pub const DRM_MODE_FLAG_NVSYNC: u32 = 8;
387pub const DRM_MODE_FLAG_INTERLACE: u32 = 16;
388pub const DRM_MODE_FLAG_DBLSCAN: u32 = 32;
389pub const DRM_MODE_FLAG_CSYNC: u32 = 64;
390pub const DRM_MODE_FLAG_PCSYNC: u32 = 128;
391pub const DRM_MODE_FLAG_NCSYNC: u32 = 256;
392pub const DRM_MODE_FLAG_HSKEW: u32 = 512;
393pub const DRM_MODE_FLAG_BCAST: u32 = 1024;
394pub const DRM_MODE_FLAG_PIXMUX: u32 = 2048;
395pub const DRM_MODE_FLAG_DBLCLK: u32 = 4096;
396pub const DRM_MODE_FLAG_CLKDIV2: u32 = 8192;
397pub const DRM_MODE_FLAG_3D_MASK: u32 = 507904;
398pub const DRM_MODE_FLAG_3D_NONE: u32 = 0;
399pub const DRM_MODE_FLAG_3D_FRAME_PACKING: u32 = 16384;
400pub const DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: u32 = 32768;
401pub const DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: u32 = 49152;
402pub const DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: u32 = 65536;
403pub const DRM_MODE_FLAG_3D_L_DEPTH: u32 = 81920;
404pub const DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: u32 = 98304;
405pub const DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: u32 = 114688;
406pub const DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: u32 = 131072;
407pub const DRM_MODE_PICTURE_ASPECT_NONE: u32 = 0;
408pub const DRM_MODE_PICTURE_ASPECT_4_3: u32 = 1;
409pub const DRM_MODE_PICTURE_ASPECT_16_9: u32 = 2;
410pub const DRM_MODE_PICTURE_ASPECT_64_27: u32 = 3;
411pub const DRM_MODE_PICTURE_ASPECT_256_135: u32 = 4;
412pub const DRM_MODE_CONTENT_TYPE_NO_DATA: u32 = 0;
413pub const DRM_MODE_CONTENT_TYPE_GRAPHICS: u32 = 1;
414pub const DRM_MODE_CONTENT_TYPE_PHOTO: u32 = 2;
415pub const DRM_MODE_CONTENT_TYPE_CINEMA: u32 = 3;
416pub const DRM_MODE_CONTENT_TYPE_GAME: u32 = 4;
417pub const DRM_MODE_FLAG_PIC_AR_MASK: u32 = 7864320;
418pub const DRM_MODE_FLAG_PIC_AR_NONE: u32 = 0;
419pub const DRM_MODE_FLAG_PIC_AR_4_3: u32 = 524288;
420pub const DRM_MODE_FLAG_PIC_AR_16_9: u32 = 1048576;
421pub const DRM_MODE_FLAG_PIC_AR_64_27: u32 = 1572864;
422pub const DRM_MODE_FLAG_PIC_AR_256_135: u32 = 2097152;
423pub const DRM_MODE_FLAG_ALL: u32 = 521215;
424pub const DRM_MODE_DPMS_ON: u32 = 0;
425pub const DRM_MODE_DPMS_STANDBY: u32 = 1;
426pub const DRM_MODE_DPMS_SUSPEND: u32 = 2;
427pub const DRM_MODE_DPMS_OFF: u32 = 3;
428pub const DRM_MODE_SCALE_NONE: u32 = 0;
429pub const DRM_MODE_SCALE_FULLSCREEN: u32 = 1;
430pub const DRM_MODE_SCALE_CENTER: u32 = 2;
431pub const DRM_MODE_SCALE_ASPECT: u32 = 3;
432pub const DRM_MODE_DITHERING_OFF: u32 = 0;
433pub const DRM_MODE_DITHERING_ON: u32 = 1;
434pub const DRM_MODE_DITHERING_AUTO: u32 = 2;
435pub const DRM_MODE_DIRTY_OFF: u32 = 0;
436pub const DRM_MODE_DIRTY_ON: u32 = 1;
437pub const DRM_MODE_DIRTY_ANNOTATE: u32 = 2;
438pub const DRM_MODE_LINK_STATUS_GOOD: u32 = 0;
439pub const DRM_MODE_LINK_STATUS_BAD: u32 = 1;
440pub const DRM_MODE_ROTATE_0: u32 = 1;
441pub const DRM_MODE_ROTATE_90: u32 = 2;
442pub const DRM_MODE_ROTATE_180: u32 = 4;
443pub const DRM_MODE_ROTATE_270: u32 = 8;
444pub const DRM_MODE_ROTATE_MASK: u32 = 15;
445pub const DRM_MODE_REFLECT_X: u32 = 16;
446pub const DRM_MODE_REFLECT_Y: u32 = 32;
447pub const DRM_MODE_REFLECT_MASK: u32 = 48;
448pub const DRM_MODE_CONTENT_PROTECTION_UNDESIRED: u32 = 0;
449pub const DRM_MODE_CONTENT_PROTECTION_DESIRED: u32 = 1;
450pub const DRM_MODE_CONTENT_PROTECTION_ENABLED: u32 = 2;
451pub const DRM_MODE_PRESENT_TOP_FIELD: u32 = 1;
452pub const DRM_MODE_PRESENT_BOTTOM_FIELD: u32 = 2;
453pub const DRM_MODE_ENCODER_NONE: u32 = 0;
454pub const DRM_MODE_ENCODER_DAC: u32 = 1;
455pub const DRM_MODE_ENCODER_TMDS: u32 = 2;
456pub const DRM_MODE_ENCODER_LVDS: u32 = 3;
457pub const DRM_MODE_ENCODER_TVDAC: u32 = 4;
458pub const DRM_MODE_ENCODER_VIRTUAL: u32 = 5;
459pub const DRM_MODE_ENCODER_DSI: u32 = 6;
460pub const DRM_MODE_ENCODER_DPMST: u32 = 7;
461pub const DRM_MODE_ENCODER_DPI: u32 = 8;
462pub const DRM_MODE_CONNECTOR_Unknown: u32 = 0;
463pub const DRM_MODE_CONNECTOR_VGA: u32 = 1;
464pub const DRM_MODE_CONNECTOR_DVII: u32 = 2;
465pub const DRM_MODE_CONNECTOR_DVID: u32 = 3;
466pub const DRM_MODE_CONNECTOR_DVIA: u32 = 4;
467pub const DRM_MODE_CONNECTOR_Composite: u32 = 5;
468pub const DRM_MODE_CONNECTOR_SVIDEO: u32 = 6;
469pub const DRM_MODE_CONNECTOR_LVDS: u32 = 7;
470pub const DRM_MODE_CONNECTOR_Component: u32 = 8;
471pub const DRM_MODE_CONNECTOR_9PinDIN: u32 = 9;
472pub const DRM_MODE_CONNECTOR_DisplayPort: u32 = 10;
473pub const DRM_MODE_CONNECTOR_HDMIA: u32 = 11;
474pub const DRM_MODE_CONNECTOR_HDMIB: u32 = 12;
475pub const DRM_MODE_CONNECTOR_TV: u32 = 13;
476pub const DRM_MODE_CONNECTOR_eDP: u32 = 14;
477pub const DRM_MODE_CONNECTOR_VIRTUAL: u32 = 15;
478pub const DRM_MODE_CONNECTOR_DSI: u32 = 16;
479pub const DRM_MODE_CONNECTOR_DPI: u32 = 17;
480pub const DRM_MODE_CONNECTOR_WRITEBACK: u32 = 18;
481pub const DRM_MODE_CONNECTOR_SPI: u32 = 19;
482pub const DRM_MODE_CONNECTOR_USB: u32 = 20;
483pub const DRM_MODE_PROP_PENDING: u32 = 1;
484pub const DRM_MODE_PROP_RANGE: u32 = 2;
485pub const DRM_MODE_PROP_IMMUTABLE: u32 = 4;
486pub const DRM_MODE_PROP_ENUM: u32 = 8;
487pub const DRM_MODE_PROP_BLOB: u32 = 16;
488pub const DRM_MODE_PROP_BITMASK: u32 = 32;
489pub const DRM_MODE_PROP_LEGACY_TYPE: u32 = 58;
490pub const DRM_MODE_PROP_EXTENDED_TYPE: u32 = 65472;
491pub const DRM_MODE_PROP_ATOMIC: u32 = 2147483648;
492pub const DRM_MODE_OBJECT_CRTC: u32 = 3435973836;
493pub const DRM_MODE_OBJECT_CONNECTOR: u32 = 3233857728;
494pub const DRM_MODE_OBJECT_ENCODER: u32 = 3772834016;
495pub const DRM_MODE_OBJECT_MODE: u32 = 3739147998;
496pub const DRM_MODE_OBJECT_PROPERTY: u32 = 2964369584;
497pub const DRM_MODE_OBJECT_FB: u32 = 4227595259;
498pub const DRM_MODE_OBJECT_BLOB: u32 = 3149642683;
499pub const DRM_MODE_OBJECT_PLANE: u32 = 4008636142;
500pub const DRM_MODE_OBJECT_ANY: u32 = 0;
501pub const DRM_MODE_FB_INTERLACED: u32 = 1;
502pub const DRM_MODE_FB_MODIFIERS: u32 = 2;
503pub const DRM_MODE_FB_DIRTY_ANNOTATE_COPY: u32 = 1;
504pub const DRM_MODE_FB_DIRTY_ANNOTATE_FILL: u32 = 2;
505pub const DRM_MODE_FB_DIRTY_FLAGS: u32 = 3;
506pub const DRM_MODE_FB_DIRTY_MAX_CLIPS: u32 = 256;
507pub const DRM_MODE_CURSOR_BO: u32 = 1;
508pub const DRM_MODE_CURSOR_MOVE: u32 = 2;
509pub const DRM_MODE_CURSOR_FLAGS: u32 = 3;
510pub const DRM_MODE_PAGE_FLIP_EVENT: u32 = 1;
511pub const DRM_MODE_PAGE_FLIP_ASYNC: u32 = 2;
512pub const DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE: u32 = 4;
513pub const DRM_MODE_PAGE_FLIP_TARGET_RELATIVE: u32 = 8;
514pub const DRM_MODE_PAGE_FLIP_TARGET: u32 = 12;
515pub const DRM_MODE_PAGE_FLIP_FLAGS: u32 = 15;
516pub const DRM_MODE_ATOMIC_TEST_ONLY: u32 = 256;
517pub const DRM_MODE_ATOMIC_NONBLOCK: u32 = 512;
518pub const DRM_MODE_ATOMIC_ALLOW_MODESET: u32 = 1024;
519pub const DRM_MODE_ATOMIC_FLAGS: u32 = 1795;
520pub const FORMAT_BLOB_CURRENT: u32 = 1;
521pub const DRM_IOCTL_BASE: u8 = 100u8;
522pub const DRM_COMMAND_BASE: u32 = 64;
523pub const DRM_COMMAND_END: u32 = 160;
524pub const DRM_EVENT_VBLANK: u32 = 1;
525pub const DRM_EVENT_FLIP_COMPLETE: u32 = 2;
526pub const DRM_EVENT_CRTC_SEQUENCE: u32 = 3;
527pub const DRM_MAX_MINOR: u32 = 64;
528pub const DRM_IOC_VOID: u32 = 0;
529pub const DRM_IOC_READ: u32 = 2;
530pub const DRM_IOC_WRITE: u32 = 1;
531pub const DRM_IOC_READWRITE: u32 = 3;
532pub const DRM_DEV_UID: u32 = 0;
533pub const DRM_DEV_GID: u32 = 0;
534pub const DRM_DIR_NAME: &[u8; 9] = b"/dev/dri\0";
535pub const DRM_PRIMARY_MINOR_NAME: &[u8; 5] = b"card\0";
536pub const DRM_CONTROL_MINOR_NAME: &[u8; 9] = b"controlD\0";
537pub const DRM_RENDER_MINOR_NAME: &[u8; 8] = b"renderD\0";
538pub const DRM_PROC_NAME: &[u8; 11] = b"/proc/dri/\0";
539pub const DRM_DEV_NAME: &[u8; 10] = b"%s/card%d\0";
540pub const DRM_CONTROL_DEV_NAME: &[u8; 14] = b"%s/controlD%d\0";
541pub const DRM_RENDER_DEV_NAME: &[u8; 13] = b"%s/renderD%d\0";
542pub const DRM_ERR_NO_DEVICE: i32 = -1001;
543pub const DRM_ERR_NO_ACCESS: i32 = -1002;
544pub const DRM_ERR_NOT_ROOT: i32 = -1003;
545pub const DRM_ERR_INVALID: i32 = -1004;
546pub const DRM_ERR_NO_FD: i32 = -1005;
547pub const DRM_AGP_NO_HANDLE: u32 = 0;
548pub const DRM_VBLANK_HIGH_CRTC_SHIFT: u32 = 1;
549pub const DRM_LOCK_HELD: u32 = 2147483648;
550pub const DRM_LOCK_CONT: u32 = 1073741824;
551pub const DRM_NODE_PRIMARY: u32 = 0;
552pub const DRM_NODE_CONTROL: u32 = 1;
553pub const DRM_NODE_RENDER: u32 = 2;
554pub const DRM_NODE_MAX: u32 = 3;
555pub const DRM_EVENT_CONTEXT_VERSION: u32 = 4;
556pub const DRM_BUS_PCI: u32 = 0;
557pub const DRM_BUS_USB: u32 = 1;
558pub const DRM_BUS_PLATFORM: u32 = 2;
559pub const DRM_BUS_HOST1X: u32 = 3;
560pub const DRM_PLATFORM_DEVICE_NAME_LEN: u32 = 512;
561pub const DRM_HOST1X_DEVICE_NAME_LEN: u32 = 512;
562pub const DRM_DEVICE_GET_PCI_REVISION: u32 = 1;
563pub const __bool_true_false_are_defined: u32 = 1;
564pub const true_: u32 = 1;
565pub const false_: u32 = 0;
566pub const DRM_MODE_FEATURE_KMS: u32 = 1;
567pub const DRM_MODE_FEATURE_DIRTYFB: u32 = 1;
568pub const DRM_PLANE_TYPE_OVERLAY: u32 = 0;
569pub const DRM_PLANE_TYPE_PRIMARY: u32 = 1;
570pub const DRM_PLANE_TYPE_CURSOR: u32 = 2;
571pub const AMDGPU_CS_MAX_IBS_PER_SUBMIT: u32 = 4;
572pub const AMDGPU_TIMEOUT_INFINITE: i32 = -1;
573pub const AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE: u32 = 1;
574pub const AMDGPU_VA_RANGE_32_BIT: u32 = 1;
575pub const AMDGPU_VA_RANGE_HIGH: u32 = 2;
576pub const AMDGPU_VA_RANGE_REPLAYABLE: u32 = 4;
577pub const DRM_AMDGPU_GEM_CREATE: u32 = 0;
578pub const DRM_AMDGPU_GEM_MMAP: u32 = 1;
579pub const DRM_AMDGPU_CTX: u32 = 2;
580pub const DRM_AMDGPU_BO_LIST: u32 = 3;
581pub const DRM_AMDGPU_CS: u32 = 4;
582pub const DRM_AMDGPU_INFO: u32 = 5;
583pub const DRM_AMDGPU_GEM_METADATA: u32 = 6;
584pub const DRM_AMDGPU_GEM_WAIT_IDLE: u32 = 7;
585pub const DRM_AMDGPU_GEM_VA: u32 = 8;
586pub const DRM_AMDGPU_WAIT_CS: u32 = 9;
587pub const DRM_AMDGPU_GEM_OP: u32 = 16;
588pub const DRM_AMDGPU_GEM_USERPTR: u32 = 17;
589pub const DRM_AMDGPU_WAIT_FENCES: u32 = 18;
590pub const DRM_AMDGPU_VM: u32 = 19;
591pub const DRM_AMDGPU_FENCE_TO_HANDLE: u32 = 20;
592pub const DRM_AMDGPU_SCHED: u32 = 21;
593pub const AMDGPU_GEM_DOMAIN_CPU: u32 = 1;
594pub const AMDGPU_GEM_DOMAIN_GTT: u32 = 2;
595pub const AMDGPU_GEM_DOMAIN_VRAM: u32 = 4;
596pub const AMDGPU_GEM_DOMAIN_GDS: u32 = 8;
597pub const AMDGPU_GEM_DOMAIN_GWS: u32 = 16;
598pub const AMDGPU_GEM_DOMAIN_OA: u32 = 32;
599pub const AMDGPU_GEM_DOMAIN_DOORBELL: u32 = 64;
600pub const AMDGPU_GEM_DOMAIN_MASK: u32 = 127;
601pub const AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED: u32 = 1;
602pub const AMDGPU_GEM_CREATE_NO_CPU_ACCESS: u32 = 2;
603pub const AMDGPU_GEM_CREATE_CPU_GTT_USWC: u32 = 4;
604pub const AMDGPU_GEM_CREATE_VRAM_CLEARED: u32 = 8;
605pub const AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS: u32 = 32;
606pub const AMDGPU_GEM_CREATE_VM_ALWAYS_VALID: u32 = 64;
607pub const AMDGPU_GEM_CREATE_EXPLICIT_SYNC: u32 = 128;
608pub const AMDGPU_GEM_CREATE_CP_MQD_GFX9: u32 = 256;
609pub const AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE: u32 = 512;
610pub const AMDGPU_GEM_CREATE_ENCRYPTED: u32 = 1024;
611pub const AMDGPU_GEM_CREATE_PREEMPTIBLE: u32 = 2048;
612pub const AMDGPU_GEM_CREATE_DISCARDABLE: u32 = 4096;
613pub const AMDGPU_GEM_CREATE_COHERENT: u32 = 8192;
614pub const AMDGPU_GEM_CREATE_UNCACHED: u32 = 16384;
615pub const AMDGPU_GEM_CREATE_EXT_COHERENT: u32 = 32768;
616pub const AMDGPU_BO_LIST_OP_CREATE: u32 = 0;
617pub const AMDGPU_BO_LIST_OP_DESTROY: u32 = 1;
618pub const AMDGPU_BO_LIST_OP_UPDATE: u32 = 2;
619pub const AMDGPU_CTX_OP_ALLOC_CTX: u32 = 1;
620pub const AMDGPU_CTX_OP_FREE_CTX: u32 = 2;
621pub const AMDGPU_CTX_OP_QUERY_STATE: u32 = 3;
622pub const AMDGPU_CTX_OP_QUERY_STATE2: u32 = 4;
623pub const AMDGPU_CTX_OP_GET_STABLE_PSTATE: u32 = 5;
624pub const AMDGPU_CTX_OP_SET_STABLE_PSTATE: u32 = 6;
625pub const AMDGPU_CTX_NO_RESET: u32 = 0;
626pub const AMDGPU_CTX_GUILTY_RESET: u32 = 1;
627pub const AMDGPU_CTX_INNOCENT_RESET: u32 = 2;
628pub const AMDGPU_CTX_UNKNOWN_RESET: u32 = 3;
629pub const AMDGPU_CTX_QUERY2_FLAGS_RESET: u32 = 1;
630pub const AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST: u32 = 2;
631pub const AMDGPU_CTX_QUERY2_FLAGS_GUILTY: u32 = 4;
632pub const AMDGPU_CTX_QUERY2_FLAGS_RAS_CE: u32 = 8;
633pub const AMDGPU_CTX_QUERY2_FLAGS_RAS_UE: u32 = 16;
634pub const AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS: u32 = 32;
635pub const AMDGPU_CTX_PRIORITY_UNSET: i32 = -2048;
636pub const AMDGPU_CTX_PRIORITY_VERY_LOW: i32 = -1023;
637pub const AMDGPU_CTX_PRIORITY_LOW: i32 = -512;
638pub const AMDGPU_CTX_PRIORITY_NORMAL: u32 = 0;
639pub const AMDGPU_CTX_PRIORITY_HIGH: u32 = 512;
640pub const AMDGPU_CTX_PRIORITY_VERY_HIGH: u32 = 1023;
641pub const AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK: u32 = 15;
642pub const AMDGPU_CTX_STABLE_PSTATE_NONE: u32 = 0;
643pub const AMDGPU_CTX_STABLE_PSTATE_STANDARD: u32 = 1;
644pub const AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: u32 = 2;
645pub const AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: u32 = 3;
646pub const AMDGPU_CTX_STABLE_PSTATE_PEAK: u32 = 4;
647pub const AMDGPU_VM_OP_RESERVE_VMID: u32 = 1;
648pub const AMDGPU_VM_OP_UNRESERVE_VMID: u32 = 2;
649pub const AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: u32 = 1;
650pub const AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE: u32 = 2;
651pub const AMDGPU_GEM_USERPTR_READONLY: u32 = 1;
652pub const AMDGPU_GEM_USERPTR_ANONONLY: u32 = 2;
653pub const AMDGPU_GEM_USERPTR_VALIDATE: u32 = 4;
654pub const AMDGPU_GEM_USERPTR_REGISTER: u32 = 8;
655pub const AMDGPU_TILING_ARRAY_MODE_SHIFT: u32 = 0;
656pub const AMDGPU_TILING_ARRAY_MODE_MASK: u32 = 15;
657pub const AMDGPU_TILING_PIPE_CONFIG_SHIFT: u32 = 4;
658pub const AMDGPU_TILING_PIPE_CONFIG_MASK: u32 = 31;
659pub const AMDGPU_TILING_TILE_SPLIT_SHIFT: u32 = 9;
660pub const AMDGPU_TILING_TILE_SPLIT_MASK: u32 = 7;
661pub const AMDGPU_TILING_MICRO_TILE_MODE_SHIFT: u32 = 12;
662pub const AMDGPU_TILING_MICRO_TILE_MODE_MASK: u32 = 7;
663pub const AMDGPU_TILING_BANK_WIDTH_SHIFT: u32 = 15;
664pub const AMDGPU_TILING_BANK_WIDTH_MASK: u32 = 3;
665pub const AMDGPU_TILING_BANK_HEIGHT_SHIFT: u32 = 17;
666pub const AMDGPU_TILING_BANK_HEIGHT_MASK: u32 = 3;
667pub const AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT: u32 = 19;
668pub const AMDGPU_TILING_MACRO_TILE_ASPECT_MASK: u32 = 3;
669pub const AMDGPU_TILING_NUM_BANKS_SHIFT: u32 = 21;
670pub const AMDGPU_TILING_NUM_BANKS_MASK: u32 = 3;
671pub const AMDGPU_TILING_SWIZZLE_MODE_SHIFT: u32 = 0;
672pub const AMDGPU_TILING_SWIZZLE_MODE_MASK: u32 = 31;
673pub const AMDGPU_TILING_DCC_OFFSET_256B_SHIFT: u32 = 5;
674pub const AMDGPU_TILING_DCC_OFFSET_256B_MASK: u32 = 16777215;
675pub const AMDGPU_TILING_DCC_PITCH_MAX_SHIFT: u32 = 29;
676pub const AMDGPU_TILING_DCC_PITCH_MAX_MASK: u32 = 16383;
677pub const AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT: u32 = 43;
678pub const AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK: u32 = 1;
679pub const AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT: u32 = 44;
680pub const AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK: u32 = 1;
681pub const AMDGPU_TILING_SCANOUT_SHIFT: u32 = 63;
682pub const AMDGPU_TILING_SCANOUT_MASK: u32 = 1;
683pub const AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT: u32 = 0;
684pub const AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK: u32 = 7;
685pub const AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT: u32 = 3;
686pub const AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK: u32 = 3;
687pub const AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT: u32 = 5;
688pub const AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK: u32 = 7;
689pub const AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT: u32 = 8;
690pub const AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK: u32 = 63;
691pub const AMDGPU_GEM_METADATA_OP_SET_METADATA: u32 = 1;
692pub const AMDGPU_GEM_METADATA_OP_GET_METADATA: u32 = 2;
693pub const AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: u32 = 0;
694pub const AMDGPU_GEM_OP_SET_PLACEMENT: u32 = 1;
695pub const AMDGPU_VA_OP_MAP: u32 = 1;
696pub const AMDGPU_VA_OP_UNMAP: u32 = 2;
697pub const AMDGPU_VA_OP_CLEAR: u32 = 3;
698pub const AMDGPU_VA_OP_REPLACE: u32 = 4;
699pub const AMDGPU_VM_DELAY_UPDATE: u32 = 1;
700pub const AMDGPU_VM_PAGE_READABLE: u32 = 2;
701pub const AMDGPU_VM_PAGE_WRITEABLE: u32 = 4;
702pub const AMDGPU_VM_PAGE_EXECUTABLE: u32 = 8;
703pub const AMDGPU_VM_PAGE_PRT: u32 = 16;
704pub const AMDGPU_VM_MTYPE_MASK: u32 = 480;
705pub const AMDGPU_VM_MTYPE_DEFAULT: u32 = 0;
706pub const AMDGPU_VM_MTYPE_NC: u32 = 32;
707pub const AMDGPU_VM_MTYPE_WC: u32 = 64;
708pub const AMDGPU_VM_MTYPE_CC: u32 = 96;
709pub const AMDGPU_VM_MTYPE_UC: u32 = 128;
710pub const AMDGPU_VM_MTYPE_RW: u32 = 160;
711pub const AMDGPU_VM_PAGE_NOALLOC: u32 = 512;
712pub const AMDGPU_HW_IP_GFX: u32 = 0;
713pub const AMDGPU_HW_IP_COMPUTE: u32 = 1;
714pub const AMDGPU_HW_IP_DMA: u32 = 2;
715pub const AMDGPU_HW_IP_UVD: u32 = 3;
716pub const AMDGPU_HW_IP_VCE: u32 = 4;
717pub const AMDGPU_HW_IP_UVD_ENC: u32 = 5;
718pub const AMDGPU_HW_IP_VCN_DEC: u32 = 6;
719pub const AMDGPU_HW_IP_VCN_ENC: u32 = 7;
720pub const AMDGPU_HW_IP_VCN_JPEG: u32 = 8;
721pub const AMDGPU_HW_IP_VPE: u32 = 9;
722pub const AMDGPU_HW_IP_NUM: u32 = 10;
723pub const AMDGPU_HW_IP_INSTANCE_MAX_COUNT: u32 = 1;
724pub const AMDGPU_CHUNK_ID_IB: u32 = 1;
725pub const AMDGPU_CHUNK_ID_FENCE: u32 = 2;
726pub const AMDGPU_CHUNK_ID_DEPENDENCIES: u32 = 3;
727pub const AMDGPU_CHUNK_ID_SYNCOBJ_IN: u32 = 4;
728pub const AMDGPU_CHUNK_ID_SYNCOBJ_OUT: u32 = 5;
729pub const AMDGPU_CHUNK_ID_BO_HANDLES: u32 = 6;
730pub const AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: u32 = 7;
731pub const AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: u32 = 8;
732pub const AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: u32 = 9;
733pub const AMDGPU_CHUNK_ID_CP_GFX_SHADOW: u32 = 10;
734pub const AMDGPU_IB_FLAG_CE: u32 = 1;
735pub const AMDGPU_IB_FLAG_PREAMBLE: u32 = 2;
736pub const AMDGPU_IB_FLAG_PREEMPT: u32 = 4;
737pub const AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE: u32 = 8;
738pub const AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID: u32 = 16;
739pub const AMDGPU_IB_FLAGS_SECURE: u32 = 32;
740pub const AMDGPU_IB_FLAG_EMIT_MEM_SYNC: u32 = 64;
741pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ: u32 = 0;
742pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD: u32 = 1;
743pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD: u32 = 2;
744pub const AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW: u32 = 1;
745pub const AMDGPU_IDS_FLAGS_FUSION: u32 = 1;
746pub const AMDGPU_IDS_FLAGS_PREEMPTION: u32 = 2;
747pub const AMDGPU_IDS_FLAGS_TMZ: u32 = 4;
748pub const AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: u32 = 8;
749pub const AMDGPU_IDS_FLAGS_MODE_MASK: u32 = 768;
750pub const AMDGPU_IDS_FLAGS_MODE_SHIFT: u32 = 8;
751pub const AMDGPU_IDS_FLAGS_MODE_PF: u32 = 0;
752pub const AMDGPU_IDS_FLAGS_MODE_VF: u32 = 1;
753pub const AMDGPU_IDS_FLAGS_MODE_PT: u32 = 2;
754pub const AMDGPU_INFO_ACCEL_WORKING: u32 = 0;
755pub const AMDGPU_INFO_CRTC_FROM_ID: u32 = 1;
756pub const AMDGPU_INFO_HW_IP_INFO: u32 = 2;
757pub const AMDGPU_INFO_HW_IP_COUNT: u32 = 3;
758pub const AMDGPU_INFO_TIMESTAMP: u32 = 5;
759pub const AMDGPU_INFO_FW_VERSION: u32 = 14;
760pub const AMDGPU_INFO_FW_VCE: u32 = 1;
761pub const AMDGPU_INFO_FW_UVD: u32 = 2;
762pub const AMDGPU_INFO_FW_GMC: u32 = 3;
763pub const AMDGPU_INFO_FW_GFX_ME: u32 = 4;
764pub const AMDGPU_INFO_FW_GFX_PFP: u32 = 5;
765pub const AMDGPU_INFO_FW_GFX_CE: u32 = 6;
766pub const AMDGPU_INFO_FW_GFX_RLC: u32 = 7;
767pub const AMDGPU_INFO_FW_GFX_MEC: u32 = 8;
768pub const AMDGPU_INFO_FW_SMC: u32 = 10;
769pub const AMDGPU_INFO_FW_SDMA: u32 = 11;
770pub const AMDGPU_INFO_FW_SOS: u32 = 12;
771pub const AMDGPU_INFO_FW_ASD: u32 = 13;
772pub const AMDGPU_INFO_FW_VCN: u32 = 14;
773pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: u32 = 15;
774pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: u32 = 16;
775pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: u32 = 17;
776pub const AMDGPU_INFO_FW_DMCU: u32 = 18;
777pub const AMDGPU_INFO_FW_TA: u32 = 19;
778pub const AMDGPU_INFO_FW_DMCUB: u32 = 20;
779pub const AMDGPU_INFO_FW_TOC: u32 = 21;
780pub const AMDGPU_INFO_FW_CAP: u32 = 22;
781pub const AMDGPU_INFO_FW_GFX_RLCP: u32 = 23;
782pub const AMDGPU_INFO_FW_GFX_RLCV: u32 = 24;
783pub const AMDGPU_INFO_FW_MES_KIQ: u32 = 25;
784pub const AMDGPU_INFO_FW_MES: u32 = 26;
785pub const AMDGPU_INFO_FW_IMU: u32 = 27;
786pub const AMDGPU_INFO_FW_VPE: u32 = 28;
787pub const AMDGPU_INFO_NUM_BYTES_MOVED: u32 = 15;
788pub const AMDGPU_INFO_VRAM_USAGE: u32 = 16;
789pub const AMDGPU_INFO_GTT_USAGE: u32 = 17;
790pub const AMDGPU_INFO_GDS_CONFIG: u32 = 19;
791pub const AMDGPU_INFO_VRAM_GTT: u32 = 20;
792pub const AMDGPU_INFO_READ_MMR_REG: u32 = 21;
793pub const AMDGPU_INFO_DEV_INFO: u32 = 22;
794pub const AMDGPU_INFO_VIS_VRAM_USAGE: u32 = 23;
795pub const AMDGPU_INFO_NUM_EVICTIONS: u32 = 24;
796pub const AMDGPU_INFO_MEMORY: u32 = 25;
797pub const AMDGPU_INFO_VCE_CLOCK_TABLE: u32 = 26;
798pub const AMDGPU_INFO_VBIOS: u32 = 27;
799pub const AMDGPU_INFO_VBIOS_SIZE: u32 = 1;
800pub const AMDGPU_INFO_VBIOS_IMAGE: u32 = 2;
801pub const AMDGPU_INFO_VBIOS_INFO: u32 = 3;
802pub const AMDGPU_INFO_NUM_HANDLES: u32 = 28;
803pub const AMDGPU_INFO_SENSOR: u32 = 29;
804pub const AMDGPU_INFO_SENSOR_GFX_SCLK: u32 = 1;
805pub const AMDGPU_INFO_SENSOR_GFX_MCLK: u32 = 2;
806pub const AMDGPU_INFO_SENSOR_GPU_TEMP: u32 = 3;
807pub const AMDGPU_INFO_SENSOR_GPU_LOAD: u32 = 4;
808pub const AMDGPU_INFO_SENSOR_GPU_AVG_POWER: u32 = 5;
809pub const AMDGPU_INFO_SENSOR_VDDNB: u32 = 6;
810pub const AMDGPU_INFO_SENSOR_VDDGFX: u32 = 7;
811pub const AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: u32 = 8;
812pub const AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: u32 = 9;
813pub const AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: u32 = 10;
814pub const AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: u32 = 11;
815pub const AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: u32 = 12;
816pub const AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: u32 = 30;
817pub const AMDGPU_INFO_VRAM_LOST_COUNTER: u32 = 31;
818pub const AMDGPU_INFO_RAS_ENABLED_FEATURES: u32 = 32;
819pub const AMDGPU_INFO_RAS_ENABLED_UMC: u32 = 1;
820pub const AMDGPU_INFO_RAS_ENABLED_SDMA: u32 = 2;
821pub const AMDGPU_INFO_RAS_ENABLED_GFX: u32 = 4;
822pub const AMDGPU_INFO_RAS_ENABLED_MMHUB: u32 = 8;
823pub const AMDGPU_INFO_RAS_ENABLED_ATHUB: u32 = 16;
824pub const AMDGPU_INFO_RAS_ENABLED_PCIE: u32 = 32;
825pub const AMDGPU_INFO_RAS_ENABLED_HDP: u32 = 64;
826pub const AMDGPU_INFO_RAS_ENABLED_XGMI: u32 = 128;
827pub const AMDGPU_INFO_RAS_ENABLED_DF: u32 = 256;
828pub const AMDGPU_INFO_RAS_ENABLED_SMN: u32 = 512;
829pub const AMDGPU_INFO_RAS_ENABLED_SEM: u32 = 1024;
830pub const AMDGPU_INFO_RAS_ENABLED_MP0: u32 = 2048;
831pub const AMDGPU_INFO_RAS_ENABLED_MP1: u32 = 4096;
832pub const AMDGPU_INFO_RAS_ENABLED_FUSE: u32 = 8192;
833pub const AMDGPU_INFO_VIDEO_CAPS: u32 = 33;
834pub const AMDGPU_INFO_VIDEO_CAPS_DECODE: u32 = 0;
835pub const AMDGPU_INFO_VIDEO_CAPS_ENCODE: u32 = 1;
836pub const AMDGPU_INFO_MAX_IBS: u32 = 34;
837pub const AMDGPU_INFO_GPUVM_FAULT: u32 = 35;
838pub const AMDGPU_INFO_MMR_SE_INDEX_SHIFT: u32 = 0;
839pub const AMDGPU_INFO_MMR_SE_INDEX_MASK: u32 = 255;
840pub const AMDGPU_INFO_MMR_SH_INDEX_SHIFT: u32 = 8;
841pub const AMDGPU_INFO_MMR_SH_INDEX_MASK: u32 = 255;
842pub const AMDGPU_VRAM_TYPE_UNKNOWN: u32 = 0;
843pub const AMDGPU_VRAM_TYPE_GDDR1: u32 = 1;
844pub const AMDGPU_VRAM_TYPE_DDR2: u32 = 2;
845pub const AMDGPU_VRAM_TYPE_GDDR3: u32 = 3;
846pub const AMDGPU_VRAM_TYPE_GDDR4: u32 = 4;
847pub const AMDGPU_VRAM_TYPE_GDDR5: u32 = 5;
848pub const AMDGPU_VRAM_TYPE_HBM: u32 = 6;
849pub const AMDGPU_VRAM_TYPE_DDR3: u32 = 7;
850pub const AMDGPU_VRAM_TYPE_DDR4: u32 = 8;
851pub const AMDGPU_VRAM_TYPE_GDDR6: u32 = 9;
852pub const AMDGPU_VRAM_TYPE_DDR5: u32 = 10;
853pub const AMDGPU_VRAM_TYPE_LPDDR4: u32 = 11;
854pub const AMDGPU_VRAM_TYPE_LPDDR5: u32 = 12;
855pub const AMDGPU_VCE_CLOCK_TABLE_ENTRIES: u32 = 6;
856pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: u32 = 0;
857pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: u32 = 1;
858pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: u32 = 2;
859pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: u32 = 3;
860pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: u32 = 4;
861pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: u32 = 5;
862pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: u32 = 6;
863pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: u32 = 7;
864pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT: u32 = 8;
865pub const AMDGPU_VMHUB_TYPE_MASK: u32 = 255;
866pub const AMDGPU_VMHUB_TYPE_SHIFT: u32 = 0;
867pub const AMDGPU_VMHUB_TYPE_GFX: u32 = 0;
868pub const AMDGPU_VMHUB_TYPE_MM0: u32 = 1;
869pub const AMDGPU_VMHUB_TYPE_MM1: u32 = 2;
870pub const AMDGPU_VMHUB_IDX_MASK: u32 = 65280;
871pub const AMDGPU_VMHUB_IDX_SHIFT: u32 = 8;
872pub const AMDGPU_FAMILY_UNKNOWN: u32 = 0;
873pub const AMDGPU_FAMILY_SI: u32 = 110;
874pub const AMDGPU_FAMILY_CI: u32 = 120;
875pub const AMDGPU_FAMILY_KV: u32 = 125;
876pub const AMDGPU_FAMILY_VI: u32 = 130;
877pub const AMDGPU_FAMILY_CZ: u32 = 135;
878pub const AMDGPU_FAMILY_AI: u32 = 141;
879pub const AMDGPU_FAMILY_RV: u32 = 142;
880pub const AMDGPU_FAMILY_NV: u32 = 143;
881pub const AMDGPU_FAMILY_VGH: u32 = 144;
882pub const AMDGPU_FAMILY_GC_11_0_0: u32 = 145;
883pub const AMDGPU_FAMILY_YC: u32 = 146;
884pub const AMDGPU_FAMILY_GC_11_0_1: u32 = 148;
885pub const AMDGPU_FAMILY_GC_10_3_6: u32 = 149;
886pub const AMDGPU_FAMILY_GC_10_3_7: u32 = 151;
887pub const AMDGPU_FAMILY_GC_11_5_0: u32 = 150;
888pub const AMDGPU_FAMILY_GC_12_0_0: u32 = 152;
889pub const BIOS_ATOM_PREFIX: &[u8; 9] = b"ATOMBIOS\0";
890pub const BIOS_VERSION_PREFIX: &[u8; 15] = b"ATOMBIOSBK-AMD\0";
891pub const BIOS_STRING_LENGTH: u32 = 43;
892pub const NUM_HBM_INSTANCES: u32 = 4;
893pub const NUM_XGMI_LINKS: u32 = 8;
894pub const MAX_GFX_CLKS: u32 = 8;
895pub const MAX_CLKS: u32 = 4;
896pub const NUM_VCN: u32 = 4;
897pub const NUM_JPEG_ENG: u32 = 32;
898pub type __gnuc_va_list = __builtin_va_list;
899pub type va_list = __builtin_va_list;
900pub type __u_char = ::core::ffi::c_uchar;
901pub type __u_short = ::core::ffi::c_ushort;
902pub type __u_int = ::core::ffi::c_uint;
903pub type __u_long = ::core::ffi::c_ulong;
904pub type __int8_t = ::core::ffi::c_schar;
905pub type __uint8_t = ::core::ffi::c_uchar;
906pub type __int16_t = ::core::ffi::c_short;
907pub type __uint16_t = ::core::ffi::c_ushort;
908pub type __int32_t = ::core::ffi::c_int;
909pub type __uint32_t = ::core::ffi::c_uint;
910pub type __int64_t = ::core::ffi::c_long;
911pub type __uint64_t = ::core::ffi::c_ulong;
912pub type __int_least8_t = __int8_t;
913pub type __uint_least8_t = __uint8_t;
914pub type __int_least16_t = __int16_t;
915pub type __uint_least16_t = __uint16_t;
916pub type __int_least32_t = __int32_t;
917pub type __uint_least32_t = __uint32_t;
918pub type __int_least64_t = __int64_t;
919pub type __uint_least64_t = __uint64_t;
920pub type __quad_t = ::core::ffi::c_long;
921pub type __u_quad_t = ::core::ffi::c_ulong;
922pub type __intmax_t = ::core::ffi::c_long;
923pub type __uintmax_t = ::core::ffi::c_ulong;
924pub type __dev_t = ::core::ffi::c_ulong;
925pub type __uid_t = ::core::ffi::c_uint;
926pub type __gid_t = ::core::ffi::c_uint;
927pub type __ino_t = ::core::ffi::c_ulong;
928pub type __ino64_t = ::core::ffi::c_ulong;
929pub type __mode_t = ::core::ffi::c_uint;
930pub type __nlink_t = ::core::ffi::c_ulong;
931pub type __off_t = ::core::ffi::c_long;
932pub type __off64_t = ::core::ffi::c_long;
933pub type __pid_t = ::core::ffi::c_int;
934#[repr(C)]
935#[derive(Debug, Copy, Clone)]
936pub struct __fsid_t {
937 pub __val: [::core::ffi::c_int; 2usize],
938}
939pub type __clock_t = ::core::ffi::c_long;
940pub type __rlim_t = ::core::ffi::c_ulong;
941pub type __rlim64_t = ::core::ffi::c_ulong;
942pub type __id_t = ::core::ffi::c_uint;
943pub type __time_t = ::core::ffi::c_long;
944pub type __useconds_t = ::core::ffi::c_uint;
945pub type __suseconds_t = ::core::ffi::c_long;
946pub type __suseconds64_t = ::core::ffi::c_long;
947pub type __daddr_t = ::core::ffi::c_int;
948pub type __key_t = ::core::ffi::c_int;
949pub type __clockid_t = ::core::ffi::c_int;
950pub type __timer_t = *mut ::core::ffi::c_void;
951pub type __blksize_t = ::core::ffi::c_long;
952pub type __blkcnt_t = ::core::ffi::c_long;
953pub type __blkcnt64_t = ::core::ffi::c_long;
954pub type __fsblkcnt_t = ::core::ffi::c_ulong;
955pub type __fsblkcnt64_t = ::core::ffi::c_ulong;
956pub type __fsfilcnt_t = ::core::ffi::c_ulong;
957pub type __fsfilcnt64_t = ::core::ffi::c_ulong;
958pub type __fsword_t = ::core::ffi::c_long;
959pub type __ssize_t = ::core::ffi::c_long;
960pub type __syscall_slong_t = ::core::ffi::c_long;
961pub type __syscall_ulong_t = ::core::ffi::c_ulong;
962pub type __loff_t = __off64_t;
963pub type __caddr_t = *mut ::core::ffi::c_char;
964pub type __intptr_t = ::core::ffi::c_long;
965pub type __socklen_t = ::core::ffi::c_uint;
966pub type __sig_atomic_t = ::core::ffi::c_int;
967pub type u_char = __u_char;
968pub type u_short = __u_short;
969pub type u_int = __u_int;
970pub type u_long = __u_long;
971pub type quad_t = __quad_t;
972pub type u_quad_t = __u_quad_t;
973pub type fsid_t = __fsid_t;
974pub type loff_t = __loff_t;
975pub type ino_t = __ino_t;
976pub type dev_t = __dev_t;
977pub type gid_t = __gid_t;
978pub type mode_t = __mode_t;
979pub type nlink_t = __nlink_t;
980pub type uid_t = __uid_t;
981pub type off_t = __off_t;
982pub type pid_t = __pid_t;
983pub type id_t = __id_t;
984pub type daddr_t = __daddr_t;
985pub type caddr_t = __caddr_t;
986pub type key_t = __key_t;
987pub type clock_t = __clock_t;
988pub type clockid_t = __clockid_t;
989pub type time_t = __time_t;
990pub type timer_t = __timer_t;
991pub type ulong = ::core::ffi::c_ulong;
992pub type ushort = ::core::ffi::c_ushort;
993pub type uint = ::core::ffi::c_uint;
994pub type u_int8_t = __uint8_t;
995pub type u_int16_t = __uint16_t;
996pub type u_int32_t = __uint32_t;
997pub type u_int64_t = __uint64_t;
998pub type register_t = ::core::ffi::c_long;
999#[repr(C)]
1000#[derive(Debug, Copy, Clone)]
1001pub struct __sigset_t {
1002 pub __val: [::core::ffi::c_ulong; 16usize],
1003}
1004pub type sigset_t = __sigset_t;
1005#[repr(C)]
1006#[derive(Debug, Copy, Clone)]
1007pub struct timeval {
1008 pub tv_sec: __time_t,
1009 pub tv_usec: __suseconds_t,
1010}
1011#[repr(C)]
1012#[derive(Debug, Copy, Clone)]
1013pub struct timespec {
1014 pub tv_sec: __time_t,
1015 pub tv_nsec: __syscall_slong_t,
1016}
1017pub type suseconds_t = __suseconds_t;
1018pub type __fd_mask = ::core::ffi::c_long;
1019#[repr(C)]
1020#[derive(Debug, Copy, Clone)]
1021pub struct fd_set {
1022 pub __fds_bits: [__fd_mask; 16usize],
1023}
1024pub type fd_mask = __fd_mask;
1025unsafe extern "C" {
1026 pub fn select(
1027 __nfds: ::core::ffi::c_int,
1028 __readfds: *mut fd_set,
1029 __writefds: *mut fd_set,
1030 __exceptfds: *mut fd_set,
1031 __timeout: *mut timeval,
1032 ) -> ::core::ffi::c_int;
1033}
1034unsafe extern "C" {
1035 pub fn pselect(
1036 __nfds: ::core::ffi::c_int,
1037 __readfds: *mut fd_set,
1038 __writefds: *mut fd_set,
1039 __exceptfds: *mut fd_set,
1040 __timeout: *const timespec,
1041 __sigmask: *const __sigset_t,
1042 ) -> ::core::ffi::c_int;
1043}
1044pub type blksize_t = __blksize_t;
1045pub type blkcnt_t = __blkcnt_t;
1046pub type fsblkcnt_t = __fsblkcnt_t;
1047pub type fsfilcnt_t = __fsfilcnt_t;
1048#[repr(C)]
1049#[derive(Copy, Clone)]
1050pub union __atomic_wide_counter {
1051 pub __value64: ::core::ffi::c_ulonglong,
1052 pub __value32: __atomic_wide_counter__bindgen_ty_1,
1053}
1054#[repr(C)]
1055#[derive(Debug, Copy, Clone)]
1056pub struct __atomic_wide_counter__bindgen_ty_1 {
1057 pub __low: ::core::ffi::c_uint,
1058 pub __high: ::core::ffi::c_uint,
1059}
1060#[repr(C)]
1061#[derive(Debug, Copy, Clone)]
1062pub struct __pthread_internal_list {
1063 pub __prev: *mut __pthread_internal_list,
1064 pub __next: *mut __pthread_internal_list,
1065}
1066pub type __pthread_list_t = __pthread_internal_list;
1067#[repr(C)]
1068#[derive(Debug, Copy, Clone)]
1069pub struct __pthread_internal_slist {
1070 pub __next: *mut __pthread_internal_slist,
1071}
1072pub type __pthread_slist_t = __pthread_internal_slist;
1073#[repr(C)]
1074#[derive(Debug, Copy, Clone)]
1075pub struct __pthread_mutex_s {
1076 pub __lock: ::core::ffi::c_int,
1077 pub __count: ::core::ffi::c_uint,
1078 pub __owner: ::core::ffi::c_int,
1079 pub __nusers: ::core::ffi::c_uint,
1080 pub __kind: ::core::ffi::c_int,
1081 pub __spins: ::core::ffi::c_short,
1082 pub __elision: ::core::ffi::c_short,
1083 pub __list: __pthread_list_t,
1084}
1085#[repr(C)]
1086#[derive(Debug, Copy, Clone)]
1087pub struct __pthread_rwlock_arch_t {
1088 pub __readers: ::core::ffi::c_uint,
1089 pub __writers: ::core::ffi::c_uint,
1090 pub __wrphase_futex: ::core::ffi::c_uint,
1091 pub __writers_futex: ::core::ffi::c_uint,
1092 pub __pad3: ::core::ffi::c_uint,
1093 pub __pad4: ::core::ffi::c_uint,
1094 pub __cur_writer: ::core::ffi::c_int,
1095 pub __shared: ::core::ffi::c_int,
1096 pub __rwelision: ::core::ffi::c_schar,
1097 pub __pad1: [::core::ffi::c_uchar; 7usize],
1098 pub __pad2: ::core::ffi::c_ulong,
1099 pub __flags: ::core::ffi::c_uint,
1100}
1101#[repr(C)]
1102#[derive(Copy, Clone)]
1103pub struct __pthread_cond_s {
1104 pub __wseq: __atomic_wide_counter,
1105 pub __g1_start: __atomic_wide_counter,
1106 pub __g_size: [::core::ffi::c_uint; 2usize],
1107 pub __g1_orig_size: ::core::ffi::c_uint,
1108 pub __wrefs: ::core::ffi::c_uint,
1109 pub __g_signals: [::core::ffi::c_uint; 2usize],
1110 pub __unused_initialized_1: ::core::ffi::c_uint,
1111 pub __unused_initialized_2: ::core::ffi::c_uint,
1112}
1113pub type __tss_t = ::core::ffi::c_uint;
1114pub type __thrd_t = ::core::ffi::c_ulong;
1115#[repr(C)]
1116#[derive(Debug, Copy, Clone)]
1117pub struct __once_flag {
1118 pub __data: ::core::ffi::c_int,
1119}
1120pub type pthread_t = ::core::ffi::c_ulong;
1121#[repr(C)]
1122#[derive(Copy, Clone)]
1123pub union pthread_mutexattr_t {
1124 pub __size: [::core::ffi::c_char; 4usize],
1125 pub __align: ::core::ffi::c_int,
1126}
1127#[repr(C)]
1128#[derive(Copy, Clone)]
1129pub union pthread_condattr_t {
1130 pub __size: [::core::ffi::c_char; 4usize],
1131 pub __align: ::core::ffi::c_int,
1132}
1133pub type pthread_key_t = ::core::ffi::c_uint;
1134pub type pthread_once_t = ::core::ffi::c_int;
1135#[repr(C)]
1136#[derive(Copy, Clone)]
1137pub union pthread_attr_t {
1138 pub __size: [::core::ffi::c_char; 56usize],
1139 pub __align: ::core::ffi::c_long,
1140}
1141#[repr(C)]
1142#[derive(Copy, Clone)]
1143pub union pthread_mutex_t {
1144 pub __data: __pthread_mutex_s,
1145 pub __size: [::core::ffi::c_char; 40usize],
1146 pub __align: ::core::ffi::c_long,
1147}
1148#[repr(C)]
1149#[derive(Copy, Clone)]
1150pub union pthread_cond_t {
1151 pub __data: __pthread_cond_s,
1152 pub __size: [::core::ffi::c_char; 48usize],
1153 pub __align: ::core::ffi::c_longlong,
1154}
1155#[repr(C)]
1156#[derive(Copy, Clone)]
1157pub union pthread_rwlock_t {
1158 pub __data: __pthread_rwlock_arch_t,
1159 pub __size: [::core::ffi::c_char; 56usize],
1160 pub __align: ::core::ffi::c_long,
1161}
1162#[repr(C)]
1163#[derive(Copy, Clone)]
1164pub union pthread_rwlockattr_t {
1165 pub __size: [::core::ffi::c_char; 8usize],
1166 pub __align: ::core::ffi::c_long,
1167}
1168pub type pthread_spinlock_t = ::core::ffi::c_int;
1169#[repr(C)]
1170#[derive(Copy, Clone)]
1171pub union pthread_barrier_t {
1172 pub __size: [::core::ffi::c_char; 32usize],
1173 pub __align: ::core::ffi::c_long,
1174}
1175#[repr(C)]
1176#[derive(Copy, Clone)]
1177pub union pthread_barrierattr_t {
1178 pub __size: [::core::ffi::c_char; 4usize],
1179 pub __align: ::core::ffi::c_int,
1180}
1181pub type int_least8_t = __int_least8_t;
1182pub type int_least16_t = __int_least16_t;
1183pub type int_least32_t = __int_least32_t;
1184pub type int_least64_t = __int_least64_t;
1185pub type uint_least8_t = __uint_least8_t;
1186pub type uint_least16_t = __uint_least16_t;
1187pub type uint_least32_t = __uint_least32_t;
1188pub type uint_least64_t = __uint_least64_t;
1189pub type int_fast8_t = ::core::ffi::c_schar;
1190pub type int_fast16_t = ::core::ffi::c_long;
1191pub type int_fast32_t = ::core::ffi::c_long;
1192pub type int_fast64_t = ::core::ffi::c_long;
1193pub type uint_fast8_t = ::core::ffi::c_uchar;
1194pub type uint_fast16_t = ::core::ffi::c_ulong;
1195pub type uint_fast32_t = ::core::ffi::c_ulong;
1196pub type uint_fast64_t = ::core::ffi::c_ulong;
1197pub type intmax_t = __intmax_t;
1198pub type uintmax_t = __uintmax_t;
1199pub type __s8 = ::core::ffi::c_schar;
1200pub type __u8 = ::core::ffi::c_uchar;
1201pub type __s16 = ::core::ffi::c_short;
1202pub type __u16 = ::core::ffi::c_ushort;
1203pub type __s32 = ::core::ffi::c_int;
1204pub type __u32 = ::core::ffi::c_uint;
1205pub type __s64 = ::core::ffi::c_longlong;
1206pub type __u64 = ::core::ffi::c_ulonglong;
1207#[repr(C)]
1208#[derive(Debug, Copy, Clone)]
1209pub struct __kernel_fd_set {
1210 pub fds_bits: [::core::ffi::c_ulong; 16usize],
1211}
1212pub type __kernel_sighandler_t =
1213 ::core::option::Option<unsafe extern "C" fn(arg1: ::core::ffi::c_int)>;
1214pub type __kernel_key_t = ::core::ffi::c_int;
1215pub type __kernel_mqd_t = ::core::ffi::c_int;
1216pub type __kernel_old_uid_t = ::core::ffi::c_ushort;
1217pub type __kernel_old_gid_t = ::core::ffi::c_ushort;
1218pub type __kernel_old_dev_t = ::core::ffi::c_ulong;
1219pub type __kernel_long_t = ::core::ffi::c_long;
1220pub type __kernel_ulong_t = ::core::ffi::c_ulong;
1221pub type __kernel_ino_t = __kernel_ulong_t;
1222pub type __kernel_mode_t = ::core::ffi::c_uint;
1223pub type __kernel_pid_t = ::core::ffi::c_int;
1224pub type __kernel_ipc_pid_t = ::core::ffi::c_int;
1225pub type __kernel_uid_t = ::core::ffi::c_uint;
1226pub type __kernel_gid_t = ::core::ffi::c_uint;
1227pub type __kernel_suseconds_t = __kernel_long_t;
1228pub type __kernel_daddr_t = ::core::ffi::c_int;
1229pub type __kernel_uid32_t = ::core::ffi::c_uint;
1230pub type __kernel_gid32_t = ::core::ffi::c_uint;
1231pub type __kernel_size_t = __kernel_ulong_t;
1232pub type __kernel_ssize_t = __kernel_long_t;
1233pub type __kernel_ptrdiff_t = __kernel_long_t;
1234#[repr(C)]
1235#[derive(Debug, Copy, Clone)]
1236pub struct __kernel_fsid_t {
1237 pub val: [::core::ffi::c_int; 2usize],
1238}
1239pub type __kernel_off_t = __kernel_long_t;
1240pub type __kernel_loff_t = ::core::ffi::c_longlong;
1241pub type __kernel_uoff_t = ::core::ffi::c_ulonglong;
1242pub type __kernel_old_time_t = __kernel_long_t;
1243pub type __kernel_time_t = __kernel_long_t;
1244pub type __kernel_time64_t = ::core::ffi::c_longlong;
1245pub type __kernel_clock_t = __kernel_long_t;
1246pub type __kernel_timer_t = ::core::ffi::c_int;
1247pub type __kernel_clockid_t = ::core::ffi::c_int;
1248pub type __kernel_caddr_t = *mut ::core::ffi::c_char;
1249pub type __kernel_uid16_t = ::core::ffi::c_ushort;
1250pub type __kernel_gid16_t = ::core::ffi::c_ushort;
1251pub type __s128 = i128;
1252pub type __u128 = u128;
1253pub type __le16 = __u16;
1254pub type __be16 = __u16;
1255pub type __le32 = __u32;
1256pub type __be32 = __u32;
1257pub type __le64 = __u64;
1258pub type __be64 = __u64;
1259pub type __sum16 = __u16;
1260pub type __wsum = __u32;
1261pub type __poll_t = ::core::ffi::c_uint;
1262pub type drm_handle_t = ::core::ffi::c_uint;
1263pub type drm_context_t = ::core::ffi::c_uint;
1264pub type drm_drawable_t = ::core::ffi::c_uint;
1265pub type drm_magic_t = ::core::ffi::c_uint;
1266#[repr(C)]
1267#[derive(Debug, Copy, Clone)]
1268pub struct drm_clip_rect {
1269 pub x1: ::core::ffi::c_ushort,
1270 pub y1: ::core::ffi::c_ushort,
1271 pub x2: ::core::ffi::c_ushort,
1272 pub y2: ::core::ffi::c_ushort,
1273}
1274#[repr(C)]
1275#[derive(Debug, Copy, Clone)]
1276pub struct drm_drawable_info {
1277 pub num_rects: ::core::ffi::c_uint,
1278 pub rects: *mut drm_clip_rect,
1279}
1280#[repr(C)]
1281#[derive(Debug, Copy, Clone)]
1282pub struct drm_tex_region {
1283 pub next: ::core::ffi::c_uchar,
1284 pub prev: ::core::ffi::c_uchar,
1285 pub in_use: ::core::ffi::c_uchar,
1286 pub padding: ::core::ffi::c_uchar,
1287 pub age: ::core::ffi::c_uint,
1288}
1289#[repr(C)]
1290#[derive(Debug, Copy, Clone)]
1291pub struct drm_hw_lock {
1292 #[doc = "< lock variable"]
1293 pub lock: ::core::ffi::c_uint,
1294 #[doc = "< Pad to cache line"]
1295 pub padding: [::core::ffi::c_char; 60usize],
1296}
1297#[repr(C)]
1298#[derive(Debug, Copy, Clone)]
1299pub struct drm_version {
1300 #[doc = "< Major version"]
1301 pub version_major: ::core::ffi::c_int,
1302 #[doc = "< Minor version"]
1303 pub version_minor: ::core::ffi::c_int,
1304 #[doc = "< Patch level"]
1305 pub version_patchlevel: ::core::ffi::c_int,
1306 #[doc = "< Length of name buffer"]
1307 pub name_len: __kernel_size_t,
1308 #[doc = "< Name of driver"]
1309 pub name: *mut ::core::ffi::c_char,
1310 #[doc = "< Length of date buffer"]
1311 pub date_len: __kernel_size_t,
1312 #[doc = "< User-space buffer to hold date"]
1313 pub date: *mut ::core::ffi::c_char,
1314 #[doc = "< Length of desc buffer"]
1315 pub desc_len: __kernel_size_t,
1316 #[doc = "< User-space buffer to hold desc"]
1317 pub desc: *mut ::core::ffi::c_char,
1318}
1319#[repr(C)]
1320#[derive(Debug, Copy, Clone)]
1321pub struct drm_unique {
1322 #[doc = "< Length of unique"]
1323 pub unique_len: __kernel_size_t,
1324 #[doc = "< Unique name for driver instantiation"]
1325 pub unique: *mut ::core::ffi::c_char,
1326}
1327#[repr(C)]
1328#[derive(Debug, Copy, Clone)]
1329pub struct drm_list {
1330 #[doc = "< Length of user-space structures"]
1331 pub count: ::core::ffi::c_int,
1332 pub version: *mut drm_version,
1333}
1334#[repr(C)]
1335#[derive(Debug, Copy, Clone)]
1336pub struct drm_block {
1337 pub unused: ::core::ffi::c_int,
1338}
1339#[repr(C)]
1340#[derive(Debug, Copy, Clone)]
1341pub struct drm_control {
1342 pub func: drm_control__bindgen_ty_1,
1343 pub irq: ::core::ffi::c_int,
1344}
1345pub const drm_control_DRM_ADD_COMMAND: drm_control__bindgen_ty_1 = 0;
1346pub const drm_control_DRM_RM_COMMAND: drm_control__bindgen_ty_1 = 1;
1347pub const drm_control_DRM_INST_HANDLER: drm_control__bindgen_ty_1 = 2;
1348pub const drm_control_DRM_UNINST_HANDLER: drm_control__bindgen_ty_1 = 3;
1349pub type drm_control__bindgen_ty_1 = ::core::ffi::c_uint;
1350#[doc = "< WC (no caching), no core dump"]
1351pub const drm_map_type__DRM_FRAME_BUFFER: drm_map_type = 0;
1352#[doc = "< no caching, no core dump"]
1353pub const drm_map_type__DRM_REGISTERS: drm_map_type = 1;
1354#[doc = "< shared, cached"]
1355pub const drm_map_type__DRM_SHM: drm_map_type = 2;
1356#[doc = "< AGP/GART"]
1357pub const drm_map_type__DRM_AGP: drm_map_type = 3;
1358#[doc = "< Scatter/gather memory for PCI DMA"]
1359pub const drm_map_type__DRM_SCATTER_GATHER: drm_map_type = 4;
1360#[doc = "< Consistent memory for PCI DMA"]
1361pub const drm_map_type__DRM_CONSISTENT: drm_map_type = 5;
1362pub type drm_map_type = ::core::ffi::c_uint;
1363#[doc = "< Cannot be mapped to user-virtual"]
1364pub const drm_map_flags__DRM_RESTRICTED: drm_map_flags = 1;
1365pub const drm_map_flags__DRM_READ_ONLY: drm_map_flags = 2;
1366#[doc = "< shared, cached, locked"]
1367pub const drm_map_flags__DRM_LOCKED: drm_map_flags = 4;
1368#[doc = "< kernel requires access"]
1369pub const drm_map_flags__DRM_KERNEL: drm_map_flags = 8;
1370#[doc = "< use write-combining if available"]
1371pub const drm_map_flags__DRM_WRITE_COMBINING: drm_map_flags = 16;
1372#[doc = "< SHM page that contains lock"]
1373pub const drm_map_flags__DRM_CONTAINS_LOCK: drm_map_flags = 32;
1374#[doc = "< Removable mapping"]
1375pub const drm_map_flags__DRM_REMOVABLE: drm_map_flags = 64;
1376#[doc = "< Managed by driver"]
1377pub const drm_map_flags__DRM_DRIVER: drm_map_flags = 128;
1378pub type drm_map_flags = ::core::ffi::c_uint;
1379#[repr(C)]
1380#[derive(Debug, Copy, Clone)]
1381pub struct drm_ctx_priv_map {
1382 #[doc = "< Context requesting private mapping"]
1383 pub ctx_id: ::core::ffi::c_uint,
1384 #[doc = "< Handle of map"]
1385 pub handle: *mut ::core::ffi::c_void,
1386}
1387#[repr(C)]
1388#[derive(Debug, Copy, Clone)]
1389pub struct drm_map {
1390 #[doc = "< Requested physical address (0 for SAREA)"]
1391 pub offset: ::core::ffi::c_ulong,
1392 #[doc = "< Requested physical size (bytes)"]
1393 pub size: ::core::ffi::c_ulong,
1394 #[doc = "< Type of memory to map"]
1395 pub type_: drm_map_type,
1396 #[doc = "< Flags"]
1397 pub flags: drm_map_flags,
1398 #[doc = "< User-space: \"Handle\" to pass to mmap() */\n/**< Kernel-space: kernel-virtual address"]
1399 pub handle: *mut ::core::ffi::c_void,
1400 #[doc = "< MTRR slot used"]
1401 pub mtrr: ::core::ffi::c_int,
1402}
1403#[repr(C)]
1404#[derive(Debug, Copy, Clone)]
1405pub struct drm_client {
1406 #[doc = "< Which client desired?"]
1407 pub idx: ::core::ffi::c_int,
1408 #[doc = "< Is client authenticated?"]
1409 pub auth: ::core::ffi::c_int,
1410 #[doc = "< Process ID"]
1411 pub pid: ::core::ffi::c_ulong,
1412 #[doc = "< User ID"]
1413 pub uid: ::core::ffi::c_ulong,
1414 #[doc = "< Magic"]
1415 pub magic: ::core::ffi::c_ulong,
1416 #[doc = "< Ioctl count"]
1417 pub iocs: ::core::ffi::c_ulong,
1418}
1419pub const drm_stat_type__DRM_STAT_LOCK: drm_stat_type = 0;
1420pub const drm_stat_type__DRM_STAT_OPENS: drm_stat_type = 1;
1421pub const drm_stat_type__DRM_STAT_CLOSES: drm_stat_type = 2;
1422pub const drm_stat_type__DRM_STAT_IOCTLS: drm_stat_type = 3;
1423pub const drm_stat_type__DRM_STAT_LOCKS: drm_stat_type = 4;
1424pub const drm_stat_type__DRM_STAT_UNLOCKS: drm_stat_type = 5;
1425#[doc = "< Generic value"]
1426pub const drm_stat_type__DRM_STAT_VALUE: drm_stat_type = 6;
1427#[doc = "< Generic byte counter (1024bytes/K)"]
1428pub const drm_stat_type__DRM_STAT_BYTE: drm_stat_type = 7;
1429#[doc = "< Generic non-byte counter (1000/k)"]
1430pub const drm_stat_type__DRM_STAT_COUNT: drm_stat_type = 8;
1431#[doc = "< IRQ"]
1432pub const drm_stat_type__DRM_STAT_IRQ: drm_stat_type = 9;
1433#[doc = "< Primary DMA bytes"]
1434pub const drm_stat_type__DRM_STAT_PRIMARY: drm_stat_type = 10;
1435#[doc = "< Secondary DMA bytes"]
1436pub const drm_stat_type__DRM_STAT_SECONDARY: drm_stat_type = 11;
1437#[doc = "< DMA"]
1438pub const drm_stat_type__DRM_STAT_DMA: drm_stat_type = 12;
1439#[doc = "< Special DMA (e.g., priority or polled)"]
1440pub const drm_stat_type__DRM_STAT_SPECIAL: drm_stat_type = 13;
1441#[doc = "< Missed DMA opportunity"]
1442pub const drm_stat_type__DRM_STAT_MISSED: drm_stat_type = 14;
1443pub type drm_stat_type = ::core::ffi::c_uint;
1444#[repr(C)]
1445#[derive(Debug, Copy, Clone)]
1446pub struct drm_stats {
1447 pub count: ::core::ffi::c_ulong,
1448 pub data: [drm_stats__bindgen_ty_1; 15usize],
1449}
1450#[repr(C)]
1451#[derive(Debug, Copy, Clone)]
1452pub struct drm_stats__bindgen_ty_1 {
1453 pub value: ::core::ffi::c_ulong,
1454 pub type_: drm_stat_type,
1455}
1456#[doc = "< Wait until hardware is ready for DMA"]
1457pub const drm_lock_flags__DRM_LOCK_READY: drm_lock_flags = 1;
1458#[doc = "< Wait until hardware quiescent"]
1459pub const drm_lock_flags__DRM_LOCK_QUIESCENT: drm_lock_flags = 2;
1460#[doc = "< Flush this context's DMA queue first"]
1461pub const drm_lock_flags__DRM_LOCK_FLUSH: drm_lock_flags = 4;
1462#[doc = "< Flush all DMA queues first"]
1463pub const drm_lock_flags__DRM_LOCK_FLUSH_ALL: drm_lock_flags = 8;
1464#[doc = "< Halt all current and future queues"]
1465pub const drm_lock_flags__DRM_HALT_ALL_QUEUES: drm_lock_flags = 16;
1466#[doc = "< Halt all current queues"]
1467pub const drm_lock_flags__DRM_HALT_CUR_QUEUES: drm_lock_flags = 32;
1468pub type drm_lock_flags = ::core::ffi::c_uint;
1469#[repr(C)]
1470#[derive(Debug, Copy, Clone)]
1471pub struct drm_lock {
1472 pub context: ::core::ffi::c_int,
1473 pub flags: drm_lock_flags,
1474}
1475#[doc = "<\n Block until buffer dispatched.\n\n \\note The buffer may not yet have\n been processed by the hardware --\n getting a hardware lock with the\n hardware quiescent will ensure\n that the buffer has been\n processed."]
1476pub const drm_dma_flags__DRM_DMA_BLOCK: drm_dma_flags = 1;
1477#[doc = "< Dispatch while lock held"]
1478pub const drm_dma_flags__DRM_DMA_WHILE_LOCKED: drm_dma_flags = 2;
1479#[doc = "< High priority dispatch"]
1480pub const drm_dma_flags__DRM_DMA_PRIORITY: drm_dma_flags = 4;
1481#[doc = "< Wait for free buffers"]
1482pub const drm_dma_flags__DRM_DMA_WAIT: drm_dma_flags = 16;
1483#[doc = "< Smaller-than-requested buffers OK"]
1484pub const drm_dma_flags__DRM_DMA_SMALLER_OK: drm_dma_flags = 32;
1485#[doc = "< Larger-than-requested buffers OK"]
1486pub const drm_dma_flags__DRM_DMA_LARGER_OK: drm_dma_flags = 64;
1487pub type drm_dma_flags = ::core::ffi::c_uint;
1488#[repr(C)]
1489#[derive(Debug, Copy, Clone)]
1490pub struct drm_buf_desc {
1491 #[doc = "< Number of buffers of this size"]
1492 pub count: ::core::ffi::c_int,
1493 #[doc = "< Size in bytes"]
1494 pub size: ::core::ffi::c_int,
1495 #[doc = "< Low water mark"]
1496 pub low_mark: ::core::ffi::c_int,
1497 #[doc = "< High water mark"]
1498 pub high_mark: ::core::ffi::c_int,
1499 pub flags: drm_buf_desc__bindgen_ty_1,
1500 #[doc = "<\n Start address of where the AGP buffers are\n in the AGP aperture"]
1501 pub agp_start: ::core::ffi::c_ulong,
1502}
1503#[doc = "< Align on page boundaries for DMA"]
1504pub const drm_buf_desc__DRM_PAGE_ALIGN: drm_buf_desc__bindgen_ty_1 = 1;
1505#[doc = "< Buffer is in AGP space"]
1506pub const drm_buf_desc__DRM_AGP_BUFFER: drm_buf_desc__bindgen_ty_1 = 2;
1507#[doc = "< Scatter/gather memory buffer"]
1508pub const drm_buf_desc__DRM_SG_BUFFER: drm_buf_desc__bindgen_ty_1 = 4;
1509#[doc = "< Buffer is in frame buffer"]
1510pub const drm_buf_desc__DRM_FB_BUFFER: drm_buf_desc__bindgen_ty_1 = 8;
1511#[doc = "< Map PCI DMA buffer read-only"]
1512pub const drm_buf_desc__DRM_PCI_BUFFER_RO: drm_buf_desc__bindgen_ty_1 = 16;
1513pub type drm_buf_desc__bindgen_ty_1 = ::core::ffi::c_uint;
1514#[repr(C)]
1515#[derive(Debug, Copy, Clone)]
1516pub struct drm_buf_info {
1517 #[doc = "< Entries in list"]
1518 pub count: ::core::ffi::c_int,
1519 pub list: *mut drm_buf_desc,
1520}
1521#[repr(C)]
1522#[derive(Debug, Copy, Clone)]
1523pub struct drm_buf_free {
1524 pub count: ::core::ffi::c_int,
1525 pub list: *mut ::core::ffi::c_int,
1526}
1527#[repr(C)]
1528#[derive(Debug, Copy, Clone)]
1529pub struct drm_buf_pub {
1530 #[doc = "< Index into the master buffer list"]
1531 pub idx: ::core::ffi::c_int,
1532 #[doc = "< Buffer size"]
1533 pub total: ::core::ffi::c_int,
1534 #[doc = "< Amount of buffer in use (for DMA)"]
1535 pub used: ::core::ffi::c_int,
1536 #[doc = "< Address of buffer"]
1537 pub address: *mut ::core::ffi::c_void,
1538}
1539#[repr(C)]
1540#[derive(Debug, Copy, Clone)]
1541pub struct drm_buf_map {
1542 #[doc = "< Length of the buffer list"]
1543 pub count: ::core::ffi::c_int,
1544 #[doc = "< Mmap'd area in user-virtual"]
1545 pub virtual_: *mut ::core::ffi::c_void,
1546 #[doc = "< Buffer information"]
1547 pub list: *mut drm_buf_pub,
1548}
1549#[repr(C)]
1550#[derive(Debug, Copy, Clone)]
1551pub struct drm_dma {
1552 #[doc = "< Context handle"]
1553 pub context: ::core::ffi::c_int,
1554 #[doc = "< Number of buffers to send"]
1555 pub send_count: ::core::ffi::c_int,
1556 #[doc = "< List of handles to buffers"]
1557 pub send_indices: *mut ::core::ffi::c_int,
1558 #[doc = "< Lengths of data to send"]
1559 pub send_sizes: *mut ::core::ffi::c_int,
1560 #[doc = "< Flags"]
1561 pub flags: drm_dma_flags,
1562 #[doc = "< Number of buffers requested"]
1563 pub request_count: ::core::ffi::c_int,
1564 #[doc = "< Desired size for buffers"]
1565 pub request_size: ::core::ffi::c_int,
1566 #[doc = "< Buffer information"]
1567 pub request_indices: *mut ::core::ffi::c_int,
1568 pub request_sizes: *mut ::core::ffi::c_int,
1569 #[doc = "< Number of buffers granted"]
1570 pub granted_count: ::core::ffi::c_int,
1571}
1572pub const drm_ctx_flags__DRM_CONTEXT_PRESERVED: drm_ctx_flags = 1;
1573pub const drm_ctx_flags__DRM_CONTEXT_2DONLY: drm_ctx_flags = 2;
1574pub type drm_ctx_flags = ::core::ffi::c_uint;
1575#[repr(C)]
1576#[derive(Debug, Copy, Clone)]
1577pub struct drm_ctx {
1578 pub handle: drm_context_t,
1579 pub flags: drm_ctx_flags,
1580}
1581#[repr(C)]
1582#[derive(Debug, Copy, Clone)]
1583pub struct drm_ctx_res {
1584 pub count: ::core::ffi::c_int,
1585 pub contexts: *mut drm_ctx,
1586}
1587#[repr(C)]
1588#[derive(Debug, Copy, Clone)]
1589pub struct drm_draw {
1590 pub handle: drm_drawable_t,
1591}
1592pub const drm_drawable_info_type_t_DRM_DRAWABLE_CLIPRECTS: drm_drawable_info_type_t = 0;
1593pub type drm_drawable_info_type_t = ::core::ffi::c_uint;
1594#[repr(C)]
1595#[derive(Debug, Copy, Clone)]
1596pub struct drm_update_draw {
1597 pub handle: drm_drawable_t,
1598 pub type_: ::core::ffi::c_uint,
1599 pub num: ::core::ffi::c_uint,
1600 pub data: ::core::ffi::c_ulonglong,
1601}
1602#[repr(C)]
1603#[derive(Debug, Copy, Clone)]
1604pub struct drm_auth {
1605 pub magic: drm_magic_t,
1606}
1607#[repr(C)]
1608#[derive(Debug, Copy, Clone)]
1609pub struct drm_irq_busid {
1610 #[doc = "< IRQ number"]
1611 pub irq: ::core::ffi::c_int,
1612 #[doc = "< bus number"]
1613 pub busnum: ::core::ffi::c_int,
1614 #[doc = "< device number"]
1615 pub devnum: ::core::ffi::c_int,
1616 #[doc = "< function number"]
1617 pub funcnum: ::core::ffi::c_int,
1618}
1619#[doc = "< Wait for specific vblank sequence number"]
1620pub const drm_vblank_seq_type__DRM_VBLANK_ABSOLUTE: drm_vblank_seq_type = 0;
1621#[doc = "< Wait for given number of vblanks"]
1622pub const drm_vblank_seq_type__DRM_VBLANK_RELATIVE: drm_vblank_seq_type = 1;
1623pub const drm_vblank_seq_type__DRM_VBLANK_HIGH_CRTC_MASK: drm_vblank_seq_type = 62;
1624#[doc = "< Send event instead of blocking"]
1625pub const drm_vblank_seq_type__DRM_VBLANK_EVENT: drm_vblank_seq_type = 67108864;
1626#[doc = "< Scheduled buffer swap should flip"]
1627pub const drm_vblank_seq_type__DRM_VBLANK_FLIP: drm_vblank_seq_type = 134217728;
1628#[doc = "< If missed, wait for next vblank"]
1629pub const drm_vblank_seq_type__DRM_VBLANK_NEXTONMISS: drm_vblank_seq_type = 268435456;
1630#[doc = "< Secondary display controller"]
1631pub const drm_vblank_seq_type__DRM_VBLANK_SECONDARY: drm_vblank_seq_type = 536870912;
1632#[doc = "< Send signal instead of blocking, unsupported"]
1633pub const drm_vblank_seq_type__DRM_VBLANK_SIGNAL: drm_vblank_seq_type = 1073741824;
1634pub type drm_vblank_seq_type = ::core::ffi::c_uint;
1635#[repr(C)]
1636#[derive(Debug, Copy, Clone)]
1637pub struct drm_wait_vblank_request {
1638 pub type_: drm_vblank_seq_type,
1639 pub sequence: ::core::ffi::c_uint,
1640 pub signal: ::core::ffi::c_ulong,
1641}
1642#[repr(C)]
1643#[derive(Debug, Copy, Clone)]
1644pub struct drm_wait_vblank_reply {
1645 pub type_: drm_vblank_seq_type,
1646 pub sequence: ::core::ffi::c_uint,
1647 pub tval_sec: ::core::ffi::c_long,
1648 pub tval_usec: ::core::ffi::c_long,
1649}
1650#[repr(C)]
1651#[derive(Copy, Clone)]
1652pub union drm_wait_vblank {
1653 pub request: drm_wait_vblank_request,
1654 pub reply: drm_wait_vblank_reply,
1655}
1656#[repr(C)]
1657#[derive(Debug, Copy, Clone)]
1658pub struct drm_modeset_ctl {
1659 pub crtc: __u32,
1660 pub cmd: __u32,
1661}
1662#[repr(C)]
1663#[derive(Debug, Copy, Clone)]
1664pub struct drm_agp_mode {
1665 #[doc = "< AGP mode"]
1666 pub mode: ::core::ffi::c_ulong,
1667}
1668#[repr(C)]
1669#[derive(Debug, Copy, Clone)]
1670pub struct drm_agp_buffer {
1671 #[doc = "< In bytes -- will round to page boundary"]
1672 pub size: ::core::ffi::c_ulong,
1673 #[doc = "< Used for binding / unbinding"]
1674 pub handle: ::core::ffi::c_ulong,
1675 #[doc = "< Type of memory to allocate"]
1676 pub type_: ::core::ffi::c_ulong,
1677 #[doc = "< Physical used by i810"]
1678 pub physical: ::core::ffi::c_ulong,
1679}
1680#[repr(C)]
1681#[derive(Debug, Copy, Clone)]
1682pub struct drm_agp_binding {
1683 #[doc = "< From drm_agp_buffer"]
1684 pub handle: ::core::ffi::c_ulong,
1685 #[doc = "< In bytes -- will round to page boundary"]
1686 pub offset: ::core::ffi::c_ulong,
1687}
1688#[repr(C)]
1689#[derive(Debug, Copy, Clone)]
1690pub struct drm_agp_info {
1691 pub agp_version_major: ::core::ffi::c_int,
1692 pub agp_version_minor: ::core::ffi::c_int,
1693 pub mode: ::core::ffi::c_ulong,
1694 pub aperture_base: ::core::ffi::c_ulong,
1695 pub aperture_size: ::core::ffi::c_ulong,
1696 pub memory_allowed: ::core::ffi::c_ulong,
1697 pub memory_used: ::core::ffi::c_ulong,
1698 pub id_vendor: ::core::ffi::c_ushort,
1699 pub id_device: ::core::ffi::c_ushort,
1700}
1701#[repr(C)]
1702#[derive(Debug, Copy, Clone)]
1703pub struct drm_scatter_gather {
1704 #[doc = "< In bytes -- will round to page boundary"]
1705 pub size: ::core::ffi::c_ulong,
1706 #[doc = "< Used for mapping / unmapping"]
1707 pub handle: ::core::ffi::c_ulong,
1708}
1709#[repr(C)]
1710#[derive(Debug, Copy, Clone)]
1711pub struct drm_set_version {
1712 pub drm_di_major: ::core::ffi::c_int,
1713 pub drm_di_minor: ::core::ffi::c_int,
1714 pub drm_dd_major: ::core::ffi::c_int,
1715 pub drm_dd_minor: ::core::ffi::c_int,
1716}
1717#[repr(C)]
1718#[derive(Debug, Copy, Clone)]
1719pub struct drm_gem_close {
1720 #[doc = " Handle of the object to be closed."]
1721 pub handle: __u32,
1722 pub pad: __u32,
1723}
1724#[repr(C)]
1725#[derive(Debug, Copy, Clone)]
1726pub struct drm_gem_flink {
1727 #[doc = " Handle for the object being named"]
1728 pub handle: __u32,
1729 #[doc = " Returned global name"]
1730 pub name: __u32,
1731}
1732#[repr(C)]
1733#[derive(Debug, Copy, Clone)]
1734pub struct drm_gem_open {
1735 #[doc = " Name of object being opened"]
1736 pub name: __u32,
1737 #[doc = " Returned handle for the object"]
1738 pub handle: __u32,
1739 #[doc = " Returned size of the object"]
1740 pub size: __u64,
1741}
1742#[repr(C)]
1743#[derive(Debug, Copy, Clone)]
1744pub struct drm_get_cap {
1745 pub capability: __u64,
1746 pub value: __u64,
1747}
1748#[repr(C)]
1749#[derive(Debug, Copy, Clone)]
1750pub struct drm_set_client_cap {
1751 pub capability: __u64,
1752 pub value: __u64,
1753}
1754#[repr(C)]
1755#[derive(Debug, Copy, Clone)]
1756pub struct drm_prime_handle {
1757 pub handle: __u32,
1758 #[doc = " Flags.. only applicable for handle->fd"]
1759 pub flags: __u32,
1760 #[doc = " Returned dmabuf file descriptor"]
1761 pub fd: __s32,
1762}
1763#[repr(C)]
1764#[derive(Debug, Copy, Clone)]
1765pub struct drm_syncobj_create {
1766 pub handle: __u32,
1767 pub flags: __u32,
1768}
1769#[repr(C)]
1770#[derive(Debug, Copy, Clone)]
1771pub struct drm_syncobj_destroy {
1772 pub handle: __u32,
1773 pub pad: __u32,
1774}
1775#[repr(C)]
1776#[derive(Debug, Copy, Clone)]
1777pub struct drm_syncobj_handle {
1778 pub handle: __u32,
1779 pub flags: __u32,
1780 pub fd: __s32,
1781 pub pad: __u32,
1782}
1783#[repr(C)]
1784#[derive(Debug, Copy, Clone)]
1785pub struct drm_syncobj_transfer {
1786 pub src_handle: __u32,
1787 pub dst_handle: __u32,
1788 pub src_point: __u64,
1789 pub dst_point: __u64,
1790 pub flags: __u32,
1791 pub pad: __u32,
1792}
1793#[repr(C)]
1794#[derive(Debug, Copy, Clone)]
1795pub struct drm_syncobj_wait {
1796 pub handles: __u64,
1797 pub timeout_nsec: __s64,
1798 pub count_handles: __u32,
1799 pub flags: __u32,
1800 pub first_signaled: __u32,
1801 pub pad: __u32,
1802 #[doc = " @deadline_nsec - fence deadline hint\n\n Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing\n fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is\n set."]
1803 pub deadline_nsec: __u64,
1804}
1805#[repr(C)]
1806#[derive(Debug, Copy, Clone)]
1807pub struct drm_syncobj_timeline_wait {
1808 pub handles: __u64,
1809 pub points: __u64,
1810 pub timeout_nsec: __s64,
1811 pub count_handles: __u32,
1812 pub flags: __u32,
1813 pub first_signaled: __u32,
1814 pub pad: __u32,
1815 #[doc = " @deadline_nsec - fence deadline hint\n\n Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing\n fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is\n set."]
1816 pub deadline_nsec: __u64,
1817}
1818#[doc = " struct drm_syncobj_eventfd\n @handle: syncobj handle.\n @flags: Zero to wait for the point to be signalled, or\n &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be\n available for the point.\n @point: syncobj timeline point (set to zero for binary syncobjs).\n @fd: Existing eventfd to sent events to.\n @pad: Must be zero.\n\n Register an eventfd to be signalled by a syncobj. The eventfd counter will\n be incremented by one."]
1819#[repr(C)]
1820#[derive(Debug, Copy, Clone)]
1821pub struct drm_syncobj_eventfd {
1822 pub handle: __u32,
1823 pub flags: __u32,
1824 pub point: __u64,
1825 pub fd: __s32,
1826 pub pad: __u32,
1827}
1828#[repr(C)]
1829#[derive(Debug, Copy, Clone)]
1830pub struct drm_syncobj_array {
1831 pub handles: __u64,
1832 pub count_handles: __u32,
1833 pub pad: __u32,
1834}
1835#[repr(C)]
1836#[derive(Debug, Copy, Clone)]
1837pub struct drm_syncobj_timeline_array {
1838 pub handles: __u64,
1839 pub points: __u64,
1840 pub count_handles: __u32,
1841 pub flags: __u32,
1842}
1843#[repr(C)]
1844#[derive(Debug, Copy, Clone)]
1845pub struct drm_crtc_get_sequence {
1846 pub crtc_id: __u32,
1847 pub active: __u32,
1848 pub sequence: __u64,
1849 pub sequence_ns: __s64,
1850}
1851#[repr(C)]
1852#[derive(Debug, Copy, Clone)]
1853pub struct drm_crtc_queue_sequence {
1854 pub crtc_id: __u32,
1855 pub flags: __u32,
1856 pub sequence: __u64,
1857 pub user_data: __u64,
1858}
1859#[doc = " struct drm_mode_modeinfo - Display mode information.\n @clock: pixel clock in kHz\n @hdisplay: horizontal display size\n @hsync_start: horizontal sync start\n @hsync_end: horizontal sync end\n @htotal: horizontal total size\n @hskew: horizontal skew\n @vdisplay: vertical display size\n @vsync_start: vertical sync start\n @vsync_end: vertical sync end\n @vtotal: vertical total size\n @vscan: vertical scan\n @vrefresh: approximate vertical refresh rate in Hz\n @flags: bitmask of misc. flags, see DRM_MODE_FLAG_* defines\n @type: bitmask of type flags, see DRM_MODE_TYPE_* defines\n @name: string describing the mode resolution\n\n This is the user-space API display mode information structure. For the\n kernel version see struct drm_display_mode."]
1860#[repr(C)]
1861#[derive(Debug, Copy, Clone)]
1862pub struct drm_mode_modeinfo {
1863 pub clock: __u32,
1864 pub hdisplay: __u16,
1865 pub hsync_start: __u16,
1866 pub hsync_end: __u16,
1867 pub htotal: __u16,
1868 pub hskew: __u16,
1869 pub vdisplay: __u16,
1870 pub vsync_start: __u16,
1871 pub vsync_end: __u16,
1872 pub vtotal: __u16,
1873 pub vscan: __u16,
1874 pub vrefresh: __u32,
1875 pub flags: __u32,
1876 pub type_: __u32,
1877 pub name: [::core::ffi::c_char; 32usize],
1878}
1879#[repr(C)]
1880#[derive(Debug, Copy, Clone)]
1881pub struct drm_mode_card_res {
1882 pub fb_id_ptr: __u64,
1883 pub crtc_id_ptr: __u64,
1884 pub connector_id_ptr: __u64,
1885 pub encoder_id_ptr: __u64,
1886 pub count_fbs: __u32,
1887 pub count_crtcs: __u32,
1888 pub count_connectors: __u32,
1889 pub count_encoders: __u32,
1890 pub min_width: __u32,
1891 pub max_width: __u32,
1892 pub min_height: __u32,
1893 pub max_height: __u32,
1894}
1895#[repr(C)]
1896#[derive(Debug, Copy, Clone)]
1897pub struct drm_mode_crtc {
1898 pub set_connectors_ptr: __u64,
1899 pub count_connectors: __u32,
1900 #[doc = "< Id"]
1901 pub crtc_id: __u32,
1902 #[doc = "< Id of framebuffer"]
1903 pub fb_id: __u32,
1904 #[doc = "< x Position on the framebuffer"]
1905 pub x: __u32,
1906 #[doc = "< y Position on the framebuffer"]
1907 pub y: __u32,
1908 pub gamma_size: __u32,
1909 pub mode_valid: __u32,
1910 pub mode: drm_mode_modeinfo,
1911}
1912#[repr(C)]
1913#[derive(Debug, Copy, Clone)]
1914pub struct drm_mode_set_plane {
1915 pub plane_id: __u32,
1916 pub crtc_id: __u32,
1917 pub fb_id: __u32,
1918 pub flags: __u32,
1919 pub crtc_x: __s32,
1920 pub crtc_y: __s32,
1921 pub crtc_w: __u32,
1922 pub crtc_h: __u32,
1923 pub src_x: __u32,
1924 pub src_y: __u32,
1925 pub src_h: __u32,
1926 pub src_w: __u32,
1927}
1928#[doc = " struct drm_mode_get_plane - Get plane metadata.\n\n Userspace can perform a GETPLANE ioctl to retrieve information about a\n plane.\n\n To retrieve the number of formats supported, set @count_format_types to zero\n and call the ioctl. @count_format_types will be updated with the value.\n\n To retrieve these formats, allocate an array with the memory needed to store\n @count_format_types formats. Point @format_type_ptr to this array and call\n the ioctl again (with @count_format_types still set to the value returned in\n the first ioctl call)."]
1929#[repr(C)]
1930#[derive(Debug, Copy, Clone)]
1931pub struct drm_mode_get_plane {
1932 #[doc = " @plane_id: Object ID of the plane whose information should be\n retrieved. Set by caller."]
1933 pub plane_id: __u32,
1934 #[doc = " @crtc_id: Object ID of the current CRTC."]
1935 pub crtc_id: __u32,
1936 #[doc = " @fb_id: Object ID of the current fb."]
1937 pub fb_id: __u32,
1938 #[doc = " @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's\n are created and they receive an index, which corresponds to their\n position in the bitmask. Bit N corresponds to\n :ref:`CRTC index<crtc_index>` N."]
1939 pub possible_crtcs: __u32,
1940 #[doc = " @gamma_size: Never used."]
1941 pub gamma_size: __u32,
1942 #[doc = " @count_format_types: Number of formats."]
1943 pub count_format_types: __u32,
1944 #[doc = " @format_type_ptr: Pointer to ``__u32`` array of formats that are\n supported by the plane. These formats do not require modifiers."]
1945 pub format_type_ptr: __u64,
1946}
1947#[repr(C)]
1948#[derive(Debug, Copy, Clone)]
1949pub struct drm_mode_get_plane_res {
1950 pub plane_id_ptr: __u64,
1951 pub count_planes: __u32,
1952}
1953#[repr(C)]
1954#[derive(Debug, Copy, Clone)]
1955pub struct drm_mode_get_encoder {
1956 pub encoder_id: __u32,
1957 pub encoder_type: __u32,
1958 #[doc = "< Id of crtc"]
1959 pub crtc_id: __u32,
1960 pub possible_crtcs: __u32,
1961 pub possible_clones: __u32,
1962}
1963pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Automatic: drm_mode_subconnector = 0;
1964pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Unknown: drm_mode_subconnector = 0;
1965pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_VGA: drm_mode_subconnector = 1;
1966pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DVID: drm_mode_subconnector = 3;
1967pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DVIA: drm_mode_subconnector = 4;
1968pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Composite: drm_mode_subconnector = 5;
1969pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_SVIDEO: drm_mode_subconnector = 6;
1970pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Component: drm_mode_subconnector = 8;
1971pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_SCART: drm_mode_subconnector = 9;
1972pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DisplayPort: drm_mode_subconnector = 10;
1973pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_HDMIA: drm_mode_subconnector = 11;
1974pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Native: drm_mode_subconnector = 15;
1975pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Wireless: drm_mode_subconnector = 18;
1976pub type drm_mode_subconnector = ::core::ffi::c_uint;
1977#[doc = " struct drm_mode_get_connector - Get connector metadata.\n\n User-space can perform a GETCONNECTOR ioctl to retrieve information about a\n connector. User-space is expected to retrieve encoders, modes and properties\n by performing this ioctl at least twice: the first time to retrieve the\n number of elements, the second time to retrieve the elements themselves.\n\n To retrieve the number of elements, set @count_props and @count_encoders to\n zero, set @count_modes to 1, and set @modes_ptr to a temporary struct\n drm_mode_modeinfo element.\n\n To retrieve the elements, allocate arrays for @encoders_ptr, @modes_ptr,\n @props_ptr and @prop_values_ptr, then set @count_modes, @count_props and\n @count_encoders to their capacity.\n\n Performing the ioctl only twice may be racy: the number of elements may have\n changed with a hotplug event in-between the two ioctls. User-space is\n expected to retry the last ioctl until the number of elements stabilizes.\n The kernel won't fill any array which doesn't have the expected length.\n\n **Force-probing a connector**\n\n If the @count_modes field is set to zero and the DRM client is the current\n DRM master, the kernel will perform a forced probe on the connector to\n refresh the connector status, modes and EDID. A forced-probe can be slow,\n might cause flickering and the ioctl will block.\n\n User-space needs to force-probe connectors to ensure their metadata is\n up-to-date at startup and after receiving a hot-plug event. User-space\n may perform a forced-probe when the user explicitly requests it. User-space\n shouldn't perform a forced-probe in other situations."]
1978#[repr(C)]
1979#[derive(Debug, Copy, Clone)]
1980pub struct drm_mode_get_connector {
1981 #[doc = " @encoders_ptr: Pointer to ``__u32`` array of object IDs."]
1982 pub encoders_ptr: __u64,
1983 #[doc = " @modes_ptr: Pointer to struct drm_mode_modeinfo array."]
1984 pub modes_ptr: __u64,
1985 #[doc = " @props_ptr: Pointer to ``__u32`` array of property IDs."]
1986 pub props_ptr: __u64,
1987 #[doc = " @prop_values_ptr: Pointer to ``__u64`` array of property values."]
1988 pub prop_values_ptr: __u64,
1989 #[doc = " @count_modes: Number of modes."]
1990 pub count_modes: __u32,
1991 #[doc = " @count_props: Number of properties."]
1992 pub count_props: __u32,
1993 #[doc = " @count_encoders: Number of encoders."]
1994 pub count_encoders: __u32,
1995 #[doc = " @encoder_id: Object ID of the current encoder."]
1996 pub encoder_id: __u32,
1997 #[doc = " @connector_id: Object ID of the connector."]
1998 pub connector_id: __u32,
1999 #[doc = " @connector_type: Type of the connector.\n\n See DRM_MODE_CONNECTOR_* defines."]
2000 pub connector_type: __u32,
2001 #[doc = " @connector_type_id: Type-specific connector number.\n\n This is not an object ID. This is a per-type connector number. Each\n (type, type_id) combination is unique across all connectors of a DRM\n device.\n\n The (type, type_id) combination is not a stable identifier: the\n type_id can change depending on the driver probe order."]
2002 pub connector_type_id: __u32,
2003 #[doc = " @connection: Status of the connector.\n\n See enum drm_connector_status."]
2004 pub connection: __u32,
2005 #[doc = " @mm_width: Width of the connected sink in millimeters."]
2006 pub mm_width: __u32,
2007 #[doc = " @mm_height: Height of the connected sink in millimeters."]
2008 pub mm_height: __u32,
2009 #[doc = " @subpixel: Subpixel order of the connected sink.\n\n See enum subpixel_order."]
2010 pub subpixel: __u32,
2011 #[doc = " @pad: Padding, must be zero."]
2012 pub pad: __u32,
2013}
2014#[doc = " struct drm_mode_property_enum - Description for an enum/bitfield entry.\n @value: numeric value for this enum entry.\n @name: symbolic name for this enum entry.\n\n See struct drm_property_enum for details."]
2015#[repr(C)]
2016#[derive(Debug, Copy, Clone)]
2017pub struct drm_mode_property_enum {
2018 pub value: __u64,
2019 pub name: [::core::ffi::c_char; 32usize],
2020}
2021#[doc = " struct drm_mode_get_property - Get property metadata.\n\n User-space can perform a GETPROPERTY ioctl to retrieve information about a\n property. The same property may be attached to multiple objects, see\n \"Modeset Base Object Abstraction\".\n\n The meaning of the @values_ptr field changes depending on the property type.\n See &drm_property.flags for more details.\n\n The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the\n property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For\n backwards compatibility, the kernel will always set @count_enum_blobs to\n zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must\n ignore these two fields if the property has a different type.\n\n User-space is expected to retrieve values and enums by performing this ioctl\n at least twice: the first time to retrieve the number of elements, the\n second time to retrieve the elements themselves.\n\n To retrieve the number of elements, set @count_values and @count_enum_blobs\n to zero, then call the ioctl. @count_values will be updated with the number\n of elements. If the property has the type &DRM_MODE_PROP_ENUM or\n &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.\n\n To retrieve the elements themselves, allocate an array for @values_ptr and\n set @count_values to its capacity. If the property has the type\n &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for\n @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl\n again will fill the arrays."]
2022#[repr(C)]
2023#[derive(Debug, Copy, Clone)]
2024pub struct drm_mode_get_property {
2025 #[doc = " @values_ptr: Pointer to a ``__u64`` array."]
2026 pub values_ptr: __u64,
2027 #[doc = " @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array."]
2028 pub enum_blob_ptr: __u64,
2029 #[doc = " @prop_id: Object ID of the property which should be retrieved. Set\n by the caller."]
2030 pub prop_id: __u32,
2031 #[doc = " @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for\n a definition of the flags."]
2032 pub flags: __u32,
2033 #[doc = " @name: Symbolic property name. User-space should use this field to\n recognize properties."]
2034 pub name: [::core::ffi::c_char; 32usize],
2035 #[doc = " @count_values: Number of elements in @values_ptr."]
2036 pub count_values: __u32,
2037 #[doc = " @count_enum_blobs: Number of elements in @enum_blob_ptr."]
2038 pub count_enum_blobs: __u32,
2039}
2040#[repr(C)]
2041#[derive(Debug, Copy, Clone)]
2042pub struct drm_mode_connector_set_property {
2043 pub value: __u64,
2044 pub prop_id: __u32,
2045 pub connector_id: __u32,
2046}
2047#[repr(C)]
2048#[derive(Debug, Copy, Clone)]
2049pub struct drm_mode_obj_get_properties {
2050 pub props_ptr: __u64,
2051 pub prop_values_ptr: __u64,
2052 pub count_props: __u32,
2053 pub obj_id: __u32,
2054 pub obj_type: __u32,
2055}
2056#[repr(C)]
2057#[derive(Debug, Copy, Clone)]
2058pub struct drm_mode_obj_set_property {
2059 pub value: __u64,
2060 pub prop_id: __u32,
2061 pub obj_id: __u32,
2062 pub obj_type: __u32,
2063}
2064#[repr(C)]
2065#[derive(Debug, Copy, Clone)]
2066pub struct drm_mode_get_blob {
2067 pub blob_id: __u32,
2068 pub length: __u32,
2069 pub data: __u64,
2070}
2071#[repr(C)]
2072#[derive(Debug, Copy, Clone)]
2073pub struct drm_mode_fb_cmd {
2074 pub fb_id: __u32,
2075 pub width: __u32,
2076 pub height: __u32,
2077 pub pitch: __u32,
2078 pub bpp: __u32,
2079 pub depth: __u32,
2080 pub handle: __u32,
2081}
2082#[doc = " struct drm_mode_fb_cmd2 - Frame-buffer metadata.\n\n This struct holds frame-buffer metadata. There are two ways to use it:\n\n - User-space can fill this struct and perform a &DRM_IOCTL_MODE_ADDFB2\n ioctl to register a new frame-buffer. The new frame-buffer object ID will\n be set by the kernel in @fb_id.\n - User-space can set @fb_id and perform a &DRM_IOCTL_MODE_GETFB2 ioctl to\n fetch metadata about an existing frame-buffer.\n\n In case of planar formats, this struct allows up to 4 buffer objects with\n offsets and pitches per plane. The pitch and offset order are dictated by\n the format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as:\n\n YUV 4:2:0 image with a plane of 8-bit Y samples followed by an\n interleaved U/V plane containing 8-bit 2x2 subsampled colour difference\n samples.\n\n So it would consist of a Y plane at ``offsets[0]`` and a UV plane at\n ``offsets[1]``.\n\n To accommodate tiled, compressed, etc formats, a modifier can be specified.\n For more information see the \"Format Modifiers\" section. Note that even\n though it looks like we have a modifier per-plane, we in fact do not. The\n modifier for each plane must be identical. Thus all combinations of\n different data layouts for multi-plane formats must be enumerated as\n separate modifiers.\n\n All of the entries in @handles, @pitches, @offsets and @modifier must be\n zero when unused. Warning, for @offsets and @modifier zero can't be used to\n figure out whether the entry is used or not since it's a valid value (a zero\n offset is common, and a zero modifier is &DRM_FORMAT_MOD_LINEAR)."]
2083#[repr(C)]
2084#[derive(Debug, Copy, Clone)]
2085pub struct drm_mode_fb_cmd2 {
2086 #[doc = " @fb_id: Object ID of the frame-buffer."]
2087 pub fb_id: __u32,
2088 #[doc = " @width: Width of the frame-buffer."]
2089 pub width: __u32,
2090 #[doc = " @height: Height of the frame-buffer."]
2091 pub height: __u32,
2092 #[doc = " @pixel_format: FourCC format code, see ``DRM_FORMAT_*`` constants in\n ``drm_fourcc.h``."]
2093 pub pixel_format: __u32,
2094 #[doc = " @flags: Frame-buffer flags (see &DRM_MODE_FB_INTERLACED and\n &DRM_MODE_FB_MODIFIERS)."]
2095 pub flags: __u32,
2096 #[doc = " @handles: GEM buffer handle, one per plane. Set to 0 if the plane is\n unused. The same handle can be used for multiple planes."]
2097 pub handles: [__u32; 4usize],
2098 #[doc = " @pitches: Pitch (aka. stride) in bytes, one per plane."]
2099 pub pitches: [__u32; 4usize],
2100 #[doc = " @offsets: Offset into the buffer in bytes, one per plane."]
2101 pub offsets: [__u32; 4usize],
2102 #[doc = " @modifier: Format modifier, one per plane. See ``DRM_FORMAT_MOD_*``\n constants in ``drm_fourcc.h``. All planes must use the same\n modifier. Ignored unless &DRM_MODE_FB_MODIFIERS is set in @flags."]
2103 pub modifier: [__u64; 4usize],
2104}
2105#[repr(C)]
2106#[derive(Debug, Copy, Clone)]
2107pub struct drm_mode_fb_dirty_cmd {
2108 pub fb_id: __u32,
2109 pub flags: __u32,
2110 pub color: __u32,
2111 pub num_clips: __u32,
2112 pub clips_ptr: __u64,
2113}
2114#[repr(C)]
2115#[derive(Debug, Copy, Clone)]
2116pub struct drm_mode_mode_cmd {
2117 pub connector_id: __u32,
2118 pub mode: drm_mode_modeinfo,
2119}
2120#[repr(C)]
2121#[derive(Debug, Copy, Clone)]
2122pub struct drm_mode_cursor {
2123 pub flags: __u32,
2124 pub crtc_id: __u32,
2125 pub x: __s32,
2126 pub y: __s32,
2127 pub width: __u32,
2128 pub height: __u32,
2129 pub handle: __u32,
2130}
2131#[repr(C)]
2132#[derive(Debug, Copy, Clone)]
2133pub struct drm_mode_cursor2 {
2134 pub flags: __u32,
2135 pub crtc_id: __u32,
2136 pub x: __s32,
2137 pub y: __s32,
2138 pub width: __u32,
2139 pub height: __u32,
2140 pub handle: __u32,
2141 pub hot_x: __s32,
2142 pub hot_y: __s32,
2143}
2144#[repr(C)]
2145#[derive(Debug, Copy, Clone)]
2146pub struct drm_mode_crtc_lut {
2147 pub crtc_id: __u32,
2148 pub gamma_size: __u32,
2149 pub red: __u64,
2150 pub green: __u64,
2151 pub blue: __u64,
2152}
2153#[repr(C)]
2154#[derive(Debug, Copy, Clone)]
2155pub struct drm_color_ctm {
2156 pub matrix: [__u64; 9usize],
2157}
2158#[repr(C)]
2159#[derive(Debug, Copy, Clone)]
2160pub struct drm_color_lut {
2161 pub red: __u16,
2162 pub green: __u16,
2163 pub blue: __u16,
2164 pub reserved: __u16,
2165}
2166#[doc = " struct drm_plane_size_hint - Plane size hints\n\n The plane SIZE_HINTS property blob contains an\n array of struct drm_plane_size_hint."]
2167#[repr(C)]
2168#[derive(Debug, Copy, Clone)]
2169pub struct drm_plane_size_hint {
2170 pub width: __u16,
2171 pub height: __u16,
2172}
2173#[doc = " struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.\n\n HDR Metadata Infoframe as per CTA 861.G spec. This is expected\n to match exactly with the spec.\n\n Userspace is expected to pass the metadata information as per\n the format described in this structure."]
2174#[repr(C)]
2175#[derive(Debug, Copy, Clone)]
2176pub struct hdr_metadata_infoframe {
2177 #[doc = " @eotf: Electro-Optical Transfer Function (EOTF)\n used in the stream."]
2178 pub eotf: __u8,
2179 #[doc = " @metadata_type: Static_Metadata_Descriptor_ID."]
2180 pub metadata_type: __u8,
2181 pub display_primaries: [hdr_metadata_infoframe__bindgen_ty_1; 3usize],
2182 pub white_point: hdr_metadata_infoframe__bindgen_ty_2,
2183 #[doc = " @max_display_mastering_luminance: Max Mastering Display Luminance.\n This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2."]
2184 pub max_display_mastering_luminance: __u16,
2185 #[doc = " @min_display_mastering_luminance: Min Mastering Display Luminance.\n This value is coded as an unsigned 16-bit value in units of\n 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF\n represents 6.5535 cd/m2."]
2186 pub min_display_mastering_luminance: __u16,
2187 #[doc = " @max_cll: Max Content Light Level.\n This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2."]
2188 pub max_cll: __u16,
2189 #[doc = " @max_fall: Max Frame Average Light Level.\n This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2."]
2190 pub max_fall: __u16,
2191}
2192#[doc = " @display_primaries: Color Primaries of the Data.\n These are coded as unsigned 16-bit values in units of\n 0.00002, where 0x0000 represents zero and 0xC350\n represents 1.0000.\n @display_primaries.x: X coordinate of color primary.\n @display_primaries.y: Y coordinate of color primary."]
2193#[repr(C)]
2194#[derive(Debug, Copy, Clone)]
2195pub struct hdr_metadata_infoframe__bindgen_ty_1 {
2196 pub x: __u16,
2197 pub y: __u16,
2198}
2199#[doc = " @white_point: White Point of Colorspace Data.\n These are coded as unsigned 16-bit values in units of\n 0.00002, where 0x0000 represents zero and 0xC350\n represents 1.0000.\n @white_point.x: X coordinate of whitepoint of color primary.\n @white_point.y: Y coordinate of whitepoint of color primary."]
2200#[repr(C)]
2201#[derive(Debug, Copy, Clone)]
2202pub struct hdr_metadata_infoframe__bindgen_ty_2 {
2203 pub x: __u16,
2204 pub y: __u16,
2205}
2206#[doc = " struct hdr_output_metadata - HDR output metadata\n\n Metadata Information to be passed from userspace"]
2207#[repr(C)]
2208#[derive(Copy, Clone)]
2209pub struct hdr_output_metadata {
2210 #[doc = " @metadata_type: Static_Metadata_Descriptor_ID."]
2211 pub metadata_type: __u32,
2212 pub __bindgen_anon_1: hdr_output_metadata__bindgen_ty_1,
2213}
2214#[doc = " @hdmi_metadata_type1: HDR Metadata Infoframe."]
2215#[repr(C)]
2216#[derive(Copy, Clone)]
2217pub union hdr_output_metadata__bindgen_ty_1 {
2218 pub hdmi_metadata_type1: hdr_metadata_infoframe,
2219}
2220#[repr(C)]
2221#[derive(Debug, Copy, Clone)]
2222pub struct drm_mode_crtc_page_flip {
2223 pub crtc_id: __u32,
2224 pub fb_id: __u32,
2225 pub flags: __u32,
2226 pub reserved: __u32,
2227 pub user_data: __u64,
2228}
2229#[repr(C)]
2230#[derive(Debug, Copy, Clone)]
2231pub struct drm_mode_crtc_page_flip_target {
2232 pub crtc_id: __u32,
2233 pub fb_id: __u32,
2234 pub flags: __u32,
2235 pub sequence: __u32,
2236 pub user_data: __u64,
2237}
2238#[doc = " struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.\n @height: buffer height in pixels\n @width: buffer width in pixels\n @bpp: bits per pixel\n @flags: must be zero\n @handle: buffer object handle\n @pitch: number of bytes between two consecutive lines\n @size: size of the whole buffer in bytes\n\n User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,\n the kernel fills @handle, @pitch and @size."]
2239#[repr(C)]
2240#[derive(Debug, Copy, Clone)]
2241pub struct drm_mode_create_dumb {
2242 pub height: __u32,
2243 pub width: __u32,
2244 pub bpp: __u32,
2245 pub flags: __u32,
2246 pub handle: __u32,
2247 pub pitch: __u32,
2248 pub size: __u64,
2249}
2250#[repr(C)]
2251#[derive(Debug, Copy, Clone)]
2252pub struct drm_mode_map_dumb {
2253 #[doc = " Handle for the object being mapped."]
2254 pub handle: __u32,
2255 pub pad: __u32,
2256 #[doc = " Fake offset to use for subsequent mmap call\n\n This is a fixed-size type for 32/64 compatibility."]
2257 pub offset: __u64,
2258}
2259#[repr(C)]
2260#[derive(Debug, Copy, Clone)]
2261pub struct drm_mode_destroy_dumb {
2262 pub handle: __u32,
2263}
2264#[repr(C)]
2265#[derive(Debug, Copy, Clone)]
2266pub struct drm_mode_atomic {
2267 pub flags: __u32,
2268 pub count_objs: __u32,
2269 pub objs_ptr: __u64,
2270 pub count_props_ptr: __u64,
2271 pub props_ptr: __u64,
2272 pub prop_values_ptr: __u64,
2273 pub reserved: __u64,
2274 pub user_data: __u64,
2275}
2276#[repr(C)]
2277#[derive(Debug, Copy, Clone)]
2278pub struct drm_format_modifier_blob {
2279 pub version: __u32,
2280 pub flags: __u32,
2281 pub count_formats: __u32,
2282 pub formats_offset: __u32,
2283 pub count_modifiers: __u32,
2284 pub modifiers_offset: __u32,
2285}
2286#[repr(C)]
2287#[derive(Debug, Copy, Clone)]
2288pub struct drm_format_modifier {
2289 pub formats: __u64,
2290 pub offset: __u32,
2291 pub pad: __u32,
2292 pub modifier: __u64,
2293}
2294#[doc = " struct drm_mode_create_blob - Create New blob property\n\n Create a new 'blob' data property, copying length bytes from data pointer,\n and returning new blob ID."]
2295#[repr(C)]
2296#[derive(Debug, Copy, Clone)]
2297pub struct drm_mode_create_blob {
2298 #[doc = " @data: Pointer to data to copy."]
2299 pub data: __u64,
2300 #[doc = " @length: Length of data to copy."]
2301 pub length: __u32,
2302 #[doc = " @blob_id: Return: new property ID."]
2303 pub blob_id: __u32,
2304}
2305#[doc = " struct drm_mode_destroy_blob - Destroy user blob\n @blob_id: blob_id to destroy\n\n Destroy a user-created blob property.\n\n User-space can release blobs as soon as they do not need to refer to them by\n their blob object ID. For instance, if you are using a MODE_ID blob in an\n atomic commit and you will not make another commit re-using the same ID, you\n can destroy the blob as soon as the commit has been issued, without waiting\n for it to complete."]
2306#[repr(C)]
2307#[derive(Debug, Copy, Clone)]
2308pub struct drm_mode_destroy_blob {
2309 pub blob_id: __u32,
2310}
2311#[doc = " struct drm_mode_create_lease - Create lease\n\n Lease mode resources, creating another drm_master.\n\n The @object_ids array must reference at least one CRTC, one connector and\n one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,\n the lease can be completely empty."]
2312#[repr(C)]
2313#[derive(Debug, Copy, Clone)]
2314pub struct drm_mode_create_lease {
2315 #[doc = " @object_ids: Pointer to array of object ids (__u32)"]
2316 pub object_ids: __u64,
2317 #[doc = " @object_count: Number of object ids"]
2318 pub object_count: __u32,
2319 #[doc = " @flags: flags for new FD (O_CLOEXEC, etc)"]
2320 pub flags: __u32,
2321 #[doc = " @lessee_id: Return: unique identifier for lessee."]
2322 pub lessee_id: __u32,
2323 #[doc = " @fd: Return: file descriptor to new drm_master file"]
2324 pub fd: __u32,
2325}
2326#[doc = " struct drm_mode_list_lessees - List lessees\n\n List lesses from a drm_master."]
2327#[repr(C)]
2328#[derive(Debug, Copy, Clone)]
2329pub struct drm_mode_list_lessees {
2330 #[doc = " @count_lessees: Number of lessees.\n\n On input, provides length of the array.\n On output, provides total number. No\n more than the input number will be written\n back, so two calls can be used to get\n the size and then the data."]
2331 pub count_lessees: __u32,
2332 #[doc = " @pad: Padding."]
2333 pub pad: __u32,
2334 #[doc = " @lessees_ptr: Pointer to lessees.\n\n Pointer to __u64 array of lessee ids"]
2335 pub lessees_ptr: __u64,
2336}
2337#[doc = " struct drm_mode_get_lease - Get Lease\n\n Get leased objects."]
2338#[repr(C)]
2339#[derive(Debug, Copy, Clone)]
2340pub struct drm_mode_get_lease {
2341 #[doc = " @count_objects: Number of leased objects.\n\n On input, provides length of the array.\n On output, provides total number. No\n more than the input number will be written\n back, so two calls can be used to get\n the size and then the data."]
2342 pub count_objects: __u32,
2343 #[doc = " @pad: Padding."]
2344 pub pad: __u32,
2345 #[doc = " @objects_ptr: Pointer to objects.\n\n Pointer to __u32 array of object ids."]
2346 pub objects_ptr: __u64,
2347}
2348#[doc = " struct drm_mode_revoke_lease - Revoke lease"]
2349#[repr(C)]
2350#[derive(Debug, Copy, Clone)]
2351pub struct drm_mode_revoke_lease {
2352 #[doc = " @lessee_id: Unique ID of lessee"]
2353 pub lessee_id: __u32,
2354}
2355#[doc = " struct drm_mode_rect - Two dimensional rectangle.\n @x1: Horizontal starting coordinate (inclusive).\n @y1: Vertical starting coordinate (inclusive).\n @x2: Horizontal ending coordinate (exclusive).\n @y2: Vertical ending coordinate (exclusive).\n\n With drm subsystem using struct drm_rect to manage rectangular area this\n export it to user-space.\n\n Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS."]
2356#[repr(C)]
2357#[derive(Debug, Copy, Clone)]
2358pub struct drm_mode_rect {
2359 pub x1: __s32,
2360 pub y1: __s32,
2361 pub x2: __s32,
2362 pub y2: __s32,
2363}
2364#[doc = " struct drm_mode_closefb\n @fb_id: Framebuffer ID.\n @pad: Must be zero."]
2365#[repr(C)]
2366#[derive(Debug, Copy, Clone)]
2367pub struct drm_mode_closefb {
2368 pub fb_id: __u32,
2369 pub pad: __u32,
2370}
2371#[doc = " struct drm_event - Header for DRM events\n @type: event type.\n @length: total number of payload bytes (including header).\n\n This struct is a header for events written back to user-space on the DRM FD.\n A read on the DRM FD will always only return complete events: e.g. if the\n read buffer is 100 bytes large and there are two 64 byte events pending,\n only one will be returned.\n\n Event types 0 - 0x7fffffff are generic DRM events, 0x80000000 and\n up are chipset specific. Generic DRM events include &DRM_EVENT_VBLANK,\n &DRM_EVENT_FLIP_COMPLETE and &DRM_EVENT_CRTC_SEQUENCE."]
2372#[repr(C)]
2373#[derive(Debug, Copy, Clone)]
2374pub struct drm_event {
2375 pub type_: __u32,
2376 pub length: __u32,
2377}
2378#[repr(C)]
2379#[derive(Debug, Copy, Clone)]
2380pub struct drm_event_vblank {
2381 pub base: drm_event,
2382 pub user_data: __u64,
2383 pub tv_sec: __u32,
2384 pub tv_usec: __u32,
2385 pub sequence: __u32,
2386 pub crtc_id: __u32,
2387}
2388#[repr(C)]
2389#[derive(Debug, Copy, Clone)]
2390pub struct drm_event_crtc_sequence {
2391 pub base: drm_event,
2392 pub user_data: __u64,
2393 pub time_ns: __s64,
2394 pub sequence: __u64,
2395}
2396pub type drm_clip_rect_t = drm_clip_rect;
2397pub type drm_drawable_info_t = drm_drawable_info;
2398pub type drm_tex_region_t = drm_tex_region;
2399pub type drm_hw_lock_t = drm_hw_lock;
2400pub type drm_version_t = drm_version;
2401pub type drm_unique_t = drm_unique;
2402pub type drm_list_t = drm_list;
2403pub type drm_block_t = drm_block;
2404pub type drm_control_t = drm_control;
2405pub use self::drm_map_flags as drm_map_flags_t;
2406pub use self::drm_map_type as drm_map_type_t;
2407pub type drm_ctx_priv_map_t = drm_ctx_priv_map;
2408pub type drm_map_t = drm_map;
2409pub type drm_client_t = drm_client;
2410pub use self::drm_stat_type as drm_stat_type_t;
2411pub type drm_stats_t = drm_stats;
2412pub use self::drm_lock_flags as drm_lock_flags_t;
2413pub type drm_lock_t = drm_lock;
2414pub use self::drm_dma_flags as drm_dma_flags_t;
2415pub type drm_buf_desc_t = drm_buf_desc;
2416pub type drm_buf_info_t = drm_buf_info;
2417pub type drm_buf_free_t = drm_buf_free;
2418pub type drm_buf_pub_t = drm_buf_pub;
2419pub type drm_buf_map_t = drm_buf_map;
2420pub type drm_dma_t = drm_dma;
2421pub type drm_wait_vblank_t = drm_wait_vblank;
2422pub type drm_agp_mode_t = drm_agp_mode;
2423pub use self::drm_ctx_flags as drm_ctx_flags_t;
2424pub type drm_ctx_t = drm_ctx;
2425pub type drm_ctx_res_t = drm_ctx_res;
2426pub type drm_draw_t = drm_draw;
2427pub type drm_update_draw_t = drm_update_draw;
2428pub type drm_auth_t = drm_auth;
2429pub type drm_irq_busid_t = drm_irq_busid;
2430pub use self::drm_vblank_seq_type as drm_vblank_seq_type_t;
2431pub type drm_agp_buffer_t = drm_agp_buffer;
2432pub type drm_agp_binding_t = drm_agp_binding;
2433pub type drm_agp_info_t = drm_agp_info;
2434pub type drm_scatter_gather_t = drm_scatter_gather;
2435pub type drm_set_version_t = drm_set_version;
2436pub type drmSize = ::core::ffi::c_uint;
2437pub type drmSizePtr = *mut ::core::ffi::c_uint;
2438pub type drmAddress = *mut ::core::ffi::c_void;
2439pub type drmAddressPtr = *mut *mut ::core::ffi::c_void;
2440#[repr(C)]
2441#[derive(Debug, Copy, Clone)]
2442pub struct _drmServerInfo {
2443 pub debug_print: ::core::option::Option<
2444 unsafe extern "C" fn(
2445 format: *const ::core::ffi::c_char,
2446 ap: *mut __va_list_tag,
2447 ) -> ::core::ffi::c_int,
2448 >,
2449 pub load_module: ::core::option::Option<
2450 unsafe extern "C" fn(name: *const ::core::ffi::c_char) -> ::core::ffi::c_int,
2451 >,
2452 pub get_perms:
2453 ::core::option::Option<unsafe extern "C" fn(arg1: *mut gid_t, arg2: *mut mode_t)>,
2454}
2455pub type drmServerInfo = _drmServerInfo;
2456pub type drmServerInfoPtr = *mut _drmServerInfo;
2457#[repr(C)]
2458#[derive(Debug, Copy, Clone)]
2459pub struct drmHashEntry {
2460 pub fd: ::core::ffi::c_int,
2461 pub f: ::core::option::Option<
2462 unsafe extern "C" fn(
2463 arg1: ::core::ffi::c_int,
2464 arg2: *mut ::core::ffi::c_void,
2465 arg3: *mut ::core::ffi::c_void,
2466 ),
2467 >,
2468 pub tagTable: *mut ::core::ffi::c_void,
2469}
2470unsafe extern "C" {
2471 pub fn drmIoctl(
2472 fd: ::core::ffi::c_int,
2473 request: ::core::ffi::c_ulong,
2474 arg: *mut ::core::ffi::c_void,
2475 ) -> ::core::ffi::c_int;
2476}
2477unsafe extern "C" {
2478 pub fn drmGetHashTable() -> *mut ::core::ffi::c_void;
2479}
2480unsafe extern "C" {
2481 pub fn drmGetEntry(fd: ::core::ffi::c_int) -> *mut drmHashEntry;
2482}
2483#[doc = " Driver version information.\n\n \\sa drmGetVersion() and drmSetVersion()."]
2484#[repr(C)]
2485#[derive(Debug, Copy, Clone)]
2486pub struct _drmVersion {
2487 #[doc = "< Major version"]
2488 pub version_major: ::core::ffi::c_int,
2489 #[doc = "< Minor version"]
2490 pub version_minor: ::core::ffi::c_int,
2491 #[doc = "< Patch level"]
2492 pub version_patchlevel: ::core::ffi::c_int,
2493 #[doc = "< Length of name buffer"]
2494 pub name_len: ::core::ffi::c_int,
2495 #[doc = "< Name of driver"]
2496 pub name: *mut ::core::ffi::c_char,
2497 #[doc = "< Length of date buffer"]
2498 pub date_len: ::core::ffi::c_int,
2499 #[doc = "< User-space buffer to hold date"]
2500 pub date: *mut ::core::ffi::c_char,
2501 #[doc = "< Length of desc buffer"]
2502 pub desc_len: ::core::ffi::c_int,
2503 #[doc = "< User-space buffer to hold desc"]
2504 pub desc: *mut ::core::ffi::c_char,
2505}
2506#[doc = " Driver version information.\n\n \\sa drmGetVersion() and drmSetVersion()."]
2507pub type drmVersion = _drmVersion;
2508#[doc = " Driver version information.\n\n \\sa drmGetVersion() and drmSetVersion()."]
2509pub type drmVersionPtr = *mut _drmVersion;
2510#[repr(C)]
2511#[derive(Debug, Copy, Clone)]
2512pub struct _drmStats {
2513 #[doc = "< Number of data"]
2514 pub count: ::core::ffi::c_ulong,
2515 pub data: [_drmStats__bindgen_ty_1; 15usize],
2516}
2517#[repr(C)]
2518#[derive(Debug, Copy, Clone)]
2519pub struct _drmStats__bindgen_ty_1 {
2520 #[doc = "< Value from kernel"]
2521 pub value: ::core::ffi::c_ulong,
2522 #[doc = "< Suggested format for long_name"]
2523 pub long_format: *const ::core::ffi::c_char,
2524 #[doc = "< Long name for value"]
2525 pub long_name: *const ::core::ffi::c_char,
2526 #[doc = "< Suggested format for rate_name"]
2527 pub rate_format: *const ::core::ffi::c_char,
2528 #[doc = "< Short name for value per second"]
2529 pub rate_name: *const ::core::ffi::c_char,
2530 #[doc = "< True if value (vs. counter)"]
2531 pub isvalue: ::core::ffi::c_int,
2532 #[doc = "< Multiplier names (e.g., \"KGM\")"]
2533 pub mult_names: *const ::core::ffi::c_char,
2534 #[doc = "< Multiplier value (e.g., 1024)"]
2535 pub mult: ::core::ffi::c_int,
2536 #[doc = "< Suggest only in verbose output"]
2537 pub verbose: ::core::ffi::c_int,
2538}
2539pub type drmStatsT = _drmStats;
2540#[doc = "< WC, no caching, no core dump"]
2541pub const drmMapType_DRM_FRAME_BUFFER: drmMapType = 0;
2542#[doc = "< no caching, no core dump"]
2543pub const drmMapType_DRM_REGISTERS: drmMapType = 1;
2544#[doc = "< shared, cached"]
2545pub const drmMapType_DRM_SHM: drmMapType = 2;
2546#[doc = "< AGP/GART"]
2547pub const drmMapType_DRM_AGP: drmMapType = 3;
2548#[doc = "< PCI scatter/gather"]
2549pub const drmMapType_DRM_SCATTER_GATHER: drmMapType = 4;
2550#[doc = "< PCI consistent"]
2551pub const drmMapType_DRM_CONSISTENT: drmMapType = 5;
2552pub type drmMapType = ::core::ffi::c_uint;
2553#[doc = "< Cannot be mapped to client-virtual"]
2554pub const drmMapFlags_DRM_RESTRICTED: drmMapFlags = 1;
2555#[doc = "< Read-only in client-virtual"]
2556pub const drmMapFlags_DRM_READ_ONLY: drmMapFlags = 2;
2557#[doc = "< Physical pages locked"]
2558pub const drmMapFlags_DRM_LOCKED: drmMapFlags = 4;
2559#[doc = "< Kernel requires access"]
2560pub const drmMapFlags_DRM_KERNEL: drmMapFlags = 8;
2561#[doc = "< Use write-combining, if available"]
2562pub const drmMapFlags_DRM_WRITE_COMBINING: drmMapFlags = 16;
2563#[doc = "< SHM page that contains lock"]
2564pub const drmMapFlags_DRM_CONTAINS_LOCK: drmMapFlags = 32;
2565#[doc = "< Removable mapping"]
2566pub const drmMapFlags_DRM_REMOVABLE: drmMapFlags = 64;
2567pub type drmMapFlags = ::core::ffi::c_uint;
2568#[doc = "<\n Block until buffer dispatched.\n\n \\note the buffer may not yet have been\n processed by the hardware -- getting a\n hardware lock with the hardware quiescent\n will ensure that the buffer has been\n processed."]
2569pub const drmDMAFlags_DRM_DMA_BLOCK: drmDMAFlags = 1;
2570#[doc = "< Dispatch while lock held"]
2571pub const drmDMAFlags_DRM_DMA_WHILE_LOCKED: drmDMAFlags = 2;
2572#[doc = "< High priority dispatch"]
2573pub const drmDMAFlags_DRM_DMA_PRIORITY: drmDMAFlags = 4;
2574#[doc = "< Wait for free buffers"]
2575pub const drmDMAFlags_DRM_DMA_WAIT: drmDMAFlags = 16;
2576#[doc = "< Smaller-than-requested buffers OK"]
2577pub const drmDMAFlags_DRM_DMA_SMALLER_OK: drmDMAFlags = 32;
2578#[doc = "< Larger-than-requested buffers OK"]
2579pub const drmDMAFlags_DRM_DMA_LARGER_OK: drmDMAFlags = 64;
2580#[doc = " \\warning These values *MUST* match drm.h"]
2581pub type drmDMAFlags = ::core::ffi::c_uint;
2582pub const drmBufDescFlags_DRM_PAGE_ALIGN: drmBufDescFlags = 1;
2583pub const drmBufDescFlags_DRM_AGP_BUFFER: drmBufDescFlags = 2;
2584pub const drmBufDescFlags_DRM_SG_BUFFER: drmBufDescFlags = 4;
2585pub const drmBufDescFlags_DRM_FB_BUFFER: drmBufDescFlags = 8;
2586pub const drmBufDescFlags_DRM_PCI_BUFFER_RO: drmBufDescFlags = 16;
2587pub type drmBufDescFlags = ::core::ffi::c_uint;
2588#[doc = "< Wait until hardware is ready for DMA"]
2589pub const drmLockFlags_DRM_LOCK_READY: drmLockFlags = 1;
2590#[doc = "< Wait until hardware quiescent"]
2591pub const drmLockFlags_DRM_LOCK_QUIESCENT: drmLockFlags = 2;
2592#[doc = "< Flush this context's DMA queue first"]
2593pub const drmLockFlags_DRM_LOCK_FLUSH: drmLockFlags = 4;
2594#[doc = "< Flush all DMA queues first"]
2595pub const drmLockFlags_DRM_LOCK_FLUSH_ALL: drmLockFlags = 8;
2596#[doc = "< Halt all current and future queues"]
2597pub const drmLockFlags_DRM_HALT_ALL_QUEUES: drmLockFlags = 16;
2598#[doc = "< Halt all current queues"]
2599pub const drmLockFlags_DRM_HALT_CUR_QUEUES: drmLockFlags = 32;
2600pub type drmLockFlags = ::core::ffi::c_uint;
2601#[doc = "< This context is preserved and\nnever swapped."]
2602pub const drm_context_tFlags_DRM_CONTEXT_PRESERVED: drm_context_tFlags = 1;
2603#[doc = "< This context is for 2D rendering only."]
2604pub const drm_context_tFlags_DRM_CONTEXT_2DONLY: drm_context_tFlags = 2;
2605pub type drm_context_tFlags = ::core::ffi::c_uint;
2606pub type drm_context_tFlagsPtr = *mut drm_context_tFlags;
2607#[repr(C)]
2608#[derive(Debug, Copy, Clone)]
2609pub struct _drmBufDesc {
2610 #[doc = "< Number of buffers of this size"]
2611 pub count: ::core::ffi::c_int,
2612 #[doc = "< Size in bytes"]
2613 pub size: ::core::ffi::c_int,
2614 #[doc = "< Low water mark"]
2615 pub low_mark: ::core::ffi::c_int,
2616 #[doc = "< High water mark"]
2617 pub high_mark: ::core::ffi::c_int,
2618}
2619pub type drmBufDesc = _drmBufDesc;
2620pub type drmBufDescPtr = *mut _drmBufDesc;
2621#[repr(C)]
2622#[derive(Debug, Copy, Clone)]
2623pub struct _drmBufInfo {
2624 #[doc = "< Number of buffers described in list"]
2625 pub count: ::core::ffi::c_int,
2626 #[doc = "< List of buffer descriptions"]
2627 pub list: drmBufDescPtr,
2628}
2629pub type drmBufInfo = _drmBufInfo;
2630pub type drmBufInfoPtr = *mut _drmBufInfo;
2631#[repr(C)]
2632#[derive(Debug, Copy, Clone)]
2633pub struct _drmBuf {
2634 #[doc = "< Index into the master buffer list"]
2635 pub idx: ::core::ffi::c_int,
2636 #[doc = "< Buffer size"]
2637 pub total: ::core::ffi::c_int,
2638 #[doc = "< Amount of buffer in use (for DMA)"]
2639 pub used: ::core::ffi::c_int,
2640 #[doc = "< Address"]
2641 pub address: drmAddress,
2642}
2643pub type drmBuf = _drmBuf;
2644pub type drmBufPtr = *mut _drmBuf;
2645#[doc = " Buffer mapping information.\n\n Used by drmMapBufs() and drmUnmapBufs() to store information about the\n mapped buffers."]
2646#[repr(C)]
2647#[derive(Debug, Copy, Clone)]
2648pub struct _drmBufMap {
2649 #[doc = "< Number of buffers mapped"]
2650 pub count: ::core::ffi::c_int,
2651 #[doc = "< Buffers"]
2652 pub list: drmBufPtr,
2653}
2654#[doc = " Buffer mapping information.\n\n Used by drmMapBufs() and drmUnmapBufs() to store information about the\n mapped buffers."]
2655pub type drmBufMap = _drmBufMap;
2656#[doc = " Buffer mapping information.\n\n Used by drmMapBufs() and drmUnmapBufs() to store information about the\n mapped buffers."]
2657pub type drmBufMapPtr = *mut _drmBufMap;
2658#[repr(C)]
2659#[derive(Debug, Copy, Clone)]
2660pub struct _drmLock {
2661 pub lock: ::core::ffi::c_uint,
2662 pub padding: [::core::ffi::c_char; 60usize],
2663}
2664pub type drmLock = _drmLock;
2665pub type drmLockPtr = *mut _drmLock;
2666#[doc = " Indices here refer to the offset into\n list in drmBufInfo"]
2667#[repr(C)]
2668#[derive(Debug, Copy, Clone)]
2669pub struct _drmDMAReq {
2670 #[doc = "< Context handle"]
2671 pub context: drm_context_t,
2672 #[doc = "< Number of buffers to send"]
2673 pub send_count: ::core::ffi::c_int,
2674 #[doc = "< List of handles to buffers"]
2675 pub send_list: *mut ::core::ffi::c_int,
2676 #[doc = "< Lengths of data to send, in bytes"]
2677 pub send_sizes: *mut ::core::ffi::c_int,
2678 #[doc = "< Flags"]
2679 pub flags: drmDMAFlags,
2680 #[doc = "< Number of buffers requested"]
2681 pub request_count: ::core::ffi::c_int,
2682 #[doc = "< Desired size of buffers requested"]
2683 pub request_size: ::core::ffi::c_int,
2684 #[doc = "< Buffer information"]
2685 pub request_list: *mut ::core::ffi::c_int,
2686 #[doc = "< Minimum acceptable sizes"]
2687 pub request_sizes: *mut ::core::ffi::c_int,
2688 #[doc = "< Number of buffers granted at this size"]
2689 pub granted_count: ::core::ffi::c_int,
2690}
2691#[doc = " Indices here refer to the offset into\n list in drmBufInfo"]
2692pub type drmDMAReq = _drmDMAReq;
2693#[doc = " Indices here refer to the offset into\n list in drmBufInfo"]
2694pub type drmDMAReqPtr = *mut _drmDMAReq;
2695#[repr(C)]
2696#[derive(Debug, Copy, Clone)]
2697pub struct _drmRegion {
2698 pub handle: drm_handle_t,
2699 pub offset: ::core::ffi::c_uint,
2700 pub size: drmSize,
2701 pub map: drmAddress,
2702}
2703pub type drmRegion = _drmRegion;
2704pub type drmRegionPtr = *mut _drmRegion;
2705#[repr(C)]
2706#[derive(Debug, Copy, Clone)]
2707pub struct _drmTextureRegion {
2708 pub next: ::core::ffi::c_uchar,
2709 pub prev: ::core::ffi::c_uchar,
2710 pub in_use: ::core::ffi::c_uchar,
2711 #[doc = "< Explicitly pad this out"]
2712 pub padding: ::core::ffi::c_uchar,
2713 pub age: ::core::ffi::c_uint,
2714}
2715pub type drmTextureRegion = _drmTextureRegion;
2716pub type drmTextureRegionPtr = *mut _drmTextureRegion;
2717#[doc = "< Wait for specific vblank sequence number"]
2718pub const drmVBlankSeqType_DRM_VBLANK_ABSOLUTE: drmVBlankSeqType = 0;
2719#[doc = "< Wait for given number of vblanks"]
2720pub const drmVBlankSeqType_DRM_VBLANK_RELATIVE: drmVBlankSeqType = 1;
2721pub const drmVBlankSeqType_DRM_VBLANK_HIGH_CRTC_MASK: drmVBlankSeqType = 62;
2722#[doc = "< Send event instead of blocking"]
2723pub const drmVBlankSeqType_DRM_VBLANK_EVENT: drmVBlankSeqType = 67108864;
2724#[doc = "< Scheduled buffer swap should flip"]
2725pub const drmVBlankSeqType_DRM_VBLANK_FLIP: drmVBlankSeqType = 134217728;
2726#[doc = "< If missed, wait for next vblank"]
2727pub const drmVBlankSeqType_DRM_VBLANK_NEXTONMISS: drmVBlankSeqType = 268435456;
2728#[doc = "< Secondary display controller"]
2729pub const drmVBlankSeqType_DRM_VBLANK_SECONDARY: drmVBlankSeqType = 536870912;
2730pub const drmVBlankSeqType_DRM_VBLANK_SIGNAL: drmVBlankSeqType = 1073741824;
2731pub type drmVBlankSeqType = ::core::ffi::c_uint;
2732#[repr(C)]
2733#[derive(Debug, Copy, Clone)]
2734pub struct _drmVBlankReq {
2735 pub type_: drmVBlankSeqType,
2736 pub sequence: ::core::ffi::c_uint,
2737 pub signal: ::core::ffi::c_ulong,
2738}
2739pub type drmVBlankReq = _drmVBlankReq;
2740pub type drmVBlankReqPtr = *mut _drmVBlankReq;
2741#[repr(C)]
2742#[derive(Debug, Copy, Clone)]
2743pub struct _drmVBlankReply {
2744 pub type_: drmVBlankSeqType,
2745 pub sequence: ::core::ffi::c_uint,
2746 pub tval_sec: ::core::ffi::c_long,
2747 pub tval_usec: ::core::ffi::c_long,
2748}
2749pub type drmVBlankReply = _drmVBlankReply;
2750pub type drmVBlankReplyPtr = *mut _drmVBlankReply;
2751#[repr(C)]
2752#[derive(Copy, Clone)]
2753pub union _drmVBlank {
2754 pub request: drmVBlankReq,
2755 pub reply: drmVBlankReply,
2756}
2757pub type drmVBlank = _drmVBlank;
2758pub type drmVBlankPtr = *mut _drmVBlank;
2759#[repr(C)]
2760#[derive(Debug, Copy, Clone)]
2761pub struct _drmSetVersion {
2762 pub drm_di_major: ::core::ffi::c_int,
2763 pub drm_di_minor: ::core::ffi::c_int,
2764 pub drm_dd_major: ::core::ffi::c_int,
2765 pub drm_dd_minor: ::core::ffi::c_int,
2766}
2767pub type drmSetVersion = _drmSetVersion;
2768pub type drmSetVersionPtr = *mut _drmSetVersion;
2769unsafe extern "C" {
2770 pub fn drmAvailable() -> ::core::ffi::c_int;
2771}
2772unsafe extern "C" {
2773 pub fn drmOpen(
2774 name: *const ::core::ffi::c_char,
2775 busid: *const ::core::ffi::c_char,
2776 ) -> ::core::ffi::c_int;
2777}
2778unsafe extern "C" {
2779 pub fn drmOpenWithType(
2780 name: *const ::core::ffi::c_char,
2781 busid: *const ::core::ffi::c_char,
2782 type_: ::core::ffi::c_int,
2783 ) -> ::core::ffi::c_int;
2784}
2785unsafe extern "C" {
2786 pub fn drmOpenControl(minor: ::core::ffi::c_int) -> ::core::ffi::c_int;
2787}
2788unsafe extern "C" {
2789 pub fn drmOpenRender(minor: ::core::ffi::c_int) -> ::core::ffi::c_int;
2790}
2791unsafe extern "C" {
2792 pub fn drmClose(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2793}
2794unsafe extern "C" {
2795 pub fn drmGetVersion(fd: ::core::ffi::c_int) -> drmVersionPtr;
2796}
2797unsafe extern "C" {
2798 pub fn drmGetLibVersion(fd: ::core::ffi::c_int) -> drmVersionPtr;
2799}
2800unsafe extern "C" {
2801 pub fn drmGetCap(
2802 fd: ::core::ffi::c_int,
2803 capability: u64,
2804 value: *mut u64,
2805 ) -> ::core::ffi::c_int;
2806}
2807unsafe extern "C" {
2808 pub fn drmFreeVersion(arg1: drmVersionPtr);
2809}
2810unsafe extern "C" {
2811 pub fn drmGetMagic(fd: ::core::ffi::c_int, magic: *mut drm_magic_t) -> ::core::ffi::c_int;
2812}
2813unsafe extern "C" {
2814 pub fn drmGetBusid(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
2815}
2816unsafe extern "C" {
2817 pub fn drmGetInterruptFromBusID(
2818 fd: ::core::ffi::c_int,
2819 busnum: ::core::ffi::c_int,
2820 devnum: ::core::ffi::c_int,
2821 funcnum: ::core::ffi::c_int,
2822 ) -> ::core::ffi::c_int;
2823}
2824unsafe extern "C" {
2825 pub fn drmGetMap(
2826 fd: ::core::ffi::c_int,
2827 idx: ::core::ffi::c_int,
2828 offset: *mut drm_handle_t,
2829 size: *mut drmSize,
2830 type_: *mut drmMapType,
2831 flags: *mut drmMapFlags,
2832 handle: *mut drm_handle_t,
2833 mtrr: *mut ::core::ffi::c_int,
2834 ) -> ::core::ffi::c_int;
2835}
2836unsafe extern "C" {
2837 pub fn drmGetClient(
2838 fd: ::core::ffi::c_int,
2839 idx: ::core::ffi::c_int,
2840 auth: *mut ::core::ffi::c_int,
2841 pid: *mut ::core::ffi::c_int,
2842 uid: *mut ::core::ffi::c_int,
2843 magic: *mut ::core::ffi::c_ulong,
2844 iocs: *mut ::core::ffi::c_ulong,
2845 ) -> ::core::ffi::c_int;
2846}
2847unsafe extern "C" {
2848 pub fn drmGetStats(fd: ::core::ffi::c_int, stats: *mut drmStatsT) -> ::core::ffi::c_int;
2849}
2850unsafe extern "C" {
2851 pub fn drmSetInterfaceVersion(
2852 fd: ::core::ffi::c_int,
2853 version: *mut drmSetVersion,
2854 ) -> ::core::ffi::c_int;
2855}
2856unsafe extern "C" {
2857 pub fn drmCommandNone(
2858 fd: ::core::ffi::c_int,
2859 drmCommandIndex: ::core::ffi::c_ulong,
2860 ) -> ::core::ffi::c_int;
2861}
2862unsafe extern "C" {
2863 pub fn drmCommandRead(
2864 fd: ::core::ffi::c_int,
2865 drmCommandIndex: ::core::ffi::c_ulong,
2866 data: *mut ::core::ffi::c_void,
2867 size: ::core::ffi::c_ulong,
2868 ) -> ::core::ffi::c_int;
2869}
2870unsafe extern "C" {
2871 pub fn drmCommandWrite(
2872 fd: ::core::ffi::c_int,
2873 drmCommandIndex: ::core::ffi::c_ulong,
2874 data: *mut ::core::ffi::c_void,
2875 size: ::core::ffi::c_ulong,
2876 ) -> ::core::ffi::c_int;
2877}
2878unsafe extern "C" {
2879 pub fn drmCommandWriteRead(
2880 fd: ::core::ffi::c_int,
2881 drmCommandIndex: ::core::ffi::c_ulong,
2882 data: *mut ::core::ffi::c_void,
2883 size: ::core::ffi::c_ulong,
2884 ) -> ::core::ffi::c_int;
2885}
2886unsafe extern "C" {
2887 pub fn drmFreeBusid(busid: *const ::core::ffi::c_char);
2888}
2889unsafe extern "C" {
2890 pub fn drmSetBusid(
2891 fd: ::core::ffi::c_int,
2892 busid: *const ::core::ffi::c_char,
2893 ) -> ::core::ffi::c_int;
2894}
2895unsafe extern "C" {
2896 pub fn drmAuthMagic(fd: ::core::ffi::c_int, magic: drm_magic_t) -> ::core::ffi::c_int;
2897}
2898unsafe extern "C" {
2899 pub fn drmAddMap(
2900 fd: ::core::ffi::c_int,
2901 offset: drm_handle_t,
2902 size: drmSize,
2903 type_: drmMapType,
2904 flags: drmMapFlags,
2905 handle: *mut drm_handle_t,
2906 ) -> ::core::ffi::c_int;
2907}
2908unsafe extern "C" {
2909 pub fn drmRmMap(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
2910}
2911unsafe extern "C" {
2912 pub fn drmAddContextPrivateMapping(
2913 fd: ::core::ffi::c_int,
2914 ctx_id: drm_context_t,
2915 handle: drm_handle_t,
2916 ) -> ::core::ffi::c_int;
2917}
2918unsafe extern "C" {
2919 pub fn drmAddBufs(
2920 fd: ::core::ffi::c_int,
2921 count: ::core::ffi::c_int,
2922 size: ::core::ffi::c_int,
2923 flags: drmBufDescFlags,
2924 agp_offset: ::core::ffi::c_int,
2925 ) -> ::core::ffi::c_int;
2926}
2927unsafe extern "C" {
2928 pub fn drmMarkBufs(fd: ::core::ffi::c_int, low: f64, high: f64) -> ::core::ffi::c_int;
2929}
2930unsafe extern "C" {
2931 pub fn drmCreateContext(
2932 fd: ::core::ffi::c_int,
2933 handle: *mut drm_context_t,
2934 ) -> ::core::ffi::c_int;
2935}
2936unsafe extern "C" {
2937 pub fn drmSetContextFlags(
2938 fd: ::core::ffi::c_int,
2939 context: drm_context_t,
2940 flags: drm_context_tFlags,
2941 ) -> ::core::ffi::c_int;
2942}
2943unsafe extern "C" {
2944 pub fn drmGetContextFlags(
2945 fd: ::core::ffi::c_int,
2946 context: drm_context_t,
2947 flags: drm_context_tFlagsPtr,
2948 ) -> ::core::ffi::c_int;
2949}
2950unsafe extern "C" {
2951 pub fn drmAddContextTag(
2952 fd: ::core::ffi::c_int,
2953 context: drm_context_t,
2954 tag: *mut ::core::ffi::c_void,
2955 ) -> ::core::ffi::c_int;
2956}
2957unsafe extern "C" {
2958 pub fn drmDelContextTag(fd: ::core::ffi::c_int, context: drm_context_t) -> ::core::ffi::c_int;
2959}
2960unsafe extern "C" {
2961 pub fn drmGetContextTag(
2962 fd: ::core::ffi::c_int,
2963 context: drm_context_t,
2964 ) -> *mut ::core::ffi::c_void;
2965}
2966unsafe extern "C" {
2967 pub fn drmGetReservedContextList(
2968 fd: ::core::ffi::c_int,
2969 count: *mut ::core::ffi::c_int,
2970 ) -> *mut drm_context_t;
2971}
2972unsafe extern "C" {
2973 pub fn drmFreeReservedContextList(arg1: *mut drm_context_t);
2974}
2975unsafe extern "C" {
2976 pub fn drmSwitchToContext(fd: ::core::ffi::c_int, context: drm_context_t)
2977 -> ::core::ffi::c_int;
2978}
2979unsafe extern "C" {
2980 pub fn drmDestroyContext(fd: ::core::ffi::c_int, handle: drm_context_t) -> ::core::ffi::c_int;
2981}
2982unsafe extern "C" {
2983 pub fn drmCreateDrawable(
2984 fd: ::core::ffi::c_int,
2985 handle: *mut drm_drawable_t,
2986 ) -> ::core::ffi::c_int;
2987}
2988unsafe extern "C" {
2989 pub fn drmDestroyDrawable(fd: ::core::ffi::c_int, handle: drm_drawable_t)
2990 -> ::core::ffi::c_int;
2991}
2992unsafe extern "C" {
2993 pub fn drmUpdateDrawableInfo(
2994 fd: ::core::ffi::c_int,
2995 handle: drm_drawable_t,
2996 type_: drm_drawable_info_type_t,
2997 num: ::core::ffi::c_uint,
2998 data: *mut ::core::ffi::c_void,
2999 ) -> ::core::ffi::c_int;
3000}
3001unsafe extern "C" {
3002 pub fn drmCtlInstHandler(fd: ::core::ffi::c_int, irq: ::core::ffi::c_int)
3003 -> ::core::ffi::c_int;
3004}
3005unsafe extern "C" {
3006 pub fn drmCtlUninstHandler(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3007}
3008unsafe extern "C" {
3009 pub fn drmSetClientCap(
3010 fd: ::core::ffi::c_int,
3011 capability: u64,
3012 value: u64,
3013 ) -> ::core::ffi::c_int;
3014}
3015unsafe extern "C" {
3016 pub fn drmCrtcGetSequence(
3017 fd: ::core::ffi::c_int,
3018 crtcId: u32,
3019 sequence: *mut u64,
3020 ns: *mut u64,
3021 ) -> ::core::ffi::c_int;
3022}
3023unsafe extern "C" {
3024 pub fn drmCrtcQueueSequence(
3025 fd: ::core::ffi::c_int,
3026 crtcId: u32,
3027 flags: u32,
3028 sequence: u64,
3029 sequence_queued: *mut u64,
3030 user_data: u64,
3031 ) -> ::core::ffi::c_int;
3032}
3033unsafe extern "C" {
3034 pub fn drmMap(
3035 fd: ::core::ffi::c_int,
3036 handle: drm_handle_t,
3037 size: drmSize,
3038 address: drmAddressPtr,
3039 ) -> ::core::ffi::c_int;
3040}
3041unsafe extern "C" {
3042 pub fn drmUnmap(address: drmAddress, size: drmSize) -> ::core::ffi::c_int;
3043}
3044unsafe extern "C" {
3045 pub fn drmGetBufInfo(fd: ::core::ffi::c_int) -> drmBufInfoPtr;
3046}
3047unsafe extern "C" {
3048 pub fn drmMapBufs(fd: ::core::ffi::c_int) -> drmBufMapPtr;
3049}
3050unsafe extern "C" {
3051 pub fn drmUnmapBufs(bufs: drmBufMapPtr) -> ::core::ffi::c_int;
3052}
3053unsafe extern "C" {
3054 pub fn drmDMA(fd: ::core::ffi::c_int, request: drmDMAReqPtr) -> ::core::ffi::c_int;
3055}
3056unsafe extern "C" {
3057 pub fn drmFreeBufs(
3058 fd: ::core::ffi::c_int,
3059 count: ::core::ffi::c_int,
3060 list: *mut ::core::ffi::c_int,
3061 ) -> ::core::ffi::c_int;
3062}
3063unsafe extern "C" {
3064 pub fn drmGetLock(
3065 fd: ::core::ffi::c_int,
3066 context: drm_context_t,
3067 flags: drmLockFlags,
3068 ) -> ::core::ffi::c_int;
3069}
3070unsafe extern "C" {
3071 pub fn drmUnlock(fd: ::core::ffi::c_int, context: drm_context_t) -> ::core::ffi::c_int;
3072}
3073unsafe extern "C" {
3074 pub fn drmFinish(
3075 fd: ::core::ffi::c_int,
3076 context: ::core::ffi::c_int,
3077 flags: drmLockFlags,
3078 ) -> ::core::ffi::c_int;
3079}
3080unsafe extern "C" {
3081 pub fn drmGetContextPrivateMapping(
3082 fd: ::core::ffi::c_int,
3083 ctx_id: drm_context_t,
3084 handle: *mut drm_handle_t,
3085 ) -> ::core::ffi::c_int;
3086}
3087unsafe extern "C" {
3088 pub fn drmAgpAcquire(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3089}
3090unsafe extern "C" {
3091 pub fn drmAgpRelease(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3092}
3093unsafe extern "C" {
3094 pub fn drmAgpEnable(fd: ::core::ffi::c_int, mode: ::core::ffi::c_ulong) -> ::core::ffi::c_int;
3095}
3096unsafe extern "C" {
3097 pub fn drmAgpAlloc(
3098 fd: ::core::ffi::c_int,
3099 size: ::core::ffi::c_ulong,
3100 type_: ::core::ffi::c_ulong,
3101 address: *mut ::core::ffi::c_ulong,
3102 handle: *mut drm_handle_t,
3103 ) -> ::core::ffi::c_int;
3104}
3105unsafe extern "C" {
3106 pub fn drmAgpFree(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
3107}
3108unsafe extern "C" {
3109 pub fn drmAgpBind(
3110 fd: ::core::ffi::c_int,
3111 handle: drm_handle_t,
3112 offset: ::core::ffi::c_ulong,
3113 ) -> ::core::ffi::c_int;
3114}
3115unsafe extern "C" {
3116 pub fn drmAgpUnbind(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
3117}
3118unsafe extern "C" {
3119 pub fn drmAgpVersionMajor(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3120}
3121unsafe extern "C" {
3122 pub fn drmAgpVersionMinor(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3123}
3124unsafe extern "C" {
3125 pub fn drmAgpGetMode(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
3126}
3127unsafe extern "C" {
3128 pub fn drmAgpBase(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
3129}
3130unsafe extern "C" {
3131 pub fn drmAgpSize(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
3132}
3133unsafe extern "C" {
3134 pub fn drmAgpMemoryUsed(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
3135}
3136unsafe extern "C" {
3137 pub fn drmAgpMemoryAvail(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
3138}
3139unsafe extern "C" {
3140 pub fn drmAgpVendorId(fd: ::core::ffi::c_int) -> ::core::ffi::c_uint;
3141}
3142unsafe extern "C" {
3143 pub fn drmAgpDeviceId(fd: ::core::ffi::c_int) -> ::core::ffi::c_uint;
3144}
3145unsafe extern "C" {
3146 pub fn drmScatterGatherAlloc(
3147 fd: ::core::ffi::c_int,
3148 size: ::core::ffi::c_ulong,
3149 handle: *mut drm_handle_t,
3150 ) -> ::core::ffi::c_int;
3151}
3152unsafe extern "C" {
3153 pub fn drmScatterGatherFree(fd: ::core::ffi::c_int, handle: drm_handle_t)
3154 -> ::core::ffi::c_int;
3155}
3156unsafe extern "C" {
3157 pub fn drmWaitVBlank(fd: ::core::ffi::c_int, vbl: drmVBlankPtr) -> ::core::ffi::c_int;
3158}
3159unsafe extern "C" {
3160 pub fn drmSetServerInfo(info: drmServerInfoPtr);
3161}
3162unsafe extern "C" {
3163 pub fn drmError(
3164 err: ::core::ffi::c_int,
3165 label: *const ::core::ffi::c_char,
3166 ) -> ::core::ffi::c_int;
3167}
3168unsafe extern "C" {
3169 pub fn drmMalloc(size: ::core::ffi::c_int) -> *mut ::core::ffi::c_void;
3170}
3171unsafe extern "C" {
3172 pub fn drmFree(pt: *mut ::core::ffi::c_void);
3173}
3174unsafe extern "C" {
3175 pub fn drmHashCreate() -> *mut ::core::ffi::c_void;
3176}
3177unsafe extern "C" {
3178 pub fn drmHashDestroy(t: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
3179}
3180unsafe extern "C" {
3181 pub fn drmHashLookup(
3182 t: *mut ::core::ffi::c_void,
3183 key: ::core::ffi::c_ulong,
3184 value: *mut *mut ::core::ffi::c_void,
3185 ) -> ::core::ffi::c_int;
3186}
3187unsafe extern "C" {
3188 pub fn drmHashInsert(
3189 t: *mut ::core::ffi::c_void,
3190 key: ::core::ffi::c_ulong,
3191 value: *mut ::core::ffi::c_void,
3192 ) -> ::core::ffi::c_int;
3193}
3194unsafe extern "C" {
3195 pub fn drmHashDelete(
3196 t: *mut ::core::ffi::c_void,
3197 key: ::core::ffi::c_ulong,
3198 ) -> ::core::ffi::c_int;
3199}
3200unsafe extern "C" {
3201 pub fn drmHashFirst(
3202 t: *mut ::core::ffi::c_void,
3203 key: *mut ::core::ffi::c_ulong,
3204 value: *mut *mut ::core::ffi::c_void,
3205 ) -> ::core::ffi::c_int;
3206}
3207unsafe extern "C" {
3208 pub fn drmHashNext(
3209 t: *mut ::core::ffi::c_void,
3210 key: *mut ::core::ffi::c_ulong,
3211 value: *mut *mut ::core::ffi::c_void,
3212 ) -> ::core::ffi::c_int;
3213}
3214unsafe extern "C" {
3215 pub fn drmRandomCreate(seed: ::core::ffi::c_ulong) -> *mut ::core::ffi::c_void;
3216}
3217unsafe extern "C" {
3218 pub fn drmRandomDestroy(state: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
3219}
3220unsafe extern "C" {
3221 pub fn drmRandom(state: *mut ::core::ffi::c_void) -> ::core::ffi::c_ulong;
3222}
3223unsafe extern "C" {
3224 pub fn drmRandomDouble(state: *mut ::core::ffi::c_void) -> f64;
3225}
3226unsafe extern "C" {
3227 pub fn drmSLCreate() -> *mut ::core::ffi::c_void;
3228}
3229unsafe extern "C" {
3230 pub fn drmSLDestroy(l: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
3231}
3232unsafe extern "C" {
3233 pub fn drmSLLookup(
3234 l: *mut ::core::ffi::c_void,
3235 key: ::core::ffi::c_ulong,
3236 value: *mut *mut ::core::ffi::c_void,
3237 ) -> ::core::ffi::c_int;
3238}
3239unsafe extern "C" {
3240 pub fn drmSLInsert(
3241 l: *mut ::core::ffi::c_void,
3242 key: ::core::ffi::c_ulong,
3243 value: *mut ::core::ffi::c_void,
3244 ) -> ::core::ffi::c_int;
3245}
3246unsafe extern "C" {
3247 pub fn drmSLDelete(
3248 l: *mut ::core::ffi::c_void,
3249 key: ::core::ffi::c_ulong,
3250 ) -> ::core::ffi::c_int;
3251}
3252unsafe extern "C" {
3253 pub fn drmSLNext(
3254 l: *mut ::core::ffi::c_void,
3255 key: *mut ::core::ffi::c_ulong,
3256 value: *mut *mut ::core::ffi::c_void,
3257 ) -> ::core::ffi::c_int;
3258}
3259unsafe extern "C" {
3260 pub fn drmSLFirst(
3261 l: *mut ::core::ffi::c_void,
3262 key: *mut ::core::ffi::c_ulong,
3263 value: *mut *mut ::core::ffi::c_void,
3264 ) -> ::core::ffi::c_int;
3265}
3266unsafe extern "C" {
3267 pub fn drmSLDump(l: *mut ::core::ffi::c_void);
3268}
3269unsafe extern "C" {
3270 pub fn drmSLLookupNeighbors(
3271 l: *mut ::core::ffi::c_void,
3272 key: ::core::ffi::c_ulong,
3273 prev_key: *mut ::core::ffi::c_ulong,
3274 prev_value: *mut *mut ::core::ffi::c_void,
3275 next_key: *mut ::core::ffi::c_ulong,
3276 next_value: *mut *mut ::core::ffi::c_void,
3277 ) -> ::core::ffi::c_int;
3278}
3279unsafe extern "C" {
3280 pub fn drmOpenOnce(
3281 unused: *mut ::core::ffi::c_void,
3282 BusID: *const ::core::ffi::c_char,
3283 newlyopened: *mut ::core::ffi::c_int,
3284 ) -> ::core::ffi::c_int;
3285}
3286unsafe extern "C" {
3287 pub fn drmOpenOnceWithType(
3288 BusID: *const ::core::ffi::c_char,
3289 newlyopened: *mut ::core::ffi::c_int,
3290 type_: ::core::ffi::c_int,
3291 ) -> ::core::ffi::c_int;
3292}
3293unsafe extern "C" {
3294 pub fn drmCloseOnce(fd: ::core::ffi::c_int);
3295}
3296unsafe extern "C" {
3297 pub fn drmMsg(format: *const ::core::ffi::c_char, ...);
3298}
3299unsafe extern "C" {
3300 pub fn drmSetMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3301}
3302unsafe extern "C" {
3303 pub fn drmDropMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3304}
3305unsafe extern "C" {
3306 pub fn drmIsMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3307}
3308#[repr(C)]
3309#[derive(Debug, Copy, Clone)]
3310pub struct _drmEventContext {
3311 pub version: ::core::ffi::c_int,
3312 pub vblank_handler: ::core::option::Option<
3313 unsafe extern "C" fn(
3314 fd: ::core::ffi::c_int,
3315 sequence: ::core::ffi::c_uint,
3316 tv_sec: ::core::ffi::c_uint,
3317 tv_usec: ::core::ffi::c_uint,
3318 user_data: *mut ::core::ffi::c_void,
3319 ),
3320 >,
3321 pub page_flip_handler: ::core::option::Option<
3322 unsafe extern "C" fn(
3323 fd: ::core::ffi::c_int,
3324 sequence: ::core::ffi::c_uint,
3325 tv_sec: ::core::ffi::c_uint,
3326 tv_usec: ::core::ffi::c_uint,
3327 user_data: *mut ::core::ffi::c_void,
3328 ),
3329 >,
3330 pub page_flip_handler2: ::core::option::Option<
3331 unsafe extern "C" fn(
3332 fd: ::core::ffi::c_int,
3333 sequence: ::core::ffi::c_uint,
3334 tv_sec: ::core::ffi::c_uint,
3335 tv_usec: ::core::ffi::c_uint,
3336 crtc_id: ::core::ffi::c_uint,
3337 user_data: *mut ::core::ffi::c_void,
3338 ),
3339 >,
3340 pub sequence_handler: ::core::option::Option<
3341 unsafe extern "C" fn(fd: ::core::ffi::c_int, sequence: u64, ns: u64, user_data: u64),
3342 >,
3343}
3344pub type drmEventContext = _drmEventContext;
3345pub type drmEventContextPtr = *mut _drmEventContext;
3346unsafe extern "C" {
3347 pub fn drmHandleEvent(fd: ::core::ffi::c_int, evctx: drmEventContextPtr) -> ::core::ffi::c_int;
3348}
3349unsafe extern "C" {
3350 pub fn drmGetDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3351}
3352unsafe extern "C" {
3353 pub fn drmGetDeviceNameFromFd2(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3354}
3355unsafe extern "C" {
3356 pub fn drmGetNodeTypeFromFd(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3357}
3358unsafe extern "C" {
3359 pub fn drmPrimeHandleToFD(
3360 fd: ::core::ffi::c_int,
3361 handle: u32,
3362 flags: u32,
3363 prime_fd: *mut ::core::ffi::c_int,
3364 ) -> ::core::ffi::c_int;
3365}
3366unsafe extern "C" {
3367 pub fn drmPrimeFDToHandle(
3368 fd: ::core::ffi::c_int,
3369 prime_fd: ::core::ffi::c_int,
3370 handle: *mut u32,
3371 ) -> ::core::ffi::c_int;
3372}
3373unsafe extern "C" {
3374 pub fn drmCloseBufferHandle(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
3375}
3376unsafe extern "C" {
3377 pub fn drmGetPrimaryDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3378}
3379unsafe extern "C" {
3380 pub fn drmGetRenderDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3381}
3382#[repr(C)]
3383#[derive(Debug, Copy, Clone)]
3384pub struct _drmPciBusInfo {
3385 pub domain: u16,
3386 pub bus: u8,
3387 pub dev: u8,
3388 pub func: u8,
3389}
3390pub type drmPciBusInfo = _drmPciBusInfo;
3391pub type drmPciBusInfoPtr = *mut _drmPciBusInfo;
3392#[repr(C)]
3393#[derive(Debug, Copy, Clone)]
3394pub struct _drmPciDeviceInfo {
3395 pub vendor_id: u16,
3396 pub device_id: u16,
3397 pub subvendor_id: u16,
3398 pub subdevice_id: u16,
3399 pub revision_id: u8,
3400}
3401pub type drmPciDeviceInfo = _drmPciDeviceInfo;
3402pub type drmPciDeviceInfoPtr = *mut _drmPciDeviceInfo;
3403#[repr(C)]
3404#[derive(Debug, Copy, Clone)]
3405pub struct _drmUsbBusInfo {
3406 pub bus: u8,
3407 pub dev: u8,
3408}
3409pub type drmUsbBusInfo = _drmUsbBusInfo;
3410pub type drmUsbBusInfoPtr = *mut _drmUsbBusInfo;
3411#[repr(C)]
3412#[derive(Debug, Copy, Clone)]
3413pub struct _drmUsbDeviceInfo {
3414 pub vendor: u16,
3415 pub product: u16,
3416}
3417pub type drmUsbDeviceInfo = _drmUsbDeviceInfo;
3418pub type drmUsbDeviceInfoPtr = *mut _drmUsbDeviceInfo;
3419#[repr(C)]
3420#[derive(Debug, Copy, Clone)]
3421pub struct _drmPlatformBusInfo {
3422 pub fullname: [::core::ffi::c_char; 512usize],
3423}
3424pub type drmPlatformBusInfo = _drmPlatformBusInfo;
3425pub type drmPlatformBusInfoPtr = *mut _drmPlatformBusInfo;
3426#[repr(C)]
3427#[derive(Debug, Copy, Clone)]
3428pub struct _drmPlatformDeviceInfo {
3429 pub compatible: *mut *mut ::core::ffi::c_char,
3430}
3431pub type drmPlatformDeviceInfo = _drmPlatformDeviceInfo;
3432pub type drmPlatformDeviceInfoPtr = *mut _drmPlatformDeviceInfo;
3433#[repr(C)]
3434#[derive(Debug, Copy, Clone)]
3435pub struct _drmHost1xBusInfo {
3436 pub fullname: [::core::ffi::c_char; 512usize],
3437}
3438pub type drmHost1xBusInfo = _drmHost1xBusInfo;
3439pub type drmHost1xBusInfoPtr = *mut _drmHost1xBusInfo;
3440#[repr(C)]
3441#[derive(Debug, Copy, Clone)]
3442pub struct _drmHost1xDeviceInfo {
3443 pub compatible: *mut *mut ::core::ffi::c_char,
3444}
3445pub type drmHost1xDeviceInfo = _drmHost1xDeviceInfo;
3446pub type drmHost1xDeviceInfoPtr = *mut _drmHost1xDeviceInfo;
3447#[repr(C)]
3448#[derive(Copy, Clone)]
3449pub struct _drmDevice {
3450 pub nodes: *mut *mut ::core::ffi::c_char,
3451 pub available_nodes: ::core::ffi::c_int,
3452 pub bustype: ::core::ffi::c_int,
3453 pub businfo: _drmDevice__bindgen_ty_1,
3454 pub deviceinfo: _drmDevice__bindgen_ty_2,
3455}
3456#[repr(C)]
3457#[derive(Copy, Clone)]
3458pub union _drmDevice__bindgen_ty_1 {
3459 pub pci: drmPciBusInfoPtr,
3460 pub usb: drmUsbBusInfoPtr,
3461 pub platform: drmPlatformBusInfoPtr,
3462 pub host1x: drmHost1xBusInfoPtr,
3463}
3464#[repr(C)]
3465#[derive(Copy, Clone)]
3466pub union _drmDevice__bindgen_ty_2 {
3467 pub pci: drmPciDeviceInfoPtr,
3468 pub usb: drmUsbDeviceInfoPtr,
3469 pub platform: drmPlatformDeviceInfoPtr,
3470 pub host1x: drmHost1xDeviceInfoPtr,
3471}
3472pub type drmDevice = _drmDevice;
3473pub type drmDevicePtr = *mut _drmDevice;
3474unsafe extern "C" {
3475 pub fn drmGetDevice(fd: ::core::ffi::c_int, device: *mut drmDevicePtr) -> ::core::ffi::c_int;
3476}
3477unsafe extern "C" {
3478 pub fn drmFreeDevice(device: *mut drmDevicePtr);
3479}
3480unsafe extern "C" {
3481 pub fn drmGetDevices(
3482 devices: *mut drmDevicePtr,
3483 max_devices: ::core::ffi::c_int,
3484 ) -> ::core::ffi::c_int;
3485}
3486unsafe extern "C" {
3487 pub fn drmFreeDevices(devices: *mut drmDevicePtr, count: ::core::ffi::c_int);
3488}
3489unsafe extern "C" {
3490 pub fn drmGetDevice2(
3491 fd: ::core::ffi::c_int,
3492 flags: u32,
3493 device: *mut drmDevicePtr,
3494 ) -> ::core::ffi::c_int;
3495}
3496unsafe extern "C" {
3497 pub fn drmGetDevices2(
3498 flags: u32,
3499 devices: *mut drmDevicePtr,
3500 max_devices: ::core::ffi::c_int,
3501 ) -> ::core::ffi::c_int;
3502}
3503unsafe extern "C" {
3504 pub fn drmGetDeviceFromDevId(
3505 dev_id: dev_t,
3506 flags: u32,
3507 device: *mut drmDevicePtr,
3508 ) -> ::core::ffi::c_int;
3509}
3510unsafe extern "C" {
3511 #[doc = " Get the node type (DRM_NODE_PRIMARY or DRM_NODE_RENDER) from a device ID.\n\n Returns negative errno on error."]
3512 pub fn drmGetNodeTypeFromDevId(devid: dev_t) -> ::core::ffi::c_int;
3513}
3514unsafe extern "C" {
3515 #[doc = " Check if two drmDevice pointers represent the same DRM device.\n\n Returns 1 if the devices are equal, 0 otherwise."]
3516 pub fn drmDevicesEqual(a: drmDevicePtr, b: drmDevicePtr) -> ::core::ffi::c_int;
3517}
3518unsafe extern "C" {
3519 pub fn drmSyncobjCreate(
3520 fd: ::core::ffi::c_int,
3521 flags: u32,
3522 handle: *mut u32,
3523 ) -> ::core::ffi::c_int;
3524}
3525unsafe extern "C" {
3526 pub fn drmSyncobjDestroy(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
3527}
3528unsafe extern "C" {
3529 pub fn drmSyncobjHandleToFD(
3530 fd: ::core::ffi::c_int,
3531 handle: u32,
3532 obj_fd: *mut ::core::ffi::c_int,
3533 ) -> ::core::ffi::c_int;
3534}
3535unsafe extern "C" {
3536 pub fn drmSyncobjFDToHandle(
3537 fd: ::core::ffi::c_int,
3538 obj_fd: ::core::ffi::c_int,
3539 handle: *mut u32,
3540 ) -> ::core::ffi::c_int;
3541}
3542unsafe extern "C" {
3543 pub fn drmSyncobjImportSyncFile(
3544 fd: ::core::ffi::c_int,
3545 handle: u32,
3546 sync_file_fd: ::core::ffi::c_int,
3547 ) -> ::core::ffi::c_int;
3548}
3549unsafe extern "C" {
3550 pub fn drmSyncobjExportSyncFile(
3551 fd: ::core::ffi::c_int,
3552 handle: u32,
3553 sync_file_fd: *mut ::core::ffi::c_int,
3554 ) -> ::core::ffi::c_int;
3555}
3556unsafe extern "C" {
3557 pub fn drmSyncobjWait(
3558 fd: ::core::ffi::c_int,
3559 handles: *mut u32,
3560 num_handles: ::core::ffi::c_uint,
3561 timeout_nsec: i64,
3562 flags: ::core::ffi::c_uint,
3563 first_signaled: *mut u32,
3564 ) -> ::core::ffi::c_int;
3565}
3566unsafe extern "C" {
3567 pub fn drmSyncobjReset(
3568 fd: ::core::ffi::c_int,
3569 handles: *const u32,
3570 handle_count: u32,
3571 ) -> ::core::ffi::c_int;
3572}
3573unsafe extern "C" {
3574 pub fn drmSyncobjSignal(
3575 fd: ::core::ffi::c_int,
3576 handles: *const u32,
3577 handle_count: u32,
3578 ) -> ::core::ffi::c_int;
3579}
3580unsafe extern "C" {
3581 pub fn drmSyncobjTimelineSignal(
3582 fd: ::core::ffi::c_int,
3583 handles: *const u32,
3584 points: *mut u64,
3585 handle_count: u32,
3586 ) -> ::core::ffi::c_int;
3587}
3588unsafe extern "C" {
3589 pub fn drmSyncobjTimelineWait(
3590 fd: ::core::ffi::c_int,
3591 handles: *mut u32,
3592 points: *mut u64,
3593 num_handles: ::core::ffi::c_uint,
3594 timeout_nsec: i64,
3595 flags: ::core::ffi::c_uint,
3596 first_signaled: *mut u32,
3597 ) -> ::core::ffi::c_int;
3598}
3599unsafe extern "C" {
3600 pub fn drmSyncobjQuery(
3601 fd: ::core::ffi::c_int,
3602 handles: *mut u32,
3603 points: *mut u64,
3604 handle_count: u32,
3605 ) -> ::core::ffi::c_int;
3606}
3607unsafe extern "C" {
3608 pub fn drmSyncobjQuery2(
3609 fd: ::core::ffi::c_int,
3610 handles: *mut u32,
3611 points: *mut u64,
3612 handle_count: u32,
3613 flags: u32,
3614 ) -> ::core::ffi::c_int;
3615}
3616unsafe extern "C" {
3617 pub fn drmSyncobjTransfer(
3618 fd: ::core::ffi::c_int,
3619 dst_handle: u32,
3620 dst_point: u64,
3621 src_handle: u32,
3622 src_point: u64,
3623 flags: u32,
3624 ) -> ::core::ffi::c_int;
3625}
3626unsafe extern "C" {
3627 pub fn drmSyncobjEventfd(
3628 fd: ::core::ffi::c_int,
3629 handle: u32,
3630 point: u64,
3631 ev_fd: ::core::ffi::c_int,
3632 flags: u32,
3633 ) -> ::core::ffi::c_int;
3634}
3635unsafe extern "C" {
3636 pub fn drmGetFormatModifierVendor(modifier: u64) -> *mut ::core::ffi::c_char;
3637}
3638unsafe extern "C" {
3639 pub fn drmGetFormatModifierName(modifier: u64) -> *mut ::core::ffi::c_char;
3640}
3641unsafe extern "C" {
3642 pub fn drmGetFormatName(format: u32) -> *mut ::core::ffi::c_char;
3643}
3644pub type wchar_t = ::core::ffi::c_int;
3645#[repr(C)]
3646#[repr(align(16))]
3647#[derive(Debug, Copy, Clone)]
3648pub struct max_align_t {
3649 pub __clang_max_align_nonce1: ::core::ffi::c_longlong,
3650 pub __bindgen_padding_0: u64,
3651 pub __clang_max_align_nonce2: u128,
3652}
3653#[repr(C)]
3654#[derive(Debug, Copy, Clone)]
3655pub struct _drmModeRes {
3656 pub count_fbs: ::core::ffi::c_int,
3657 pub fbs: *mut u32,
3658 pub count_crtcs: ::core::ffi::c_int,
3659 pub crtcs: *mut u32,
3660 pub count_connectors: ::core::ffi::c_int,
3661 pub connectors: *mut u32,
3662 pub count_encoders: ::core::ffi::c_int,
3663 pub encoders: *mut u32,
3664 pub min_width: u32,
3665 pub max_width: u32,
3666 pub min_height: u32,
3667 pub max_height: u32,
3668}
3669pub type drmModeRes = _drmModeRes;
3670pub type drmModeResPtr = *mut _drmModeRes;
3671#[repr(C)]
3672#[derive(Debug, Copy, Clone)]
3673pub struct _drmModeModeInfo {
3674 pub clock: u32,
3675 pub hdisplay: u16,
3676 pub hsync_start: u16,
3677 pub hsync_end: u16,
3678 pub htotal: u16,
3679 pub hskew: u16,
3680 pub vdisplay: u16,
3681 pub vsync_start: u16,
3682 pub vsync_end: u16,
3683 pub vtotal: u16,
3684 pub vscan: u16,
3685 pub vrefresh: u32,
3686 pub flags: u32,
3687 pub type_: u32,
3688 pub name: [::core::ffi::c_char; 32usize],
3689}
3690pub type drmModeModeInfo = _drmModeModeInfo;
3691pub type drmModeModeInfoPtr = *mut _drmModeModeInfo;
3692#[repr(C)]
3693#[derive(Debug, Copy, Clone)]
3694pub struct _drmModeFB {
3695 pub fb_id: u32,
3696 pub width: u32,
3697 pub height: u32,
3698 pub pitch: u32,
3699 pub bpp: u32,
3700 pub depth: u32,
3701 pub handle: u32,
3702}
3703pub type drmModeFB = _drmModeFB;
3704pub type drmModeFBPtr = *mut _drmModeFB;
3705#[repr(C)]
3706#[derive(Debug, Copy, Clone)]
3707pub struct _drmModeFB2 {
3708 pub fb_id: u32,
3709 pub width: u32,
3710 pub height: u32,
3711 pub pixel_format: u32,
3712 pub modifier: u64,
3713 pub flags: u32,
3714 pub handles: [u32; 4usize],
3715 pub pitches: [u32; 4usize],
3716 pub offsets: [u32; 4usize],
3717}
3718pub type drmModeFB2 = _drmModeFB2;
3719pub type drmModeFB2Ptr = *mut _drmModeFB2;
3720pub type drmModeClip = drm_clip_rect;
3721pub type drmModeClipPtr = *mut drm_clip_rect;
3722#[repr(C)]
3723#[derive(Debug, Copy, Clone)]
3724pub struct _drmModePropertyBlob {
3725 pub id: u32,
3726 pub length: u32,
3727 pub data: *mut ::core::ffi::c_void,
3728}
3729pub type drmModePropertyBlobRes = _drmModePropertyBlob;
3730pub type drmModePropertyBlobPtr = *mut _drmModePropertyBlob;
3731#[repr(C)]
3732#[derive(Debug, Copy, Clone)]
3733pub struct _drmModeProperty {
3734 pub prop_id: u32,
3735 pub flags: u32,
3736 pub name: [::core::ffi::c_char; 32usize],
3737 pub count_values: ::core::ffi::c_int,
3738 pub values: *mut u64,
3739 pub count_enums: ::core::ffi::c_int,
3740 pub enums: *mut drm_mode_property_enum,
3741 pub count_blobs: ::core::ffi::c_int,
3742 pub blob_ids: *mut u32,
3743}
3744pub type drmModePropertyRes = _drmModeProperty;
3745pub type drmModePropertyPtr = *mut _drmModeProperty;
3746#[repr(C)]
3747#[derive(Debug, Copy, Clone)]
3748pub struct _drmModeCrtc {
3749 pub crtc_id: u32,
3750 #[doc = "< FB id to connect to 0 = disconnect"]
3751 pub buffer_id: u32,
3752 #[doc = "< Position on the framebuffer"]
3753 pub x: u32,
3754 #[doc = "< Position on the framebuffer"]
3755 pub y: u32,
3756 pub width: u32,
3757 pub height: u32,
3758 pub mode_valid: ::core::ffi::c_int,
3759 pub mode: drmModeModeInfo,
3760 #[doc = "< Number of gamma stops"]
3761 pub gamma_size: ::core::ffi::c_int,
3762}
3763pub type drmModeCrtc = _drmModeCrtc;
3764pub type drmModeCrtcPtr = *mut _drmModeCrtc;
3765#[repr(C)]
3766#[derive(Debug, Copy, Clone)]
3767pub struct _drmModeEncoder {
3768 pub encoder_id: u32,
3769 pub encoder_type: u32,
3770 pub crtc_id: u32,
3771 pub possible_crtcs: u32,
3772 pub possible_clones: u32,
3773}
3774pub type drmModeEncoder = _drmModeEncoder;
3775pub type drmModeEncoderPtr = *mut _drmModeEncoder;
3776pub const drmModeConnection_DRM_MODE_CONNECTED: drmModeConnection = 1;
3777pub const drmModeConnection_DRM_MODE_DISCONNECTED: drmModeConnection = 2;
3778pub const drmModeConnection_DRM_MODE_UNKNOWNCONNECTION: drmModeConnection = 3;
3779#[doc = " Describes the connector status.\n\n DRM_MODE_CONNECTED means that the connector has a sink plugged in.\n DRM_MODE_DISCONNECTED means the contrary. DRM_MODE_UNKNOWNCONNECTION is used\n when it could be either.\n\n User-space should first try to enable DRM_MODE_CONNECTED connectors and\n ignore other connectors. If there are no DRM_MODE_CONNECTED connectors,\n user-space should then try to probe and enable DRM_MODE_UNKNOWNCONNECTION\n connectors."]
3780pub type drmModeConnection = ::core::ffi::c_uint;
3781pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_UNKNOWN: drmModeSubPixel = 1;
3782pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_HORIZONTAL_RGB: drmModeSubPixel = 2;
3783pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_HORIZONTAL_BGR: drmModeSubPixel = 3;
3784pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_VERTICAL_RGB: drmModeSubPixel = 4;
3785pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_VERTICAL_BGR: drmModeSubPixel = 5;
3786pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_NONE: drmModeSubPixel = 6;
3787pub type drmModeSubPixel = ::core::ffi::c_uint;
3788#[repr(C)]
3789#[derive(Debug, Copy, Clone)]
3790pub struct _drmModeConnector {
3791 pub connector_id: u32,
3792 #[doc = "< Encoder currently connected to"]
3793 pub encoder_id: u32,
3794 pub connector_type: u32,
3795 pub connector_type_id: u32,
3796 pub connection: drmModeConnection,
3797 #[doc = "< HxW in millimeters"]
3798 pub mmWidth: u32,
3799 #[doc = "< HxW in millimeters"]
3800 pub mmHeight: u32,
3801 pub subpixel: drmModeSubPixel,
3802 pub count_modes: ::core::ffi::c_int,
3803 pub modes: drmModeModeInfoPtr,
3804 pub count_props: ::core::ffi::c_int,
3805 #[doc = "< List of property ids"]
3806 pub props: *mut u32,
3807 #[doc = "< List of property values"]
3808 pub prop_values: *mut u64,
3809 pub count_encoders: ::core::ffi::c_int,
3810 #[doc = "< List of encoder ids"]
3811 pub encoders: *mut u32,
3812}
3813pub type drmModeConnector = _drmModeConnector;
3814pub type drmModeConnectorPtr = *mut _drmModeConnector;
3815#[repr(C)]
3816#[derive(Debug, Copy, Clone)]
3817pub struct _drmModeObjectProperties {
3818 pub count_props: u32,
3819 pub props: *mut u32,
3820 pub prop_values: *mut u64,
3821}
3822pub type drmModeObjectProperties = _drmModeObjectProperties;
3823pub type drmModeObjectPropertiesPtr = *mut _drmModeObjectProperties;
3824#[repr(C)]
3825#[derive(Debug, Copy, Clone)]
3826pub struct _drmModeFormatModifierIterator {
3827 pub fmt_idx: u32,
3828 pub mod_idx: u32,
3829 pub fmt: u32,
3830 pub mod_: u64,
3831}
3832pub type drmModeFormatModifierIterator = _drmModeFormatModifierIterator;
3833#[repr(C)]
3834#[derive(Debug, Copy, Clone)]
3835pub struct _drmModePlane {
3836 pub count_formats: u32,
3837 pub formats: *mut u32,
3838 pub plane_id: u32,
3839 pub crtc_id: u32,
3840 pub fb_id: u32,
3841 pub crtc_x: u32,
3842 pub crtc_y: u32,
3843 pub x: u32,
3844 pub y: u32,
3845 pub possible_crtcs: u32,
3846 pub gamma_size: u32,
3847}
3848pub type drmModePlane = _drmModePlane;
3849pub type drmModePlanePtr = *mut _drmModePlane;
3850#[repr(C)]
3851#[derive(Debug, Copy, Clone)]
3852pub struct _drmModePlaneRes {
3853 pub count_planes: u32,
3854 pub planes: *mut u32,
3855}
3856pub type drmModePlaneRes = _drmModePlaneRes;
3857pub type drmModePlaneResPtr = *mut _drmModePlaneRes;
3858unsafe extern "C" {
3859 pub fn drmModeFreeModeInfo(ptr: drmModeModeInfoPtr);
3860}
3861unsafe extern "C" {
3862 pub fn drmModeFreeResources(ptr: drmModeResPtr);
3863}
3864unsafe extern "C" {
3865 pub fn drmModeFreeFB(ptr: drmModeFBPtr);
3866}
3867unsafe extern "C" {
3868 pub fn drmModeFreeFB2(ptr: drmModeFB2Ptr);
3869}
3870unsafe extern "C" {
3871 pub fn drmModeFreeCrtc(ptr: drmModeCrtcPtr);
3872}
3873unsafe extern "C" {
3874 pub fn drmModeFreeConnector(ptr: drmModeConnectorPtr);
3875}
3876unsafe extern "C" {
3877 pub fn drmModeFreeEncoder(ptr: drmModeEncoderPtr);
3878}
3879unsafe extern "C" {
3880 pub fn drmModeFreePlane(ptr: drmModePlanePtr);
3881}
3882unsafe extern "C" {
3883 pub fn drmModeFreePlaneResources(ptr: drmModePlaneResPtr);
3884}
3885unsafe extern "C" {
3886 #[doc = " Check whether the DRM node supports Kernel Mode-Setting.\n\n Returns 1 if suitable for KMS, 0 otherwise."]
3887 pub fn drmIsKMS(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3888}
3889unsafe extern "C" {
3890 #[doc = " Retrieves all of the resources associated with a card."]
3891 pub fn drmModeGetResources(fd: ::core::ffi::c_int) -> drmModeResPtr;
3892}
3893unsafe extern "C" {
3894 #[doc = " Retrieve information about framebuffer bufferId"]
3895 pub fn drmModeGetFB(fd: ::core::ffi::c_int, bufferId: u32) -> drmModeFBPtr;
3896}
3897unsafe extern "C" {
3898 pub fn drmModeGetFB2(fd: ::core::ffi::c_int, bufferId: u32) -> drmModeFB2Ptr;
3899}
3900unsafe extern "C" {
3901 #[doc = " Creates a new framebuffer with an buffer object as its scanout buffer."]
3902 pub fn drmModeAddFB(
3903 fd: ::core::ffi::c_int,
3904 width: u32,
3905 height: u32,
3906 depth: u8,
3907 bpp: u8,
3908 pitch: u32,
3909 bo_handle: u32,
3910 buf_id: *mut u32,
3911 ) -> ::core::ffi::c_int;
3912}
3913unsafe extern "C" {
3914 pub fn drmModeAddFB2(
3915 fd: ::core::ffi::c_int,
3916 width: u32,
3917 height: u32,
3918 pixel_format: u32,
3919 bo_handles: *const u32,
3920 pitches: *const u32,
3921 offsets: *const u32,
3922 buf_id: *mut u32,
3923 flags: u32,
3924 ) -> ::core::ffi::c_int;
3925}
3926unsafe extern "C" {
3927 pub fn drmModeAddFB2WithModifiers(
3928 fd: ::core::ffi::c_int,
3929 width: u32,
3930 height: u32,
3931 pixel_format: u32,
3932 bo_handles: *const u32,
3933 pitches: *const u32,
3934 offsets: *const u32,
3935 modifier: *const u64,
3936 buf_id: *mut u32,
3937 flags: u32,
3938 ) -> ::core::ffi::c_int;
3939}
3940unsafe extern "C" {
3941 #[doc = " Destroies the given framebuffer."]
3942 pub fn drmModeRmFB(fd: ::core::ffi::c_int, bufferId: u32) -> ::core::ffi::c_int;
3943}
3944unsafe extern "C" {
3945 #[doc = " Close a framebuffer.\n\n Same as drmModeRmFB(), except it doesn't implicitly disable planes and CRTCs."]
3946 pub fn drmModeCloseFB(fd: ::core::ffi::c_int, buffer_id: u32) -> ::core::ffi::c_int;
3947}
3948unsafe extern "C" {
3949 #[doc = " Mark a region of a framebuffer as dirty."]
3950 pub fn drmModeDirtyFB(
3951 fd: ::core::ffi::c_int,
3952 bufferId: u32,
3953 clips: drmModeClipPtr,
3954 num_clips: u32,
3955 ) -> ::core::ffi::c_int;
3956}
3957unsafe extern "C" {
3958 #[doc = " Retrieve information about the ctrt crtcId"]
3959 pub fn drmModeGetCrtc(fd: ::core::ffi::c_int, crtcId: u32) -> drmModeCrtcPtr;
3960}
3961unsafe extern "C" {
3962 #[doc = " Set the mode on a crtc crtcId with the given mode modeId."]
3963 pub fn drmModeSetCrtc(
3964 fd: ::core::ffi::c_int,
3965 crtcId: u32,
3966 bufferId: u32,
3967 x: u32,
3968 y: u32,
3969 connectors: *mut u32,
3970 count: ::core::ffi::c_int,
3971 mode: drmModeModeInfoPtr,
3972 ) -> ::core::ffi::c_int;
3973}
3974unsafe extern "C" {
3975 #[doc = " Set the cursor on crtc"]
3976 pub fn drmModeSetCursor(
3977 fd: ::core::ffi::c_int,
3978 crtcId: u32,
3979 bo_handle: u32,
3980 width: u32,
3981 height: u32,
3982 ) -> ::core::ffi::c_int;
3983}
3984unsafe extern "C" {
3985 pub fn drmModeSetCursor2(
3986 fd: ::core::ffi::c_int,
3987 crtcId: u32,
3988 bo_handle: u32,
3989 width: u32,
3990 height: u32,
3991 hot_x: i32,
3992 hot_y: i32,
3993 ) -> ::core::ffi::c_int;
3994}
3995unsafe extern "C" {
3996 #[doc = " Move the cursor on crtc"]
3997 pub fn drmModeMoveCursor(
3998 fd: ::core::ffi::c_int,
3999 crtcId: u32,
4000 x: ::core::ffi::c_int,
4001 y: ::core::ffi::c_int,
4002 ) -> ::core::ffi::c_int;
4003}
4004unsafe extern "C" {
4005 #[doc = " Encoder functions"]
4006 pub fn drmModeGetEncoder(fd: ::core::ffi::c_int, encoder_id: u32) -> drmModeEncoderPtr;
4007}
4008unsafe extern "C" {
4009 #[doc = " Retrieve all information about the connector connectorId. This will do a\n forced probe on the connector to retrieve remote information such as EDIDs\n from the display device."]
4010 pub fn drmModeGetConnector(fd: ::core::ffi::c_int, connectorId: u32) -> drmModeConnectorPtr;
4011}
4012unsafe extern "C" {
4013 #[doc = " Retrieve current information, i.e the currently active mode and encoder,\n about the connector connectorId. This will not do any probing on the\n connector or remote device, and only reports what is currently known.\n For the complete set of modes and encoders associated with the connector\n use drmModeGetConnector() which will do a probe to determine any display\n link changes first."]
4014 pub fn drmModeGetConnectorCurrent(
4015 fd: ::core::ffi::c_int,
4016 connector_id: u32,
4017 ) -> drmModeConnectorPtr;
4018}
4019unsafe extern "C" {
4020 #[doc = " Get a bitmask of CRTCs a connector is compatible with.\n\n The bits reference CRTC indices. If the n-th CRTC is compatible with the\n connector, the n-th bit will be set. The indices are taken from the array\n returned by drmModeGetResources(). The indices are different from the object\n IDs.\n\n Zero is returned on error."]
4021 pub fn drmModeConnectorGetPossibleCrtcs(
4022 fd: ::core::ffi::c_int,
4023 connector: *const drmModeConnector,
4024 ) -> u32;
4025}
4026unsafe extern "C" {
4027 #[doc = " Attaches the given mode to an connector."]
4028 pub fn drmModeAttachMode(
4029 fd: ::core::ffi::c_int,
4030 connectorId: u32,
4031 mode_info: drmModeModeInfoPtr,
4032 ) -> ::core::ffi::c_int;
4033}
4034unsafe extern "C" {
4035 #[doc = " Detaches a mode from the connector\n must be unused, by the given mode."]
4036 pub fn drmModeDetachMode(
4037 fd: ::core::ffi::c_int,
4038 connectorId: u32,
4039 mode_info: drmModeModeInfoPtr,
4040 ) -> ::core::ffi::c_int;
4041}
4042unsafe extern "C" {
4043 pub fn drmModeGetProperty(fd: ::core::ffi::c_int, propertyId: u32) -> drmModePropertyPtr;
4044}
4045unsafe extern "C" {
4046 pub fn drmModeFreeProperty(ptr: drmModePropertyPtr);
4047}
4048unsafe extern "C" {
4049 pub fn drmModeGetPropertyBlob(fd: ::core::ffi::c_int, blob_id: u32) -> drmModePropertyBlobPtr;
4050}
4051unsafe extern "C" {
4052 pub fn drmModeFormatModifierBlobIterNext(
4053 blob: *const drmModePropertyBlobRes,
4054 iter: *mut drmModeFormatModifierIterator,
4055 ) -> bool;
4056}
4057unsafe extern "C" {
4058 pub fn drmModeFreePropertyBlob(ptr: drmModePropertyBlobPtr);
4059}
4060unsafe extern "C" {
4061 pub fn drmModeConnectorSetProperty(
4062 fd: ::core::ffi::c_int,
4063 connector_id: u32,
4064 property_id: u32,
4065 value: u64,
4066 ) -> ::core::ffi::c_int;
4067}
4068unsafe extern "C" {
4069 pub fn drmCheckModesettingSupported(busid: *const ::core::ffi::c_char) -> ::core::ffi::c_int;
4070}
4071unsafe extern "C" {
4072 pub fn drmModeCrtcSetGamma(
4073 fd: ::core::ffi::c_int,
4074 crtc_id: u32,
4075 size: u32,
4076 red: *const u16,
4077 green: *const u16,
4078 blue: *const u16,
4079 ) -> ::core::ffi::c_int;
4080}
4081unsafe extern "C" {
4082 pub fn drmModeCrtcGetGamma(
4083 fd: ::core::ffi::c_int,
4084 crtc_id: u32,
4085 size: u32,
4086 red: *mut u16,
4087 green: *mut u16,
4088 blue: *mut u16,
4089 ) -> ::core::ffi::c_int;
4090}
4091unsafe extern "C" {
4092 pub fn drmModePageFlip(
4093 fd: ::core::ffi::c_int,
4094 crtc_id: u32,
4095 fb_id: u32,
4096 flags: u32,
4097 user_data: *mut ::core::ffi::c_void,
4098 ) -> ::core::ffi::c_int;
4099}
4100unsafe extern "C" {
4101 pub fn drmModePageFlipTarget(
4102 fd: ::core::ffi::c_int,
4103 crtc_id: u32,
4104 fb_id: u32,
4105 flags: u32,
4106 user_data: *mut ::core::ffi::c_void,
4107 target_vblank: u32,
4108 ) -> ::core::ffi::c_int;
4109}
4110unsafe extern "C" {
4111 pub fn drmModeGetPlaneResources(fd: ::core::ffi::c_int) -> drmModePlaneResPtr;
4112}
4113unsafe extern "C" {
4114 pub fn drmModeGetPlane(fd: ::core::ffi::c_int, plane_id: u32) -> drmModePlanePtr;
4115}
4116unsafe extern "C" {
4117 pub fn drmModeSetPlane(
4118 fd: ::core::ffi::c_int,
4119 plane_id: u32,
4120 crtc_id: u32,
4121 fb_id: u32,
4122 flags: u32,
4123 crtc_x: i32,
4124 crtc_y: i32,
4125 crtc_w: u32,
4126 crtc_h: u32,
4127 src_x: u32,
4128 src_y: u32,
4129 src_w: u32,
4130 src_h: u32,
4131 ) -> ::core::ffi::c_int;
4132}
4133unsafe extern "C" {
4134 pub fn drmModeObjectGetProperties(
4135 fd: ::core::ffi::c_int,
4136 object_id: u32,
4137 object_type: u32,
4138 ) -> drmModeObjectPropertiesPtr;
4139}
4140unsafe extern "C" {
4141 pub fn drmModeFreeObjectProperties(ptr: drmModeObjectPropertiesPtr);
4142}
4143unsafe extern "C" {
4144 pub fn drmModeObjectSetProperty(
4145 fd: ::core::ffi::c_int,
4146 object_id: u32,
4147 object_type: u32,
4148 property_id: u32,
4149 value: u64,
4150 ) -> ::core::ffi::c_int;
4151}
4152#[repr(C)]
4153#[derive(Debug, Copy, Clone)]
4154pub struct _drmModeAtomicReq {
4155 _unused: [u8; 0],
4156}
4157pub type drmModeAtomicReq = _drmModeAtomicReq;
4158pub type drmModeAtomicReqPtr = *mut _drmModeAtomicReq;
4159unsafe extern "C" {
4160 pub fn drmModeAtomicAlloc() -> drmModeAtomicReqPtr;
4161}
4162unsafe extern "C" {
4163 pub fn drmModeAtomicDuplicate(req: drmModeAtomicReqPtr) -> drmModeAtomicReqPtr;
4164}
4165unsafe extern "C" {
4166 pub fn drmModeAtomicMerge(
4167 base: drmModeAtomicReqPtr,
4168 augment: drmModeAtomicReqPtr,
4169 ) -> ::core::ffi::c_int;
4170}
4171unsafe extern "C" {
4172 pub fn drmModeAtomicFree(req: drmModeAtomicReqPtr);
4173}
4174unsafe extern "C" {
4175 pub fn drmModeAtomicGetCursor(req: drmModeAtomicReqPtr) -> ::core::ffi::c_int;
4176}
4177unsafe extern "C" {
4178 pub fn drmModeAtomicSetCursor(req: drmModeAtomicReqPtr, cursor: ::core::ffi::c_int);
4179}
4180unsafe extern "C" {
4181 pub fn drmModeAtomicAddProperty(
4182 req: drmModeAtomicReqPtr,
4183 object_id: u32,
4184 property_id: u32,
4185 value: u64,
4186 ) -> ::core::ffi::c_int;
4187}
4188unsafe extern "C" {
4189 pub fn drmModeAtomicCommit(
4190 fd: ::core::ffi::c_int,
4191 req: drmModeAtomicReqPtr,
4192 flags: u32,
4193 user_data: *mut ::core::ffi::c_void,
4194 ) -> ::core::ffi::c_int;
4195}
4196unsafe extern "C" {
4197 pub fn drmModeCreatePropertyBlob(
4198 fd: ::core::ffi::c_int,
4199 data: *const ::core::ffi::c_void,
4200 size: usize,
4201 id: *mut u32,
4202 ) -> ::core::ffi::c_int;
4203}
4204unsafe extern "C" {
4205 pub fn drmModeDestroyPropertyBlob(fd: ::core::ffi::c_int, id: u32) -> ::core::ffi::c_int;
4206}
4207unsafe extern "C" {
4208 pub fn drmModeCreateLease(
4209 fd: ::core::ffi::c_int,
4210 objects: *const u32,
4211 num_objects: ::core::ffi::c_int,
4212 flags: ::core::ffi::c_int,
4213 lessee_id: *mut u32,
4214 ) -> ::core::ffi::c_int;
4215}
4216#[repr(C)]
4217#[derive(Debug)]
4218pub struct drmModeLesseeList {
4219 pub count: u32,
4220 pub lessees: __IncompleteArrayField<u32>,
4221}
4222pub type drmModeLesseeListRes = drmModeLesseeList;
4223pub type drmModeLesseeListPtr = *mut drmModeLesseeList;
4224unsafe extern "C" {
4225 pub fn drmModeListLessees(fd: ::core::ffi::c_int) -> drmModeLesseeListPtr;
4226}
4227#[repr(C)]
4228#[derive(Debug)]
4229pub struct drmModeObjectList {
4230 pub count: u32,
4231 pub objects: __IncompleteArrayField<u32>,
4232}
4233pub type drmModeObjectListRes = drmModeObjectList;
4234pub type drmModeObjectListPtr = *mut drmModeObjectList;
4235unsafe extern "C" {
4236 pub fn drmModeGetLease(fd: ::core::ffi::c_int) -> drmModeObjectListPtr;
4237}
4238unsafe extern "C" {
4239 pub fn drmModeRevokeLease(fd: ::core::ffi::c_int, lessee_id: u32) -> ::core::ffi::c_int;
4240}
4241unsafe extern "C" {
4242 #[doc = " Get a string describing a connector type.\n\n NULL is returned if the connector type is unsupported. Callers should handle\n this gracefully, e.g. by falling back to \"Unknown\" or printing the raw value."]
4243 pub fn drmModeGetConnectorTypeName(connector_type: u32) -> *const ::core::ffi::c_char;
4244}
4245unsafe extern "C" {
4246 #[doc = " Create a dumb buffer.\n\n Given a width, height and bits-per-pixel, the kernel will return a buffer\n handle, pitch and size. The flags must be zero.\n\n Returns 0 on success, negative errno on error."]
4247 pub fn drmModeCreateDumbBuffer(
4248 fd: ::core::ffi::c_int,
4249 width: u32,
4250 height: u32,
4251 bpp: u32,
4252 flags: u32,
4253 handle: *mut u32,
4254 pitch: *mut u32,
4255 size: *mut u64,
4256 ) -> ::core::ffi::c_int;
4257}
4258unsafe extern "C" {
4259 #[doc = " Destroy a dumb buffer.\n\n Returns 0 on success, negative errno on error."]
4260 pub fn drmModeDestroyDumbBuffer(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
4261}
4262unsafe extern "C" {
4263 #[doc = " Prepare a dumb buffer for mapping.\n\n The kernel returns an offset which can be used as an argument to mmap(2) on\n the DRM FD.\n\n Returns 0 on success, negative errno on error."]
4264 pub fn drmModeMapDumbBuffer(
4265 fd: ::core::ffi::c_int,
4266 handle: u32,
4267 offset: *mut u64,
4268 ) -> ::core::ffi::c_int;
4269}
4270#[doc = " GEM flink name (needs DRM authentication, used by DRI2)"]
4271pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_gem_flink_name: amdgpu_bo_handle_type = 0;
4272#[doc = " KMS handle which is used by all driver ioctls"]
4273pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_kms: amdgpu_bo_handle_type = 1;
4274#[doc = " DMA-buf fd handle"]
4275pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_dma_buf_fd: amdgpu_bo_handle_type = 2;
4276#[doc = " Deprecated in favour of and same behaviour as\n amdgpu_bo_handle_type_kms, use that instead of this"]
4277pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_kms_noimport: amdgpu_bo_handle_type = 3;
4278#[doc = " Enum describing possible handle types\n\n \\sa amdgpu_bo_import, amdgpu_bo_export"]
4279pub type amdgpu_bo_handle_type = ::core::ffi::c_uint;
4280#[doc = " Allocate from \"normal\"/general range"]
4281pub const amdgpu_gpu_va_range_amdgpu_gpu_va_range_general: amdgpu_gpu_va_range = 0;
4282#[doc = " Define known types of GPU VM VA ranges"]
4283pub type amdgpu_gpu_va_range = ::core::ffi::c_uint;
4284pub const amdgpu_sw_info_amdgpu_sw_info_address32_hi: amdgpu_sw_info = 0;
4285pub type amdgpu_sw_info = ::core::ffi::c_uint;
4286#[repr(C)]
4287#[derive(Debug, Copy, Clone)]
4288pub struct amdgpu_device {
4289 _unused: [u8; 0],
4290}
4291#[doc = " Define opaque pointer to context associated with fd.\n This context will be returned as the result of\n \"initialize\" function and should be pass as the first\n parameter to any API call"]
4292pub type amdgpu_device_handle = *mut amdgpu_device;
4293#[repr(C)]
4294#[derive(Debug, Copy, Clone)]
4295pub struct amdgpu_context {
4296 _unused: [u8; 0],
4297}
4298#[doc = " Define GPU Context type as pointer to opaque structure\n Example of GPU Context is the \"rendering\" context associated\n with OpenGL context (glCreateContext)"]
4299pub type amdgpu_context_handle = *mut amdgpu_context;
4300#[repr(C)]
4301#[derive(Debug, Copy, Clone)]
4302pub struct amdgpu_bo {
4303 _unused: [u8; 0],
4304}
4305#[doc = " Define handle for amdgpu resources: buffer, GDS, etc."]
4306pub type amdgpu_bo_handle = *mut amdgpu_bo;
4307#[repr(C)]
4308#[derive(Debug, Copy, Clone)]
4309pub struct amdgpu_bo_list {
4310 _unused: [u8; 0],
4311}
4312#[doc = " Define handle for list of BOs"]
4313pub type amdgpu_bo_list_handle = *mut amdgpu_bo_list;
4314#[repr(C)]
4315#[derive(Debug, Copy, Clone)]
4316pub struct amdgpu_va {
4317 _unused: [u8; 0],
4318}
4319#[doc = " Define handle to be used to work with VA allocated ranges"]
4320pub type amdgpu_va_handle = *mut amdgpu_va;
4321#[repr(C)]
4322#[derive(Debug, Copy, Clone)]
4323pub struct amdgpu_va_manager {
4324 _unused: [u8; 0],
4325}
4326#[doc = " Define handle dealing with VA allocation. An amdgpu_device\n owns one of these, but they can also be used without a device."]
4327pub type amdgpu_va_manager_handle = *mut amdgpu_va_manager;
4328#[repr(C)]
4329#[derive(Debug, Copy, Clone)]
4330pub struct amdgpu_semaphore {
4331 _unused: [u8; 0],
4332}
4333#[doc = " Define handle for semaphore"]
4334pub type amdgpu_semaphore_handle = *mut amdgpu_semaphore;
4335#[doc = " Structure describing memory allocation request\n\n \\sa amdgpu_bo_alloc()"]
4336#[repr(C)]
4337#[derive(Debug, Copy, Clone)]
4338pub struct amdgpu_bo_alloc_request {
4339 #[doc = " Allocation request. It must be aligned correctly."]
4340 pub alloc_size: u64,
4341 #[doc = " It may be required to have some specific alignment requirements\n for physical back-up storage (e.g. for displayable surface).\n If 0 there is no special alignment requirement"]
4342 pub phys_alignment: u64,
4343 #[doc = " UMD should specify where to allocate memory and how it\n will be accessed by the CPU."]
4344 pub preferred_heap: u32,
4345 #[doc = " Additional flags passed on allocation"]
4346 pub flags: u64,
4347}
4348#[doc = " Special UMD specific information associated with buffer.\n\n It may be need to pass some buffer charactersitic as part\n of buffer sharing. Such information are defined UMD and\n opaque for libdrm_amdgpu as well for kernel driver.\n\n \\sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,\n amdgpu_bo_import(), amdgpu_bo_export"]
4349#[repr(C)]
4350#[derive(Debug, Copy, Clone)]
4351pub struct amdgpu_bo_metadata {
4352 #[doc = " Special flag associated with surface"]
4353 pub flags: u64,
4354 #[doc = " ASIC-specific tiling information (also used by DCE).\n The encoding is defined by the AMDGPU_TILING_* definitions."]
4355 pub tiling_info: u64,
4356 #[doc = " Size of metadata associated with the buffer, in bytes."]
4357 pub size_metadata: u32,
4358 #[doc = " UMD specific metadata. Opaque for kernel"]
4359 pub umd_metadata: [u32; 64usize],
4360}
4361#[doc = " Structure describing allocated buffer. Client may need\n to query such information as part of 'sharing' buffers mechanism\n\n \\sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),\n amdgpu_bo_import(), amdgpu_bo_export()"]
4362#[repr(C)]
4363#[derive(Debug, Copy, Clone)]
4364pub struct amdgpu_bo_info {
4365 #[doc = " Allocated memory size"]
4366 pub alloc_size: u64,
4367 #[doc = " It may be required to have some specific alignment requirements\n for physical back-up storage."]
4368 pub phys_alignment: u64,
4369 #[doc = " Heap where to allocate memory."]
4370 pub preferred_heap: u32,
4371 #[doc = " Additional allocation flags."]
4372 pub alloc_flags: u64,
4373 #[doc = " Metadata associated with buffer if any."]
4374 pub metadata: amdgpu_bo_metadata,
4375}
4376#[doc = " Structure with information about \"imported\" buffer\n\n \\sa amdgpu_bo_import()\n"]
4377#[repr(C)]
4378#[derive(Debug, Copy, Clone)]
4379pub struct amdgpu_bo_import_result {
4380 #[doc = " Handle of memory/buffer to use"]
4381 pub buf_handle: amdgpu_bo_handle,
4382 #[doc = " Buffer size"]
4383 pub alloc_size: u64,
4384}
4385#[doc = " Structure to describe GDS partitioning information.\n \\note OA and GWS resources are asscoiated with GDS partition\n\n \\sa amdgpu_gpu_resource_query_gds_info"]
4386#[repr(C)]
4387#[derive(Debug, Copy, Clone)]
4388pub struct amdgpu_gds_resource_info {
4389 pub gds_gfx_partition_size: u32,
4390 pub compute_partition_size: u32,
4391 pub gds_total_size: u32,
4392 pub gws_per_gfx_partition: u32,
4393 pub gws_per_compute_partition: u32,
4394 pub oa_per_gfx_partition: u32,
4395 pub oa_per_compute_partition: u32,
4396}
4397#[doc = " Structure describing CS fence\n\n \\sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()"]
4398#[repr(C)]
4399#[derive(Debug, Copy, Clone)]
4400pub struct amdgpu_cs_fence {
4401 #[doc = " In which context IB was sent to execution"]
4402 pub context: amdgpu_context_handle,
4403 #[doc = " To which HW IP type the fence belongs"]
4404 pub ip_type: u32,
4405 #[doc = " IP instance index if there are several IPs of the same type."]
4406 pub ip_instance: u32,
4407 #[doc = " Ring index of the HW IP"]
4408 pub ring: u32,
4409 #[doc = " Specify fence for which we need to check submission status."]
4410 pub fence: u64,
4411}
4412#[doc = " Structure describing IB\n\n \\sa amdgpu_cs_request, amdgpu_cs_submit()"]
4413#[repr(C)]
4414#[derive(Debug, Copy, Clone)]
4415pub struct amdgpu_cs_ib_info {
4416 #[doc = " Special flags"]
4417 pub flags: u64,
4418 #[doc = " Virtual MC address of the command buffer"]
4419 pub ib_mc_address: u64,
4420 #[doc = " Size of Command Buffer to be submitted.\n - The size is in units of dwords (4 bytes).\n - Could be 0"]
4421 pub size: u32,
4422}
4423#[doc = " Structure describing fence information\n\n \\sa amdgpu_cs_request, amdgpu_cs_query_fence,\n amdgpu_cs_submit(), amdgpu_cs_query_fence_status()"]
4424#[repr(C)]
4425#[derive(Debug, Copy, Clone)]
4426pub struct amdgpu_cs_fence_info {
4427 #[doc = " buffer object for the fence"]
4428 pub handle: amdgpu_bo_handle,
4429 #[doc = " fence offset in the unit of sizeof(uint64_t)"]
4430 pub offset: u64,
4431}
4432#[doc = " Structure describing submission request\n\n \\note We could have several IBs as packet. e.g. CE, CE, DE case for gfx\n\n \\sa amdgpu_cs_submit()"]
4433#[repr(C)]
4434#[derive(Debug, Copy, Clone)]
4435pub struct amdgpu_cs_request {
4436 #[doc = " Specify flags with additional information"]
4437 pub flags: u64,
4438 #[doc = " Specify HW IP block type to which to send the IB."]
4439 pub ip_type: ::core::ffi::c_uint,
4440 #[doc = " IP instance index if there are several IPs of the same type."]
4441 pub ip_instance: ::core::ffi::c_uint,
4442 #[doc = " Specify ring index of the IP. We could have several rings\n in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1."]
4443 pub ring: u32,
4444 #[doc = " List handle with resources used by this request."]
4445 pub resources: amdgpu_bo_list_handle,
4446 #[doc = " Number of dependencies this Command submission needs to\n wait for before starting execution."]
4447 pub number_of_dependencies: u32,
4448 #[doc = " Array of dependencies which need to be met before\n execution can start."]
4449 pub dependencies: *mut amdgpu_cs_fence,
4450 #[doc = " Number of IBs to submit in the field ibs."]
4451 pub number_of_ibs: u32,
4452 #[doc = " IBs to submit. Those IBs will be submit together as single entity"]
4453 pub ibs: *mut amdgpu_cs_ib_info,
4454 #[doc = " The returned sequence number for the command submission"]
4455 pub seq_no: u64,
4456 #[doc = " The fence information"]
4457 pub fence_info: amdgpu_cs_fence_info,
4458}
4459#[doc = " Structure which provide information about GPU VM MC Address space\n alignments requirements\n\n \\sa amdgpu_query_buffer_size_alignment"]
4460#[repr(C)]
4461#[derive(Debug, Copy, Clone)]
4462pub struct amdgpu_buffer_size_alignments {
4463 #[doc = " Size alignment requirement for allocation in\n local memory"]
4464 pub size_local: u64,
4465 #[doc = " Size alignment requirement for allocation in remote memory"]
4466 pub size_remote: u64,
4467}
4468#[doc = " Structure which provide information about heap\n\n \\sa amdgpu_query_heap_info()\n"]
4469#[repr(C)]
4470#[derive(Debug, Copy, Clone)]
4471pub struct amdgpu_heap_info {
4472 #[doc = " Theoretical max. available memory in the given heap"]
4473 pub heap_size: u64,
4474 #[doc = " Number of bytes allocated in the heap. This includes all processes\n and private allocations in the kernel. It changes when new buffers\n are allocated, freed, and moved. It cannot be larger than\n heap_size."]
4475 pub heap_usage: u64,
4476 #[doc = " Theoretical possible max. size of buffer which\n could be allocated in the given heap"]
4477 pub max_allocation: u64,
4478}
4479#[doc = " Describe GPU h/w info needed for UMD correct initialization\n\n \\sa amdgpu_query_gpu_info()"]
4480#[repr(C)]
4481#[derive(Debug, Copy, Clone)]
4482pub struct amdgpu_gpu_info {
4483 #[doc = " Asic id"]
4484 pub asic_id: u32,
4485 #[doc = " Chip revision"]
4486 pub chip_rev: u32,
4487 #[doc = " Chip external revision"]
4488 pub chip_external_rev: u32,
4489 #[doc = " Family ID"]
4490 pub family_id: u32,
4491 #[doc = " Special flags"]
4492 pub ids_flags: u64,
4493 #[doc = " max engine clock"]
4494 pub max_engine_clk: u64,
4495 #[doc = " max memory clock"]
4496 pub max_memory_clk: u64,
4497 #[doc = " number of shader engines"]
4498 pub num_shader_engines: u32,
4499 #[doc = " number of shader arrays per engine"]
4500 pub num_shader_arrays_per_engine: u32,
4501 #[doc = " Number of available good shader pipes"]
4502 pub avail_quad_shader_pipes: u32,
4503 #[doc = " Max. number of shader pipes.(including good and bad pipes"]
4504 pub max_quad_shader_pipes: u32,
4505 #[doc = " Number of parameter cache entries per shader quad pipe"]
4506 pub cache_entries_per_quad_pipe: u32,
4507 #[doc = " Number of available graphics context"]
4508 pub num_hw_gfx_contexts: u32,
4509 #[doc = " Number of render backend pipes"]
4510 pub rb_pipes: u32,
4511 #[doc = " Enabled render backend pipe mask"]
4512 pub enabled_rb_pipes_mask: u32,
4513 #[doc = " Frequency of GPU Counter"]
4514 pub gpu_counter_freq: u32,
4515 #[doc = " CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE"]
4516 pub backend_disable: [u32; 4usize],
4517 #[doc = " Value of MC_ARB_RAMCFG register"]
4518 pub mc_arb_ramcfg: u32,
4519 #[doc = " Value of GB_ADDR_CONFIG"]
4520 pub gb_addr_cfg: u32,
4521 #[doc = " Values of the GB_TILE_MODE0..31 registers"]
4522 pub gb_tile_mode: [u32; 32usize],
4523 #[doc = " Values of GB_MACROTILE_MODE0..15 registers"]
4524 pub gb_macro_tile_mode: [u32; 16usize],
4525 #[doc = " Value of PA_SC_RASTER_CONFIG register per SE"]
4526 pub pa_sc_raster_cfg: [u32; 4usize],
4527 #[doc = " Value of PA_SC_RASTER_CONFIG_1 register per SE"]
4528 pub pa_sc_raster_cfg1: [u32; 4usize],
4529 pub cu_active_number: u32,
4530 pub cu_ao_mask: u32,
4531 pub cu_bitmap: [[u32; 4usize]; 4usize],
4532 pub vram_type: u32,
4533 pub vram_bit_width: u32,
4534 #[doc = " constant engine ram size"]
4535 pub ce_ram_size: u32,
4536 pub vce_harvest_config: u32,
4537 pub pci_rev_id: u32,
4538}
4539unsafe extern "C" {
4540 #[doc = " \\param fd - \\c [in] File descriptor for AMD GPU device\n received previously as the result of\n e.g. drmOpen() call.\n For legacy fd type, the DRI2/DRI3\n authentication should be done before\n calling this function.\n \\param major_version - \\c [out] Major version of library. It is assumed\n that adding new functionality will cause\n increase in major version\n \\param minor_version - \\c [out] Minor version of library\n \\param device_handle - \\c [out] Pointer to opaque context which should\n be passed as the first parameter on each\n API call\n\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n\n \\sa amdgpu_device_deinitialize()"]
4541 pub fn amdgpu_device_initialize(
4542 fd: ::core::ffi::c_int,
4543 major_version: *mut u32,
4544 minor_version: *mut u32,
4545 device_handle: *mut amdgpu_device_handle,
4546 ) -> ::core::ffi::c_int;
4547}
4548unsafe extern "C" {
4549 #[doc = " Same as amdgpu_device_initialize() except when deduplicate_device\n is false *and* fd points to a device that was already initialized.\n In this case, amdgpu_device_initialize would return the same\n amdgpu_device_handle while here amdgpu_device_initialize2 would\n return a new handle.\n amdgpu_device_initialize() should be preferred in most situations;\n the only use-case where not-deduplicating devices make sense is\n when one wants to have isolated device handles in the same process."]
4550 pub fn amdgpu_device_initialize2(
4551 fd: ::core::ffi::c_int,
4552 deduplicate_device: bool,
4553 major_version: *mut u32,
4554 minor_version: *mut u32,
4555 device_handle: *mut amdgpu_device_handle,
4556 ) -> ::core::ffi::c_int;
4557}
4558unsafe extern "C" {
4559 #[doc = " When access to such library does not needed any more the special\n function must be call giving opportunity to clean up any\n resources if needed.\n\n \\param device_handle - \\c [in] Context associated with file\n descriptor for AMD GPU device\n received previously as the\n result e.g. of drmOpen() call.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_device_initialize()"]
4560 pub fn amdgpu_device_deinitialize(device_handle: amdgpu_device_handle) -> ::core::ffi::c_int;
4561}
4562unsafe extern "C" {
4563 #[doc = " Allocate memory to be used by UMD for GPU related operations\n\n \\param dev\t\t - \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param alloc_buffer - \\c [in] Pointer to the structure describing an\n\t\t\t\t allocation request\n \\param buf_handle\t- \\c [out] Allocated buffer handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_free()"]
4564 pub fn amdgpu_bo_alloc(
4565 dev: amdgpu_device_handle,
4566 alloc_buffer: *mut amdgpu_bo_alloc_request,
4567 buf_handle: *mut amdgpu_bo_handle,
4568 ) -> ::core::ffi::c_int;
4569}
4570unsafe extern "C" {
4571 #[doc = " Associate opaque data with buffer to be queried by another UMD\n\n \\param dev\t - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param buf_handle - \\c [in] Buffer handle\n \\param info - \\c [in] Metadata to associated with buffer\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4572 pub fn amdgpu_bo_set_metadata(
4573 buf_handle: amdgpu_bo_handle,
4574 info: *mut amdgpu_bo_metadata,
4575 ) -> ::core::ffi::c_int;
4576}
4577unsafe extern "C" {
4578 #[doc = " Query buffer information including metadata previusly associated with\n buffer.\n\n \\param dev\t - \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param buf_handle - \\c [in] Buffer handle\n \\param info - \\c [out] Structure describing buffer\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()"]
4579 pub fn amdgpu_bo_query_info(
4580 buf_handle: amdgpu_bo_handle,
4581 info: *mut amdgpu_bo_info,
4582 ) -> ::core::ffi::c_int;
4583}
4584unsafe extern "C" {
4585 #[doc = " Allow others to get access to buffer\n\n \\param dev\t\t - \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param buf_handle - \\c [in] Buffer handle\n \\param type - \\c [in] Type of handle requested\n \\param shared_handle - \\c [out] Special \"shared\" handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_import()"]
4586 pub fn amdgpu_bo_export(
4587 buf_handle: amdgpu_bo_handle,
4588 type_: amdgpu_bo_handle_type,
4589 shared_handle: *mut u32,
4590 ) -> ::core::ffi::c_int;
4591}
4592unsafe extern "C" {
4593 #[doc = " Request access to \"shared\" buffer\n\n \\param dev\t\t - \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param type\t - \\c [in] Type of handle requested\n \\param shared_handle - \\c [in] Shared handle received as result \"import\"\n\t\t\t\t operation\n \\param output - \\c [out] Pointer to structure with information\n\t\t\t\t about imported buffer\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\note Buffer must be \"imported\" only using new \"fd\" (different from\n\t one used by \"exporter\").\n\n \\sa amdgpu_bo_export()"]
4594 pub fn amdgpu_bo_import(
4595 dev: amdgpu_device_handle,
4596 type_: amdgpu_bo_handle_type,
4597 shared_handle: u32,
4598 output: *mut amdgpu_bo_import_result,
4599 ) -> ::core::ffi::c_int;
4600}
4601unsafe extern "C" {
4602 #[doc = " Request GPU access to user allocated memory e.g. via \"malloc\"\n\n \\param dev - [in] Device handle. See #amdgpu_device_initialize()\n \\param cpu - [in] CPU address of user allocated memory which we\n want to map to GPU address space (make GPU accessible)\n (This address must be correctly aligned).\n \\param size - [in] Size of allocation (must be correctly aligned)\n \\param buf_handle - [out] Buffer handle for the userptr memory\n resource on submission and be used in other operations.\n\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\note\n This call doesn't guarantee that such memory will be persistently\n \"locked\" / make non-pageable. The purpose of this call is to provide\n opportunity for GPU get access to this resource during submission.\n\n The maximum amount of memory which could be mapped in this call depends\n if overcommit is disabled or not. If overcommit is disabled than the max.\n amount of memory to be pinned will be limited by left \"free\" size in total\n amount of memory which could be locked simultaneously (\"GART\" size).\n\n Supported (theoretical) max. size of mapping is restricted only by\n \"GART\" size.\n\n It is responsibility of caller to correctly specify access rights\n on VA assignment."]
4603 pub fn amdgpu_create_bo_from_user_mem(
4604 dev: amdgpu_device_handle,
4605 cpu: *mut ::core::ffi::c_void,
4606 size: u64,
4607 buf_handle: *mut amdgpu_bo_handle,
4608 ) -> ::core::ffi::c_int;
4609}
4610unsafe extern "C" {
4611 #[doc = " Validate if the user memory comes from BO\n\n \\param dev - [in] Device handle. See #amdgpu_device_initialize()\n \\param cpu - [in] CPU address of user allocated memory which we\n want to map to GPU address space (make GPU accessible)\n (This address must be correctly aligned).\n \\param size - [in] Size of allocation (must be correctly aligned)\n \\param buf_handle - [out] Buffer handle for the userptr memory\n if the user memory is not from BO, the buf_handle will be NULL.\n \\param offset_in_bo - [out] offset in this BO for this user memory\n\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4612 pub fn amdgpu_find_bo_by_cpu_mapping(
4613 dev: amdgpu_device_handle,
4614 cpu: *mut ::core::ffi::c_void,
4615 size: u64,
4616 buf_handle: *mut amdgpu_bo_handle,
4617 offset_in_bo: *mut u64,
4618 ) -> ::core::ffi::c_int;
4619}
4620unsafe extern "C" {
4621 #[doc = " Free previously allocated memory\n\n \\param dev\t - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param buf_handle - \\c [in] Buffer handle to free\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\note In the case of memory shared between different applications all\n\t resources will be “physically” freed only all such applications\n\t will be terminated\n \\note If is UMD responsibility to ‘free’ buffer only when there is no\n\t more GPU access\n\n \\sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()"]
4622 pub fn amdgpu_bo_free(buf_handle: amdgpu_bo_handle) -> ::core::ffi::c_int;
4623}
4624unsafe extern "C" {
4625 #[doc = " Increase the reference count of a buffer object\n\n \\param bo - \\c [in] Buffer object handle to increase the reference count\n\n \\sa amdgpu_bo_alloc(), amdgpu_bo_free()"]
4626 pub fn amdgpu_bo_inc_ref(bo: amdgpu_bo_handle);
4627}
4628unsafe extern "C" {
4629 #[doc = " Request CPU access to GPU accessible memory\n\n \\param buf_handle - \\c [in] Buffer handle\n \\param cpu - \\c [out] CPU address to be used for access\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_cpu_unmap()"]
4630 pub fn amdgpu_bo_cpu_map(
4631 buf_handle: amdgpu_bo_handle,
4632 cpu: *mut *mut ::core::ffi::c_void,
4633 ) -> ::core::ffi::c_int;
4634}
4635unsafe extern "C" {
4636 #[doc = " Release CPU access to GPU memory\n\n \\param buf_handle - \\c [in] Buffer handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_cpu_map()"]
4637 pub fn amdgpu_bo_cpu_unmap(buf_handle: amdgpu_bo_handle) -> ::core::ffi::c_int;
4638}
4639unsafe extern "C" {
4640 #[doc = " Wait until a buffer is not used by the device.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param buf_handle - \\c [in] Buffer handle.\n \\param timeout_ns - Timeout in nanoseconds.\n \\param buffer_busy - 0 if buffer is idle, all GPU access was completed\n and no GPU access is scheduled.\n 1 GPU access is in fly or scheduled\n\n \\return 0 - on success\n <0 - Negative POSIX Error code"]
4641 pub fn amdgpu_bo_wait_for_idle(
4642 buf_handle: amdgpu_bo_handle,
4643 timeout_ns: u64,
4644 buffer_busy: *mut bool,
4645 ) -> ::core::ffi::c_int;
4646}
4647unsafe extern "C" {
4648 #[doc = " Creates a BO list handle for command submission.\n\n \\param dev\t\t\t- \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param number_of_buffers\t- \\c [in] Number of BOs in the list\n \\param buffers\t\t- \\c [in] List of BO handles\n \\param result\t\t- \\c [out] Created BO list handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()"]
4649 pub fn amdgpu_bo_list_create_raw(
4650 dev: amdgpu_device_handle,
4651 number_of_buffers: u32,
4652 buffers: *mut drm_amdgpu_bo_list_entry,
4653 result: *mut u32,
4654 ) -> ::core::ffi::c_int;
4655}
4656unsafe extern "C" {
4657 #[doc = " Destroys a BO list handle.\n\n \\param bo_list\t- \\c [in] BO list handle.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()"]
4658 pub fn amdgpu_bo_list_destroy_raw(
4659 dev: amdgpu_device_handle,
4660 bo_list: u32,
4661 ) -> ::core::ffi::c_int;
4662}
4663unsafe extern "C" {
4664 #[doc = " Creates a BO list handle for command submission.\n\n \\param dev\t\t\t- \\c [in] Device handle.\n\t\t\t\t See #amdgpu_device_initialize()\n \\param number_of_resources\t- \\c [in] Number of BOs in the list\n \\param resources\t\t- \\c [in] List of BO handles\n \\param resource_prios\t- \\c [in] Optional priority for each handle\n \\param result\t\t- \\c [out] Created BO list handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_destroy()"]
4665 pub fn amdgpu_bo_list_create(
4666 dev: amdgpu_device_handle,
4667 number_of_resources: u32,
4668 resources: *mut amdgpu_bo_handle,
4669 resource_prios: *mut u8,
4670 result: *mut amdgpu_bo_list_handle,
4671 ) -> ::core::ffi::c_int;
4672}
4673unsafe extern "C" {
4674 #[doc = " Destroys a BO list handle.\n\n \\param handle\t- \\c [in] BO list handle.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_create()"]
4675 pub fn amdgpu_bo_list_destroy(handle: amdgpu_bo_list_handle) -> ::core::ffi::c_int;
4676}
4677unsafe extern "C" {
4678 #[doc = " Update resources for existing BO list\n\n \\param handle - \\c [in] BO list handle\n \\param number_of_resources - \\c [in] Number of BOs in the list\n \\param resources - \\c [in] List of BO handles\n \\param resource_prios - \\c [in] Optional priority for each handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_update()"]
4679 pub fn amdgpu_bo_list_update(
4680 handle: amdgpu_bo_list_handle,
4681 number_of_resources: u32,
4682 resources: *mut amdgpu_bo_handle,
4683 resource_prios: *mut u8,
4684 ) -> ::core::ffi::c_int;
4685}
4686unsafe extern "C" {
4687 #[doc = " Create GPU execution Context\n\n For the purpose of GPU Scheduler and GPU Robustness extensions it is\n necessary to have information/identify rendering/compute contexts.\n It also may be needed to associate some specific requirements with such\n contexts. Kernel driver will guarantee that submission from the same\n context will always be executed in order (first come, first serve).\n\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param priority - \\c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*\n \\param context - \\c [out] GPU Context handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_cs_ctx_free()"]
4688 pub fn amdgpu_cs_ctx_create2(
4689 dev: amdgpu_device_handle,
4690 priority: u32,
4691 context: *mut amdgpu_context_handle,
4692 ) -> ::core::ffi::c_int;
4693}
4694unsafe extern "C" {
4695 #[doc = " Create GPU execution Context\n\n Refer to amdgpu_cs_ctx_create2 for full documentation. This call\n is missing the priority parameter.\n\n \\sa amdgpu_cs_ctx_create2()"]
4696 pub fn amdgpu_cs_ctx_create(
4697 dev: amdgpu_device_handle,
4698 context: *mut amdgpu_context_handle,
4699 ) -> ::core::ffi::c_int;
4700}
4701unsafe extern "C" {
4702 #[doc = " Destroy GPU execution context when not needed any more\n\n \\param context - \\c [in] GPU Context handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_cs_ctx_create()"]
4703 pub fn amdgpu_cs_ctx_free(context: amdgpu_context_handle) -> ::core::ffi::c_int;
4704}
4705unsafe extern "C" {
4706 #[doc = " Override the submission priority for the given context using a master fd.\n\n \\param dev - \\c [in] device handle\n \\param context - \\c [in] context handle for context id\n \\param master_fd - \\c [in] The master fd to authorize the override.\n \\param priority - \\c [in] The priority to assign to the context.\n\n \\return 0 on success or a a negative Posix error code on failure."]
4707 pub fn amdgpu_cs_ctx_override_priority(
4708 dev: amdgpu_device_handle,
4709 context: amdgpu_context_handle,
4710 master_fd: ::core::ffi::c_int,
4711 priority: ::core::ffi::c_uint,
4712 ) -> ::core::ffi::c_int;
4713}
4714unsafe extern "C" {
4715 #[doc = " Set or query the stable power state for GPU profiling.\n\n \\param dev - \\c [in] device handle\n \\param op - \\c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE\n \\param flags - \\c [in] AMDGPU_CTX_STABLE_PSTATE_*\n \\param out_flags - \\c [out] output current stable pstate\n\n \\return 0 on success otherwise POSIX Error code."]
4716 pub fn amdgpu_cs_ctx_stable_pstate(
4717 context: amdgpu_context_handle,
4718 op: u32,
4719 flags: u32,
4720 out_flags: *mut u32,
4721 ) -> ::core::ffi::c_int;
4722}
4723unsafe extern "C" {
4724 #[doc = " Query reset state for the specific GPU Context\n\n \\param context - \\c [in] GPU Context handle\n \\param state - \\c [out] One of AMDGPU_CTX_*_RESET\n \\param hangs - \\c [out] Number of hangs caused by the context.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_cs_ctx_create()"]
4725 pub fn amdgpu_cs_query_reset_state(
4726 context: amdgpu_context_handle,
4727 state: *mut u32,
4728 hangs: *mut u32,
4729 ) -> ::core::ffi::c_int;
4730}
4731unsafe extern "C" {
4732 #[doc = " Query reset state for the specific GPU Context.\n\n \\param context - \\c [in] GPU Context handle\n \\param flags - \\c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_*\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_cs_ctx_create()"]
4733 pub fn amdgpu_cs_query_reset_state2(
4734 context: amdgpu_context_handle,
4735 flags: *mut u64,
4736 ) -> ::core::ffi::c_int;
4737}
4738unsafe extern "C" {
4739 #[doc = " Send request to submit command buffers to hardware.\n\n Kernel driver could use GPU Scheduler to make decision when physically\n sent this request to the hardware. Accordingly this request could be put\n in queue and sent for execution later. The only guarantee is that request\n from the same GPU context to the same ip:ip_instance:ring will be executed in\n order.\n\n The caller can specify the user fence buffer/location with the fence_info in the\n cs_request.The sequence number is returned via the 'seq_no' parameter\n in ibs_request structure.\n\n\n \\param dev\t\t - \\c [in] Device handle.\n\t\t\t\t\t See #amdgpu_device_initialize()\n \\param context - \\c [in] GPU Context\n \\param flags - \\c [in] Global submission flags\n \\param ibs_request - \\c [in/out] Pointer to submission requests.\n\t\t\t\t\t We could submit to the several\n\t\t\t\t\t engines/rings simulteniously as\n\t\t\t\t\t 'atomic' operation\n \\param number_of_requests - \\c [in] Number of submission requests\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\note It is required to pass correct resource list with buffer handles\n\t which will be accessible by command buffers from submission\n\t This will allow kernel driver to correctly implement \"paging\".\n\t Failure to do so will have unpredictable results.\n\n \\sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),\n amdgpu_cs_query_fence_status()"]
4740 pub fn amdgpu_cs_submit(
4741 context: amdgpu_context_handle,
4742 flags: u64,
4743 ibs_request: *mut amdgpu_cs_request,
4744 number_of_requests: u32,
4745 ) -> ::core::ffi::c_int;
4746}
4747unsafe extern "C" {
4748 #[doc = " Query status of Command Buffer Submission\n\n \\param fence - \\c [in] Structure describing fence to query\n \\param timeout_ns - \\c [in] Timeout value to wait\n \\param flags - \\c [in] Flags for the query\n \\param expired - \\c [out] If fence expired or not.\\n\n\t\t\t\t0 – if fence is not expired\\n\n\t\t\t\t!0 - otherwise\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\note If UMD wants only to check operation status and returned immediately\n\t then timeout value as 0 must be passed. In this case success will be\n\t returned in the case if submission was completed or timeout error\n\t code.\n\n \\sa amdgpu_cs_submit()"]
4749 pub fn amdgpu_cs_query_fence_status(
4750 fence: *mut amdgpu_cs_fence,
4751 timeout_ns: u64,
4752 flags: u64,
4753 expired: *mut u32,
4754 ) -> ::core::ffi::c_int;
4755}
4756unsafe extern "C" {
4757 #[doc = " Wait for multiple fences\n\n \\param fences - \\c [in] The fence array to wait\n \\param fence_count - \\c [in] The fence count\n \\param wait_all - \\c [in] If true, wait all fences to be signaled,\n otherwise, wait at least one fence\n \\param timeout_ns - \\c [in] The timeout to wait, in nanoseconds\n \\param status - \\c [out] '1' for signaled, '0' for timeout\n \\param first - \\c [out] the index of the first signaled fence from @fences\n\n \\return 0 on success\n <0 - Negative POSIX Error code\n\n \\note Currently it supports only one amdgpu_device. All fences come from\n the same amdgpu_device with the same fd."]
4758 pub fn amdgpu_cs_wait_fences(
4759 fences: *mut amdgpu_cs_fence,
4760 fence_count: u32,
4761 wait_all: bool,
4762 timeout_ns: u64,
4763 status: *mut u32,
4764 first: *mut u32,
4765 ) -> ::core::ffi::c_int;
4766}
4767unsafe extern "C" {
4768 #[doc = " Query allocation size alignments\n\n UMD should query information about GPU VM MC size alignments requirements\n to be able correctly choose required allocation size and implement\n internal optimization if needed.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param info - \\c [out] Pointer to structure to get size alignment\n\t\t\t requirements\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4769 pub fn amdgpu_query_buffer_size_alignment(
4770 dev: amdgpu_device_handle,
4771 info: *mut amdgpu_buffer_size_alignments,
4772 ) -> ::core::ffi::c_int;
4773}
4774unsafe extern "C" {
4775 #[doc = " Query firmware versions\n\n \\param dev\t - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param fw_type - \\c [in] AMDGPU_INFO_FW_*\n \\param ip_instance - \\c [in] Index of the IP block of the same type.\n \\param index - \\c [in] Index of the engine. (for SDMA and MEC)\n \\param version - \\c [out] Pointer to to the \"version\" return value\n \\param feature - \\c [out] Pointer to to the \"feature\" return value\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4776 pub fn amdgpu_query_firmware_version(
4777 dev: amdgpu_device_handle,
4778 fw_type: ::core::ffi::c_uint,
4779 ip_instance: ::core::ffi::c_uint,
4780 index: ::core::ffi::c_uint,
4781 version: *mut u32,
4782 feature: *mut u32,
4783 ) -> ::core::ffi::c_int;
4784}
4785unsafe extern "C" {
4786 #[doc = " Query the number of HW IP instances of a certain type.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param type - \\c [in] Hardware IP block type = AMDGPU_HW_IP_*\n \\param count - \\c [out] Pointer to structure to get information\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4787 pub fn amdgpu_query_hw_ip_count(
4788 dev: amdgpu_device_handle,
4789 type_: ::core::ffi::c_uint,
4790 count: *mut u32,
4791 ) -> ::core::ffi::c_int;
4792}
4793unsafe extern "C" {
4794 #[doc = " Query engine information\n\n This query allows UMD to query information different engines and their\n capabilities.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param type - \\c [in] Hardware IP block type = AMDGPU_HW_IP_*\n \\param ip_instance - \\c [in] Index of the IP block of the same type.\n \\param info - \\c [out] Pointer to structure to get information\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4795 pub fn amdgpu_query_hw_ip_info(
4796 dev: amdgpu_device_handle,
4797 type_: ::core::ffi::c_uint,
4798 ip_instance: ::core::ffi::c_uint,
4799 info: *mut drm_amdgpu_info_hw_ip,
4800 ) -> ::core::ffi::c_int;
4801}
4802unsafe extern "C" {
4803 #[doc = " Query heap information\n\n This query allows UMD to query potentially available memory resources and\n adjust their logic if necessary.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param heap - \\c [in] Heap type\n \\param info - \\c [in] Pointer to structure to get needed information\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4804 pub fn amdgpu_query_heap_info(
4805 dev: amdgpu_device_handle,
4806 heap: u32,
4807 flags: u32,
4808 info: *mut amdgpu_heap_info,
4809 ) -> ::core::ffi::c_int;
4810}
4811unsafe extern "C" {
4812 #[doc = " Get the CRTC ID from the mode object ID\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param id - \\c [in] Mode object ID\n \\param result - \\c [in] Pointer to the CRTC ID\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4813 pub fn amdgpu_query_crtc_from_id(
4814 dev: amdgpu_device_handle,
4815 id: ::core::ffi::c_uint,
4816 result: *mut i32,
4817 ) -> ::core::ffi::c_int;
4818}
4819unsafe extern "C" {
4820 #[doc = " Query GPU H/w Info\n\n Query hardware specific information\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param heap - \\c [in] Heap type\n \\param info - \\c [in] Pointer to structure to get needed information\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4821 pub fn amdgpu_query_gpu_info(
4822 dev: amdgpu_device_handle,
4823 info: *mut amdgpu_gpu_info,
4824 ) -> ::core::ffi::c_int;
4825}
4826unsafe extern "C" {
4827 #[doc = " Query hardware or driver information.\n\n The return size is query-specific and depends on the \"info_id\" parameter.\n No more than \"size\" bytes is returned.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param info_id - \\c [in] AMDGPU_INFO_*\n \\param size - \\c [in] Size of the returned value.\n \\param value - \\c [out] Pointer to the return value.\n\n \\return 0 on success\\n\n <0 - Negative POSIX error code"]
4828 pub fn amdgpu_query_info(
4829 dev: amdgpu_device_handle,
4830 info_id: ::core::ffi::c_uint,
4831 size: ::core::ffi::c_uint,
4832 value: *mut ::core::ffi::c_void,
4833 ) -> ::core::ffi::c_int;
4834}
4835unsafe extern "C" {
4836 #[doc = " Query hardware or driver information.\n\n The return size is query-specific and depends on the \"info_id\" parameter.\n No more than \"size\" bytes is returned.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param info - \\c [in] amdgpu_sw_info_*\n \\param value - \\c [out] Pointer to the return value.\n\n \\return 0 on success\\n\n <0 - Negative POSIX error code"]
4837 pub fn amdgpu_query_sw_info(
4838 dev: amdgpu_device_handle,
4839 info: amdgpu_sw_info,
4840 value: *mut ::core::ffi::c_void,
4841 ) -> ::core::ffi::c_int;
4842}
4843unsafe extern "C" {
4844 #[doc = " Query information about GDS\n\n \\param dev\t - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param gds_info - \\c [out] Pointer to structure to get GDS information\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4845 pub fn amdgpu_query_gds_info(
4846 dev: amdgpu_device_handle,
4847 gds_info: *mut amdgpu_gds_resource_info,
4848 ) -> ::core::ffi::c_int;
4849}
4850unsafe extern "C" {
4851 #[doc = " Query information about sensor.\n\n The return size is query-specific and depends on the \"sensor_type\"\n parameter. No more than \"size\" bytes is returned.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param sensor_type - \\c [in] AMDGPU_INFO_SENSOR_*\n \\param size - \\c [in] Size of the returned value.\n \\param value - \\c [out] Pointer to the return value.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4852 pub fn amdgpu_query_sensor_info(
4853 dev: amdgpu_device_handle,
4854 sensor_type: ::core::ffi::c_uint,
4855 size: ::core::ffi::c_uint,
4856 value: *mut ::core::ffi::c_void,
4857 ) -> ::core::ffi::c_int;
4858}
4859unsafe extern "C" {
4860 #[doc = " Query information about video capabilities\n\n The return sizeof(struct drm_amdgpu_info_video_caps)\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param caps_type - \\c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE)\n \\param size - \\c [in] Size of the returned value.\n \\param value - \\c [out] Pointer to the return value.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4861 pub fn amdgpu_query_video_caps_info(
4862 dev: amdgpu_device_handle,
4863 cap_type: ::core::ffi::c_uint,
4864 size: ::core::ffi::c_uint,
4865 value: *mut ::core::ffi::c_void,
4866 ) -> ::core::ffi::c_int;
4867}
4868unsafe extern "C" {
4869 #[doc = " Query information about VM faults\n\n The return sizeof(struct drm_amdgpu_info_gpuvm_fault)\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n \\param size - \\c [in] Size of the returned value.\n \\param value - \\c [out] Pointer to the return value.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4870 pub fn amdgpu_query_gpuvm_fault_info(
4871 dev: amdgpu_device_handle,
4872 size: ::core::ffi::c_uint,
4873 value: *mut ::core::ffi::c_void,
4874 ) -> ::core::ffi::c_int;
4875}
4876unsafe extern "C" {
4877 #[doc = " Read a set of consecutive memory-mapped registers.\n Not all registers are allowed to be read by userspace.\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize(\n \\param dword_offset - \\c [in] Register offset in dwords\n \\param count - \\c [in] The number of registers to read starting\n from the offset\n \\param instance - \\c [in] GRBM_GFX_INDEX selector. It may have other\n uses. Set it to 0xffffffff if unsure.\n \\param flags - \\c [in] Flags with additional information.\n \\param values - \\c [out] The pointer to return values.\n\n \\return 0 on success\\n\n <0 - Negative POSIX error code"]
4878 pub fn amdgpu_read_mm_registers(
4879 dev: amdgpu_device_handle,
4880 dword_offset: ::core::ffi::c_uint,
4881 count: ::core::ffi::c_uint,
4882 instance: u32,
4883 flags: u32,
4884 values: *mut u32,
4885 ) -> ::core::ffi::c_int;
4886}
4887unsafe extern "C" {
4888 #[doc = " Allocate virtual address range\n\n \\param dev - [in] Device handle. See #amdgpu_device_initialize()\n \\param va_range_type - \\c [in] Type of MC va range from which to allocate\n \\param size - \\c [in] Size of range. Size must be correctly* aligned.\n It is client responsibility to correctly aligned size based on the future\n usage of allocated range.\n \\param va_base_alignment - \\c [in] Overwrite base address alignment\n requirement for GPU VM MC virtual\n address assignment. Must be multiple of size alignments received as\n 'amdgpu_buffer_size_alignments'.\n If 0 use the default one.\n \\param va_base_required - \\c [in] Specified required va base address.\n If 0 then library choose available one.\n If !0 value will be passed and those value already \"in use\" then\n corresponding error status will be returned.\n \\param va_base_allocated - \\c [out] On return: Allocated VA base to be used\n by client.\n \\param va_range_handle - \\c [out] On return: Handle assigned to allocation\n \\param flags - \\c [in] flags for special VA range\n\n \\return 0 on success\\n\n >0 - AMD specific error code\\n\n <0 - Negative POSIX Error code\n\n \\notes \\n\n It is client responsibility to correctly handle VA assignments and usage.\n Neither kernel driver nor libdrm_amdpgu are able to prevent and\n detect wrong va assignment.\n\n It is client responsibility to correctly handle multi-GPU cases and to pass\n the corresponding arrays of all devices handles where corresponding VA will\n be used."]
4889 pub fn amdgpu_va_range_alloc(
4890 dev: amdgpu_device_handle,
4891 va_range_type: amdgpu_gpu_va_range,
4892 size: u64,
4893 va_base_alignment: u64,
4894 va_base_required: u64,
4895 va_base_allocated: *mut u64,
4896 va_range_handle: *mut amdgpu_va_handle,
4897 flags: u64,
4898 ) -> ::core::ffi::c_int;
4899}
4900unsafe extern "C" {
4901 #[doc = " Free previously allocated virtual address range\n\n\n \\param va_range_handle - \\c [in] Handle assigned to VA allocation\n\n \\return 0 on success\\n\n >0 - AMD specific error code\\n\n <0 - Negative POSIX Error code"]
4902 pub fn amdgpu_va_range_free(va_range_handle: amdgpu_va_handle) -> ::core::ffi::c_int;
4903}
4904unsafe extern "C" {
4905 #[doc = " Return the starting address of the allocated virtual address range."]
4906 pub fn amdgpu_va_get_start_addr(va_handle: amdgpu_va_handle) -> u64;
4907}
4908unsafe extern "C" {
4909 #[doc = " Query virtual address range\n\n UMD can query GPU VM range supported by each device\n to initialize its own VAM accordingly.\n\n \\param dev - [in] Device handle. See #amdgpu_device_initialize()\n \\param type - \\c [in] Type of virtual address range\n \\param offset - \\c [out] Start offset of virtual address range\n \\param size - \\c [out] Size of virtual address range\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4910 pub fn amdgpu_va_range_query(
4911 dev: amdgpu_device_handle,
4912 type_: amdgpu_gpu_va_range,
4913 start: *mut u64,
4914 end: *mut u64,
4915 ) -> ::core::ffi::c_int;
4916}
4917unsafe extern "C" {
4918 #[doc = " Allocate a amdgpu_va_manager object.\n The returned object has be initialized with the amdgpu_va_manager_init\n before use.\n On release, amdgpu_va_manager_deinit needs to be called, then the memory\n can be released using free()."]
4919 pub fn amdgpu_va_manager_alloc() -> amdgpu_va_manager_handle;
4920}
4921unsafe extern "C" {
4922 pub fn amdgpu_va_manager_init(
4923 va_mgr: amdgpu_va_manager_handle,
4924 low_va_offset: u64,
4925 low_va_max: u64,
4926 high_va_offset: u64,
4927 high_va_max: u64,
4928 virtual_address_alignment: u32,
4929 );
4930}
4931unsafe extern "C" {
4932 pub fn amdgpu_va_manager_deinit(va_mgr: amdgpu_va_manager_handle);
4933}
4934unsafe extern "C" {
4935 #[doc = " Similar to #amdgpu_va_range_alloc() but allocates VA\n directly from an amdgpu_va_manager_handle instead of using\n the manager from an amdgpu_device."]
4936 pub fn amdgpu_va_range_alloc2(
4937 va_mgr: amdgpu_va_manager_handle,
4938 va_range_type: amdgpu_gpu_va_range,
4939 size: u64,
4940 va_base_alignment: u64,
4941 va_base_required: u64,
4942 va_base_allocated: *mut u64,
4943 va_range_handle: *mut amdgpu_va_handle,
4944 flags: u64,
4945 ) -> ::core::ffi::c_int;
4946}
4947unsafe extern "C" {
4948 #[doc = " VA mapping/unmapping for the buffer object\n\n \\param bo\t\t- \\c [in] BO handle\n \\param offset\t- \\c [in] Start offset to map\n \\param size\t\t- \\c [in] Size to map\n \\param addr\t\t- \\c [in] Start virtual address.\n \\param flags\t- \\c [in] Supported flags for mapping/unmapping\n \\param ops\t\t- \\c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4949 pub fn amdgpu_bo_va_op(
4950 bo: amdgpu_bo_handle,
4951 offset: u64,
4952 size: u64,
4953 addr: u64,
4954 flags: u64,
4955 ops: u32,
4956 ) -> ::core::ffi::c_int;
4957}
4958unsafe extern "C" {
4959 #[doc = " VA mapping/unmapping for a buffer object or PRT region.\n\n This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all\n parameters are treated \"raw\", i.e. size is not automatically aligned, and\n all flags must be specified explicitly.\n\n \\param dev\t\t- \\c [in] device handle\n \\param bo\t\t- \\c [in] BO handle (may be NULL)\n \\param offset\t- \\c [in] Start offset to map\n \\param size\t\t- \\c [in] Size to map\n \\param addr\t\t- \\c [in] Start virtual address.\n \\param flags\t- \\c [in] Supported flags for mapping/unmapping\n \\param ops\t\t- \\c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4960 pub fn amdgpu_bo_va_op_raw(
4961 dev: amdgpu_device_handle,
4962 bo: amdgpu_bo_handle,
4963 offset: u64,
4964 size: u64,
4965 addr: u64,
4966 flags: u64,
4967 ops: u32,
4968 ) -> ::core::ffi::c_int;
4969}
4970unsafe extern "C" {
4971 #[doc = " create semaphore\n\n \\param sem\t - \\c [out] semaphore handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4972 pub fn amdgpu_cs_create_semaphore(sem: *mut amdgpu_semaphore_handle) -> ::core::ffi::c_int;
4973}
4974unsafe extern "C" {
4975 #[doc = " signal semaphore\n\n \\param context - \\c [in] GPU Context\n \\param ip_type - \\c [in] Hardware IP block type = AMDGPU_HW_IP_*\n \\param ip_instance - \\c [in] Index of the IP block of the same type\n \\param ring - \\c [in] Specify ring index of the IP\n \\param sem\t - \\c [in] semaphore handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4976 pub fn amdgpu_cs_signal_semaphore(
4977 ctx: amdgpu_context_handle,
4978 ip_type: u32,
4979 ip_instance: u32,
4980 ring: u32,
4981 sem: amdgpu_semaphore_handle,
4982 ) -> ::core::ffi::c_int;
4983}
4984unsafe extern "C" {
4985 #[doc = " wait semaphore\n\n \\param context - \\c [in] GPU Context\n \\param ip_type - \\c [in] Hardware IP block type = AMDGPU_HW_IP_*\n \\param ip_instance - \\c [in] Index of the IP block of the same type\n \\param ring - \\c [in] Specify ring index of the IP\n \\param sem\t - \\c [in] semaphore handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4986 pub fn amdgpu_cs_wait_semaphore(
4987 ctx: amdgpu_context_handle,
4988 ip_type: u32,
4989 ip_instance: u32,
4990 ring: u32,
4991 sem: amdgpu_semaphore_handle,
4992 ) -> ::core::ffi::c_int;
4993}
4994unsafe extern "C" {
4995 #[doc = " destroy semaphore\n\n \\param sem\t - \\c [in] semaphore handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
4996 pub fn amdgpu_cs_destroy_semaphore(sem: amdgpu_semaphore_handle) -> ::core::ffi::c_int;
4997}
4998unsafe extern "C" {
4999 #[doc = " Get the ASIC marketing name\n\n \\param dev - \\c [in] Device handle. See #amdgpu_device_initialize()\n\n \\return the constant string of the marketing name\n \"NULL\" means the ASIC is not found"]
5000 pub fn amdgpu_get_marketing_name(dev: amdgpu_device_handle) -> *const ::core::ffi::c_char;
5001}
5002unsafe extern "C" {
5003 #[doc = " Create kernel sync object\n\n \\param dev - \\c [in] device handle\n \\param flags - \\c [in] flags that affect creation\n \\param syncobj - \\c [out] sync object handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5004 pub fn amdgpu_cs_create_syncobj2(
5005 dev: amdgpu_device_handle,
5006 flags: u32,
5007 syncobj: *mut u32,
5008 ) -> ::core::ffi::c_int;
5009}
5010unsafe extern "C" {
5011 #[doc = " Create kernel sync object\n\n \\param dev\t - \\c [in] device handle\n \\param syncobj - \\c [out] sync object handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5012 pub fn amdgpu_cs_create_syncobj(
5013 dev: amdgpu_device_handle,
5014 syncobj: *mut u32,
5015 ) -> ::core::ffi::c_int;
5016}
5017unsafe extern "C" {
5018 #[doc = " Destroy kernel sync object\n\n \\param dev\t - \\c [in] device handle\n \\param syncobj - \\c [in] sync object handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5019 pub fn amdgpu_cs_destroy_syncobj(dev: amdgpu_device_handle, syncobj: u32)
5020 -> ::core::ffi::c_int;
5021}
5022unsafe extern "C" {
5023 #[doc = " Reset kernel sync objects to unsignalled state.\n\n \\param dev - \\c [in] device handle\n \\param syncobjs - \\c [in] array of sync object handles\n \\param syncobj_count - \\c [in] number of handles in syncobjs\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5024 pub fn amdgpu_cs_syncobj_reset(
5025 dev: amdgpu_device_handle,
5026 syncobjs: *const u32,
5027 syncobj_count: u32,
5028 ) -> ::core::ffi::c_int;
5029}
5030unsafe extern "C" {
5031 #[doc = " Signal kernel sync objects.\n\n \\param dev - \\c [in] device handle\n \\param syncobjs - \\c [in] array of sync object handles\n \\param syncobj_count - \\c [in] number of handles in syncobjs\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5032 pub fn amdgpu_cs_syncobj_signal(
5033 dev: amdgpu_device_handle,
5034 syncobjs: *const u32,
5035 syncobj_count: u32,
5036 ) -> ::core::ffi::c_int;
5037}
5038unsafe extern "C" {
5039 #[doc = " Signal kernel timeline sync objects.\n\n \\param dev - \\c [in] device handle\n \\param syncobjs - \\c [in] array of sync object handles\n \\param points\t- \\c [in] array of timeline points\n \\param syncobj_count - \\c [in] number of handles in syncobjs\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5040 pub fn amdgpu_cs_syncobj_timeline_signal(
5041 dev: amdgpu_device_handle,
5042 syncobjs: *const u32,
5043 points: *mut u64,
5044 syncobj_count: u32,
5045 ) -> ::core::ffi::c_int;
5046}
5047unsafe extern "C" {
5048 #[doc = " Wait for one or all sync objects to signal.\n\n \\param dev\t - \\c [in] self-explanatory\n \\param handles - \\c [in] array of sync object handles\n \\param num_handles - \\c [in] self-explanatory\n \\param timeout_nsec - \\c [in] self-explanatory\n \\param flags - \\c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*\n \\param first_signaled - \\c [in] self-explanatory\n\n \\return 0 on success\\n\n -ETIME - Timeout\n <0 - Negative POSIX Error code\n"]
5049 pub fn amdgpu_cs_syncobj_wait(
5050 dev: amdgpu_device_handle,
5051 handles: *mut u32,
5052 num_handles: ::core::ffi::c_uint,
5053 timeout_nsec: i64,
5054 flags: ::core::ffi::c_uint,
5055 first_signaled: *mut u32,
5056 ) -> ::core::ffi::c_int;
5057}
5058unsafe extern "C" {
5059 #[doc = " Wait for one or all sync objects on their points to signal.\n\n \\param dev\t - \\c [in] self-explanatory\n \\param handles - \\c [in] array of sync object handles\n \\param points - \\c [in] array of sync points to wait\n \\param num_handles - \\c [in] self-explanatory\n \\param timeout_nsec - \\c [in] self-explanatory\n \\param flags - \\c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*\n \\param first_signaled - \\c [in] self-explanatory\n\n \\return 0 on success\\n\n -ETIME - Timeout\n <0 - Negative POSIX Error code\n"]
5060 pub fn amdgpu_cs_syncobj_timeline_wait(
5061 dev: amdgpu_device_handle,
5062 handles: *mut u32,
5063 points: *mut u64,
5064 num_handles: ::core::ffi::c_uint,
5065 timeout_nsec: i64,
5066 flags: ::core::ffi::c_uint,
5067 first_signaled: *mut u32,
5068 ) -> ::core::ffi::c_int;
5069}
5070unsafe extern "C" {
5071 #[doc = " Query sync objects payloads.\n\n \\param dev\t - \\c [in] self-explanatory\n \\param handles - \\c [in] array of sync object handles\n \\param points - \\c [out] array of sync points returned, which presents\n syncobj payload.\n \\param num_handles - \\c [in] self-explanatory\n\n \\return 0 on success\\n\n -ETIME - Timeout\n <0 - Negative POSIX Error code\n"]
5072 pub fn amdgpu_cs_syncobj_query(
5073 dev: amdgpu_device_handle,
5074 handles: *mut u32,
5075 points: *mut u64,
5076 num_handles: ::core::ffi::c_uint,
5077 ) -> ::core::ffi::c_int;
5078}
5079unsafe extern "C" {
5080 #[doc = " Query sync objects last signaled or submitted point.\n\n \\param dev\t - \\c [in] self-explanatory\n \\param handles - \\c [in] array of sync object handles\n \\param points - \\c [out] array of sync points returned, which presents\n syncobj payload.\n \\param num_handles - \\c [in] self-explanatory\n \\param flags - \\c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_*\n\n \\return 0 on success\\n\n -ETIME - Timeout\n <0 - Negative POSIX Error code\n"]
5081 pub fn amdgpu_cs_syncobj_query2(
5082 dev: amdgpu_device_handle,
5083 handles: *mut u32,
5084 points: *mut u64,
5085 num_handles: ::core::ffi::c_uint,
5086 flags: u32,
5087 ) -> ::core::ffi::c_int;
5088}
5089unsafe extern "C" {
5090 #[doc = " Export kernel sync object to shareable fd.\n\n \\param dev\t - \\c [in] device handle\n \\param syncobj - \\c [in] sync object handle\n \\param shared_fd - \\c [out] shared file descriptor.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5091 pub fn amdgpu_cs_export_syncobj(
5092 dev: amdgpu_device_handle,
5093 syncobj: u32,
5094 shared_fd: *mut ::core::ffi::c_int,
5095 ) -> ::core::ffi::c_int;
5096}
5097unsafe extern "C" {
5098 #[doc = " Import kernel sync object from shareable fd.\n\n \\param dev\t - \\c [in] device handle\n \\param shared_fd - \\c [in] shared file descriptor.\n \\param syncobj - \\c [out] sync object handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5099 pub fn amdgpu_cs_import_syncobj(
5100 dev: amdgpu_device_handle,
5101 shared_fd: ::core::ffi::c_int,
5102 syncobj: *mut u32,
5103 ) -> ::core::ffi::c_int;
5104}
5105unsafe extern "C" {
5106 #[doc = " Export kernel sync object to a sync_file.\n\n \\param dev\t - \\c [in] device handle\n \\param syncobj - \\c [in] sync object handle\n \\param sync_file_fd - \\c [out] sync_file file descriptor.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5107 pub fn amdgpu_cs_syncobj_export_sync_file(
5108 dev: amdgpu_device_handle,
5109 syncobj: u32,
5110 sync_file_fd: *mut ::core::ffi::c_int,
5111 ) -> ::core::ffi::c_int;
5112}
5113unsafe extern "C" {
5114 #[doc = " Import kernel sync object from a sync_file.\n\n \\param dev\t - \\c [in] device handle\n \\param syncobj - \\c [in] sync object handle\n \\param sync_file_fd - \\c [in] sync_file file descriptor.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5115 pub fn amdgpu_cs_syncobj_import_sync_file(
5116 dev: amdgpu_device_handle,
5117 syncobj: u32,
5118 sync_file_fd: ::core::ffi::c_int,
5119 ) -> ::core::ffi::c_int;
5120}
5121unsafe extern "C" {
5122 #[doc = " Export kernel timeline sync object to a sync_file.\n\n \\param dev\t\t- \\c [in] device handle\n \\param syncobj\t- \\c [in] sync object handle\n \\param point\t- \\c [in] timeline point\n \\param flags\t- \\c [in] flags\n \\param sync_file_fd - \\c [out] sync_file file descriptor.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5123 pub fn amdgpu_cs_syncobj_export_sync_file2(
5124 dev: amdgpu_device_handle,
5125 syncobj: u32,
5126 point: u64,
5127 flags: u32,
5128 sync_file_fd: *mut ::core::ffi::c_int,
5129 ) -> ::core::ffi::c_int;
5130}
5131unsafe extern "C" {
5132 #[doc = " Import kernel timeline sync object from a sync_file.\n\n \\param dev\t\t- \\c [in] device handle\n \\param syncobj\t- \\c [in] sync object handle\n \\param point\t- \\c [in] timeline point\n \\param sync_file_fd - \\c [in] sync_file file descriptor.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5133 pub fn amdgpu_cs_syncobj_import_sync_file2(
5134 dev: amdgpu_device_handle,
5135 syncobj: u32,
5136 point: u64,
5137 sync_file_fd: ::core::ffi::c_int,
5138 ) -> ::core::ffi::c_int;
5139}
5140unsafe extern "C" {
5141 #[doc = " transfer between syncbojs.\n\n \\param dev\t\t- \\c [in] device handle\n \\param dst_handle\t- \\c [in] sync object handle\n \\param dst_point\t- \\c [in] timeline point, 0 presents dst is binary\n \\param src_handle\t- \\c [in] sync object handle\n \\param src_point\t- \\c [in] timeline point, 0 presents src is binary\n \\param flags\t- \\c [in] flags\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5142 pub fn amdgpu_cs_syncobj_transfer(
5143 dev: amdgpu_device_handle,
5144 dst_handle: u32,
5145 dst_point: u64,
5146 src_handle: u32,
5147 src_point: u64,
5148 flags: u32,
5149 ) -> ::core::ffi::c_int;
5150}
5151unsafe extern "C" {
5152 #[doc = " Export an amdgpu fence as a handle (syncobj or fd).\n\n \\param what\t\tAMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}\n \\param out_handle\treturned handle\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code"]
5153 pub fn amdgpu_cs_fence_to_handle(
5154 dev: amdgpu_device_handle,
5155 fence: *mut amdgpu_cs_fence,
5156 what: u32,
5157 out_handle: *mut u32,
5158 ) -> ::core::ffi::c_int;
5159}
5160unsafe extern "C" {
5161 pub fn amdgpu_cs_submit_raw(
5162 dev: amdgpu_device_handle,
5163 context: amdgpu_context_handle,
5164 bo_list_handle: amdgpu_bo_list_handle,
5165 num_chunks: ::core::ffi::c_int,
5166 chunks: *mut drm_amdgpu_cs_chunk,
5167 seq_no: *mut u64,
5168 ) -> ::core::ffi::c_int;
5169}
5170unsafe extern "C" {
5171 #[doc = " Submit raw command submission to the kernel with a raw BO list handle.\n\n \\param dev\t - \\c [in] device handle\n \\param context - \\c [in] context handle for context id\n \\param bo_list_handle - \\c [in] raw bo list handle (0 for none)\n \\param num_chunks - \\c [in] number of CS chunks to submit\n \\param chunks - \\c [in] array of CS chunks\n \\param seq_no - \\c [out] output sequence number for submission.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n\n \\sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()"]
5172 pub fn amdgpu_cs_submit_raw2(
5173 dev: amdgpu_device_handle,
5174 context: amdgpu_context_handle,
5175 bo_list_handle: u32,
5176 num_chunks: ::core::ffi::c_int,
5177 chunks: *mut drm_amdgpu_cs_chunk,
5178 seq_no: *mut u64,
5179 ) -> ::core::ffi::c_int;
5180}
5181unsafe extern "C" {
5182 pub fn amdgpu_cs_chunk_fence_to_dep(
5183 fence: *mut amdgpu_cs_fence,
5184 dep: *mut drm_amdgpu_cs_chunk_dep,
5185 );
5186}
5187unsafe extern "C" {
5188 pub fn amdgpu_cs_chunk_fence_info_to_data(
5189 fence_info: *mut amdgpu_cs_fence_info,
5190 data: *mut drm_amdgpu_cs_chunk_data,
5191 );
5192}
5193unsafe extern "C" {
5194 #[doc = " Reserve VMID\n \\param context - \\c [in] GPU Context\n \\param flags - \\c [in] TBD\n\n \\return 0 on success otherwise POSIX Error code"]
5195 pub fn amdgpu_vm_reserve_vmid(dev: amdgpu_device_handle, flags: u32) -> ::core::ffi::c_int;
5196}
5197unsafe extern "C" {
5198 #[doc = " Free reserved VMID\n \\param context - \\c [in] GPU Context\n \\param flags - \\c [in] TBD\n\n \\return 0 on success otherwise POSIX Error code"]
5199 pub fn amdgpu_vm_unreserve_vmid(dev: amdgpu_device_handle, flags: u32) -> ::core::ffi::c_int;
5200}
5201#[repr(C)]
5202#[derive(Debug, Copy, Clone)]
5203pub struct drm_amdgpu_gem_create_in {
5204 #[doc = " the requested memory size"]
5205 pub bo_size: __u64,
5206 #[doc = " physical start_addr alignment in bytes for some HW requirements"]
5207 pub alignment: __u64,
5208 #[doc = " the requested memory domains"]
5209 pub domains: __u64,
5210 #[doc = " allocation flags"]
5211 pub domain_flags: __u64,
5212}
5213#[repr(C)]
5214#[derive(Debug, Copy, Clone)]
5215pub struct drm_amdgpu_gem_create_out {
5216 #[doc = " returned GEM object handle"]
5217 pub handle: __u32,
5218 pub _pad: __u32,
5219}
5220#[repr(C)]
5221#[derive(Copy, Clone)]
5222pub union drm_amdgpu_gem_create {
5223 pub in_: drm_amdgpu_gem_create_in,
5224 pub out: drm_amdgpu_gem_create_out,
5225}
5226#[repr(C)]
5227#[derive(Debug, Copy, Clone)]
5228pub struct drm_amdgpu_bo_list_in {
5229 #[doc = " Type of operation"]
5230 pub operation: __u32,
5231 #[doc = " Handle of list or 0 if we want to create one"]
5232 pub list_handle: __u32,
5233 #[doc = " Number of BOs in list"]
5234 pub bo_number: __u32,
5235 #[doc = " Size of each element describing BO"]
5236 pub bo_info_size: __u32,
5237 #[doc = " Pointer to array describing BOs"]
5238 pub bo_info_ptr: __u64,
5239}
5240#[repr(C)]
5241#[derive(Debug, Copy, Clone)]
5242pub struct drm_amdgpu_bo_list_entry {
5243 #[doc = " Handle of BO"]
5244 pub bo_handle: __u32,
5245 #[doc = " New (if specified) BO priority to be used during migration"]
5246 pub bo_priority: __u32,
5247}
5248#[repr(C)]
5249#[derive(Debug, Copy, Clone)]
5250pub struct drm_amdgpu_bo_list_out {
5251 #[doc = " Handle of resource list"]
5252 pub list_handle: __u32,
5253 pub _pad: __u32,
5254}
5255#[repr(C)]
5256#[derive(Copy, Clone)]
5257pub union drm_amdgpu_bo_list {
5258 pub in_: drm_amdgpu_bo_list_in,
5259 pub out: drm_amdgpu_bo_list_out,
5260}
5261#[repr(C)]
5262#[derive(Debug, Copy, Clone)]
5263pub struct drm_amdgpu_ctx_in {
5264 #[doc = " AMDGPU_CTX_OP_*"]
5265 pub op: __u32,
5266 #[doc = " Flags"]
5267 pub flags: __u32,
5268 pub ctx_id: __u32,
5269 #[doc = " AMDGPU_CTX_PRIORITY_*"]
5270 pub priority: __s32,
5271}
5272#[repr(C)]
5273#[derive(Copy, Clone)]
5274pub union drm_amdgpu_ctx_out {
5275 pub alloc: drm_amdgpu_ctx_out__bindgen_ty_1,
5276 pub state: drm_amdgpu_ctx_out__bindgen_ty_2,
5277 pub pstate: drm_amdgpu_ctx_out__bindgen_ty_3,
5278}
5279#[repr(C)]
5280#[derive(Debug, Copy, Clone)]
5281pub struct drm_amdgpu_ctx_out__bindgen_ty_1 {
5282 pub ctx_id: __u32,
5283 pub _pad: __u32,
5284}
5285#[repr(C)]
5286#[derive(Debug, Copy, Clone)]
5287pub struct drm_amdgpu_ctx_out__bindgen_ty_2 {
5288 #[doc = " For future use, no flags defined so far"]
5289 pub flags: __u64,
5290 #[doc = " Number of resets caused by this context so far."]
5291 pub hangs: __u32,
5292 #[doc = " Reset status since the last call of the ioctl."]
5293 pub reset_status: __u32,
5294}
5295#[repr(C)]
5296#[derive(Debug, Copy, Clone)]
5297pub struct drm_amdgpu_ctx_out__bindgen_ty_3 {
5298 pub flags: __u32,
5299 pub _pad: __u32,
5300}
5301#[repr(C)]
5302#[derive(Copy, Clone)]
5303pub union drm_amdgpu_ctx {
5304 pub in_: drm_amdgpu_ctx_in,
5305 pub out: drm_amdgpu_ctx_out,
5306}
5307#[repr(C)]
5308#[derive(Debug, Copy, Clone)]
5309pub struct drm_amdgpu_vm_in {
5310 #[doc = " AMDGPU_VM_OP_*"]
5311 pub op: __u32,
5312 pub flags: __u32,
5313}
5314#[repr(C)]
5315#[derive(Debug, Copy, Clone)]
5316pub struct drm_amdgpu_vm_out {
5317 #[doc = " For future use, no flags defined so far"]
5318 pub flags: __u64,
5319}
5320#[repr(C)]
5321#[derive(Copy, Clone)]
5322pub union drm_amdgpu_vm {
5323 pub in_: drm_amdgpu_vm_in,
5324 pub out: drm_amdgpu_vm_out,
5325}
5326#[repr(C)]
5327#[derive(Debug, Copy, Clone)]
5328pub struct drm_amdgpu_sched_in {
5329 pub op: __u32,
5330 pub fd: __u32,
5331 #[doc = " AMDGPU_CTX_PRIORITY_*"]
5332 pub priority: __s32,
5333 pub ctx_id: __u32,
5334}
5335#[repr(C)]
5336#[derive(Copy, Clone)]
5337pub union drm_amdgpu_sched {
5338 pub in_: drm_amdgpu_sched_in,
5339}
5340#[repr(C)]
5341#[derive(Debug, Copy, Clone)]
5342pub struct drm_amdgpu_gem_userptr {
5343 pub addr: __u64,
5344 pub size: __u64,
5345 pub flags: __u32,
5346 pub handle: __u32,
5347}
5348#[doc = " The same structure is shared for input/output"]
5349#[repr(C)]
5350#[derive(Debug, Copy, Clone)]
5351pub struct drm_amdgpu_gem_metadata {
5352 #[doc = " GEM Object handle"]
5353 pub handle: __u32,
5354 #[doc = " Do we want get or set metadata"]
5355 pub op: __u32,
5356 pub data: drm_amdgpu_gem_metadata__bindgen_ty_1,
5357}
5358#[repr(C)]
5359#[derive(Debug, Copy, Clone)]
5360pub struct drm_amdgpu_gem_metadata__bindgen_ty_1 {
5361 #[doc = " For future use, no flags defined so far"]
5362 pub flags: __u64,
5363 #[doc = " family specific tiling info"]
5364 pub tiling_info: __u64,
5365 pub data_size_bytes: __u32,
5366 pub data: [__u32; 64usize],
5367}
5368#[repr(C)]
5369#[derive(Debug, Copy, Clone)]
5370pub struct drm_amdgpu_gem_mmap_in {
5371 #[doc = " the GEM object handle"]
5372 pub handle: __u32,
5373 pub _pad: __u32,
5374}
5375#[repr(C)]
5376#[derive(Debug, Copy, Clone)]
5377pub struct drm_amdgpu_gem_mmap_out {
5378 #[doc = " mmap offset from the vma offset manager"]
5379 pub addr_ptr: __u64,
5380}
5381#[repr(C)]
5382#[derive(Copy, Clone)]
5383pub union drm_amdgpu_gem_mmap {
5384 pub in_: drm_amdgpu_gem_mmap_in,
5385 pub out: drm_amdgpu_gem_mmap_out,
5386}
5387#[repr(C)]
5388#[derive(Debug, Copy, Clone)]
5389pub struct drm_amdgpu_gem_wait_idle_in {
5390 #[doc = " GEM object handle"]
5391 pub handle: __u32,
5392 #[doc = " For future use, no flags defined so far"]
5393 pub flags: __u32,
5394 #[doc = " Absolute timeout to wait"]
5395 pub timeout: __u64,
5396}
5397#[repr(C)]
5398#[derive(Debug, Copy, Clone)]
5399pub struct drm_amdgpu_gem_wait_idle_out {
5400 #[doc = " BO status: 0 - BO is idle, 1 - BO is busy"]
5401 pub status: __u32,
5402 #[doc = " Returned current memory domain"]
5403 pub domain: __u32,
5404}
5405#[repr(C)]
5406#[derive(Copy, Clone)]
5407pub union drm_amdgpu_gem_wait_idle {
5408 pub in_: drm_amdgpu_gem_wait_idle_in,
5409 pub out: drm_amdgpu_gem_wait_idle_out,
5410}
5411#[repr(C)]
5412#[derive(Debug, Copy, Clone)]
5413pub struct drm_amdgpu_wait_cs_in {
5414 pub handle: __u64,
5415 #[doc = " Absolute timeout to wait"]
5416 pub timeout: __u64,
5417 pub ip_type: __u32,
5418 pub ip_instance: __u32,
5419 pub ring: __u32,
5420 pub ctx_id: __u32,
5421}
5422#[repr(C)]
5423#[derive(Debug, Copy, Clone)]
5424pub struct drm_amdgpu_wait_cs_out {
5425 #[doc = " CS status: 0 - CS completed, 1 - CS still busy"]
5426 pub status: __u64,
5427}
5428#[repr(C)]
5429#[derive(Copy, Clone)]
5430pub union drm_amdgpu_wait_cs {
5431 pub in_: drm_amdgpu_wait_cs_in,
5432 pub out: drm_amdgpu_wait_cs_out,
5433}
5434#[repr(C)]
5435#[derive(Debug, Copy, Clone)]
5436pub struct drm_amdgpu_fence {
5437 pub ctx_id: __u32,
5438 pub ip_type: __u32,
5439 pub ip_instance: __u32,
5440 pub ring: __u32,
5441 pub seq_no: __u64,
5442}
5443#[repr(C)]
5444#[derive(Debug, Copy, Clone)]
5445pub struct drm_amdgpu_wait_fences_in {
5446 #[doc = " This points to uint64_t * which points to fences"]
5447 pub fences: __u64,
5448 pub fence_count: __u32,
5449 pub wait_all: __u32,
5450 pub timeout_ns: __u64,
5451}
5452#[repr(C)]
5453#[derive(Debug, Copy, Clone)]
5454pub struct drm_amdgpu_wait_fences_out {
5455 pub status: __u32,
5456 pub first_signaled: __u32,
5457}
5458#[repr(C)]
5459#[derive(Copy, Clone)]
5460pub union drm_amdgpu_wait_fences {
5461 pub in_: drm_amdgpu_wait_fences_in,
5462 pub out: drm_amdgpu_wait_fences_out,
5463}
5464#[repr(C)]
5465#[derive(Debug, Copy, Clone)]
5466pub struct drm_amdgpu_gem_op {
5467 #[doc = " GEM object handle"]
5468 pub handle: __u32,
5469 #[doc = " AMDGPU_GEM_OP_*"]
5470 pub op: __u32,
5471 #[doc = " Input or return value"]
5472 pub value: __u64,
5473}
5474#[repr(C)]
5475#[derive(Debug, Copy, Clone)]
5476pub struct drm_amdgpu_gem_va {
5477 #[doc = " GEM object handle"]
5478 pub handle: __u32,
5479 pub _pad: __u32,
5480 #[doc = " AMDGPU_VA_OP_*"]
5481 pub operation: __u32,
5482 #[doc = " AMDGPU_VM_PAGE_*"]
5483 pub flags: __u32,
5484 #[doc = " va address to assign . Must be correctly aligned."]
5485 pub va_address: __u64,
5486 #[doc = " Specify offset inside of BO to assign. Must be correctly aligned."]
5487 pub offset_in_bo: __u64,
5488 #[doc = " Specify mapping size. Must be correctly aligned."]
5489 pub map_size: __u64,
5490}
5491#[doc = " Submit raw command submission to kernel\n\n \\param dev\t - \\c [in] device handle\n \\param context - \\c [in] context handle for context id\n \\param bo_list_handle - \\c [in] request bo list handle (0 for none)\n \\param num_chunks - \\c [in] number of CS chunks to submit\n \\param chunks - \\c [in] array of CS chunks\n \\param seq_no - \\c [out] output sequence number for submission.\n\n \\return 0 on success\\n\n <0 - Negative POSIX Error code\n"]
5492#[repr(C)]
5493#[derive(Debug, Copy, Clone)]
5494pub struct drm_amdgpu_cs_chunk {
5495 pub chunk_id: __u32,
5496 pub length_dw: __u32,
5497 pub chunk_data: __u64,
5498}
5499#[repr(C)]
5500#[derive(Debug, Copy, Clone)]
5501pub struct drm_amdgpu_cs_in {
5502 #[doc = " Rendering context id"]
5503 pub ctx_id: __u32,
5504 #[doc = " Handle of resource list associated with CS"]
5505 pub bo_list_handle: __u32,
5506 pub num_chunks: __u32,
5507 pub flags: __u32,
5508 #[doc = " this points to __u64 * which point to cs chunks"]
5509 pub chunks: __u64,
5510}
5511#[repr(C)]
5512#[derive(Debug, Copy, Clone)]
5513pub struct drm_amdgpu_cs_out {
5514 pub handle: __u64,
5515}
5516#[repr(C)]
5517#[derive(Copy, Clone)]
5518pub union drm_amdgpu_cs {
5519 pub in_: drm_amdgpu_cs_in,
5520 pub out: drm_amdgpu_cs_out,
5521}
5522#[repr(C)]
5523#[derive(Debug, Copy, Clone)]
5524pub struct drm_amdgpu_cs_chunk_ib {
5525 pub _pad: __u32,
5526 #[doc = " AMDGPU_IB_FLAG_*"]
5527 pub flags: __u32,
5528 #[doc = " Virtual address to begin IB execution"]
5529 pub va_start: __u64,
5530 #[doc = " Size of submission"]
5531 pub ib_bytes: __u32,
5532 #[doc = " HW IP to submit to"]
5533 pub ip_type: __u32,
5534 #[doc = " HW IP index of the same type to submit to"]
5535 pub ip_instance: __u32,
5536 #[doc = " Ring index to submit to"]
5537 pub ring: __u32,
5538}
5539#[repr(C)]
5540#[derive(Debug, Copy, Clone)]
5541pub struct drm_amdgpu_cs_chunk_dep {
5542 pub ip_type: __u32,
5543 pub ip_instance: __u32,
5544 pub ring: __u32,
5545 pub ctx_id: __u32,
5546 pub handle: __u64,
5547}
5548#[repr(C)]
5549#[derive(Debug, Copy, Clone)]
5550pub struct drm_amdgpu_cs_chunk_fence {
5551 pub handle: __u32,
5552 pub offset: __u32,
5553}
5554#[repr(C)]
5555#[derive(Debug, Copy, Clone)]
5556pub struct drm_amdgpu_cs_chunk_sem {
5557 pub handle: __u32,
5558}
5559#[repr(C)]
5560#[derive(Debug, Copy, Clone)]
5561pub struct drm_amdgpu_cs_chunk_syncobj {
5562 pub handle: __u32,
5563 pub flags: __u32,
5564 pub point: __u64,
5565}
5566#[repr(C)]
5567#[derive(Copy, Clone)]
5568pub union drm_amdgpu_fence_to_handle {
5569 pub in_: drm_amdgpu_fence_to_handle__bindgen_ty_1,
5570 pub out: drm_amdgpu_fence_to_handle__bindgen_ty_2,
5571}
5572#[repr(C)]
5573#[derive(Debug, Copy, Clone)]
5574pub struct drm_amdgpu_fence_to_handle__bindgen_ty_1 {
5575 pub fence: drm_amdgpu_fence,
5576 pub what: __u32,
5577 pub pad: __u32,
5578}
5579#[repr(C)]
5580#[derive(Debug, Copy, Clone)]
5581pub struct drm_amdgpu_fence_to_handle__bindgen_ty_2 {
5582 pub handle: __u32,
5583}
5584#[repr(C)]
5585#[derive(Copy, Clone)]
5586pub struct drm_amdgpu_cs_chunk_data {
5587 pub __bindgen_anon_1: drm_amdgpu_cs_chunk_data__bindgen_ty_1,
5588}
5589#[repr(C)]
5590#[derive(Copy, Clone)]
5591pub union drm_amdgpu_cs_chunk_data__bindgen_ty_1 {
5592 pub ib_data: drm_amdgpu_cs_chunk_ib,
5593 pub fence_data: drm_amdgpu_cs_chunk_fence,
5594}
5595#[repr(C)]
5596#[derive(Debug, Copy, Clone)]
5597pub struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
5598 pub shadow_va: __u64,
5599 pub csa_va: __u64,
5600 pub gds_va: __u64,
5601 pub flags: __u64,
5602}
5603#[repr(C)]
5604#[derive(Debug, Copy, Clone)]
5605pub struct drm_amdgpu_query_fw {
5606 #[doc = " AMDGPU_INFO_FW_*"]
5607 pub fw_type: __u32,
5608 #[doc = " Index of the IP if there are more IPs of\n the same type."]
5609 pub ip_instance: __u32,
5610 #[doc = " Index of the engine. Whether this is used depends\n on the firmware type. (e.g. MEC, SDMA)"]
5611 pub index: __u32,
5612 pub _pad: __u32,
5613}
5614#[repr(C)]
5615#[derive(Copy, Clone)]
5616pub struct drm_amdgpu_info {
5617 pub return_pointer: __u64,
5618 pub return_size: __u32,
5619 pub query: __u32,
5620 pub __bindgen_anon_1: drm_amdgpu_info__bindgen_ty_1,
5621}
5622#[repr(C)]
5623#[derive(Copy, Clone)]
5624pub union drm_amdgpu_info__bindgen_ty_1 {
5625 pub mode_crtc: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_1,
5626 pub query_hw_ip: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_2,
5627 pub read_mmr_reg: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_3,
5628 pub query_fw: drm_amdgpu_query_fw,
5629 pub vbios_info: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_4,
5630 pub sensor_info: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_5,
5631 pub video_cap: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_6,
5632}
5633#[repr(C)]
5634#[derive(Debug, Copy, Clone)]
5635pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_1 {
5636 pub id: __u32,
5637 pub _pad: __u32,
5638}
5639#[repr(C)]
5640#[derive(Debug, Copy, Clone)]
5641pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_2 {
5642 #[doc = " AMDGPU_HW_IP_*"]
5643 pub type_: __u32,
5644 #[doc = " Index of the IP if there are more IPs of the same\n type. Ignored by AMDGPU_INFO_HW_IP_COUNT."]
5645 pub ip_instance: __u32,
5646}
5647#[repr(C)]
5648#[derive(Debug, Copy, Clone)]
5649pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_3 {
5650 pub dword_offset: __u32,
5651 #[doc = " number of registers to read"]
5652 pub count: __u32,
5653 pub instance: __u32,
5654 #[doc = " For future use, no flags defined so far"]
5655 pub flags: __u32,
5656}
5657#[repr(C)]
5658#[derive(Debug, Copy, Clone)]
5659pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_4 {
5660 pub type_: __u32,
5661 pub offset: __u32,
5662}
5663#[repr(C)]
5664#[derive(Debug, Copy, Clone)]
5665pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_5 {
5666 pub type_: __u32,
5667}
5668#[repr(C)]
5669#[derive(Debug, Copy, Clone)]
5670pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_6 {
5671 pub type_: __u32,
5672}
5673#[repr(C)]
5674#[derive(Debug, Copy, Clone)]
5675pub struct drm_amdgpu_info_gds {
5676 #[doc = " GDS GFX partition size"]
5677 pub gds_gfx_partition_size: __u32,
5678 #[doc = " GDS compute partition size"]
5679 pub compute_partition_size: __u32,
5680 #[doc = " total GDS memory size"]
5681 pub gds_total_size: __u32,
5682 #[doc = " GWS size per GFX partition"]
5683 pub gws_per_gfx_partition: __u32,
5684 #[doc = " GSW size per compute partition"]
5685 pub gws_per_compute_partition: __u32,
5686 #[doc = " OA size per GFX partition"]
5687 pub oa_per_gfx_partition: __u32,
5688 #[doc = " OA size per compute partition"]
5689 pub oa_per_compute_partition: __u32,
5690 pub _pad: __u32,
5691}
5692#[repr(C)]
5693#[derive(Debug, Copy, Clone)]
5694pub struct drm_amdgpu_info_vram_gtt {
5695 pub vram_size: __u64,
5696 pub vram_cpu_accessible_size: __u64,
5697 pub gtt_size: __u64,
5698}
5699#[repr(C)]
5700#[derive(Debug, Copy, Clone)]
5701pub struct drm_amdgpu_heap_info {
5702 #[doc = " max. physical memory"]
5703 pub total_heap_size: __u64,
5704 #[doc = " Theoretical max. available memory in the given heap"]
5705 pub usable_heap_size: __u64,
5706 #[doc = " Number of bytes allocated in the heap. This includes all processes\n and private allocations in the kernel. It changes when new buffers\n are allocated, freed, and moved. It cannot be larger than\n heap_size."]
5707 pub heap_usage: __u64,
5708 #[doc = " Theoretical possible max. size of buffer which\n could be allocated in the given heap"]
5709 pub max_allocation: __u64,
5710}
5711#[repr(C)]
5712#[derive(Debug, Copy, Clone)]
5713pub struct drm_amdgpu_memory_info {
5714 pub vram: drm_amdgpu_heap_info,
5715 pub cpu_accessible_vram: drm_amdgpu_heap_info,
5716 pub gtt: drm_amdgpu_heap_info,
5717}
5718#[repr(C)]
5719#[derive(Debug, Copy, Clone)]
5720pub struct drm_amdgpu_info_firmware {
5721 pub ver: __u32,
5722 pub feature: __u32,
5723}
5724#[repr(C)]
5725#[derive(Debug, Copy, Clone)]
5726pub struct drm_amdgpu_info_vbios {
5727 pub name: [__u8; 64usize],
5728 pub vbios_pn: [__u8; 64usize],
5729 pub version: __u32,
5730 pub pad: __u32,
5731 pub vbios_ver_str: [__u8; 32usize],
5732 pub date: [__u8; 32usize],
5733}
5734#[repr(C)]
5735#[derive(Debug, Copy, Clone)]
5736pub struct drm_amdgpu_info_device {
5737 #[doc = " PCI Device ID"]
5738 pub device_id: __u32,
5739 #[doc = " Internal chip revision: A0, A1, etc.)"]
5740 pub chip_rev: __u32,
5741 pub external_rev: __u32,
5742 #[doc = " Revision id in PCI Config space"]
5743 pub pci_rev: __u32,
5744 pub family: __u32,
5745 pub num_shader_engines: __u32,
5746 pub num_shader_arrays_per_engine: __u32,
5747 pub gpu_counter_freq: __u32,
5748 pub max_engine_clock: __u64,
5749 pub max_memory_clock: __u64,
5750 pub cu_active_number: __u32,
5751 pub cu_ao_mask: __u32,
5752 pub cu_bitmap: [[__u32; 4usize]; 4usize],
5753 #[doc = " Render backend pipe mask. One render backend is CB+DB."]
5754 pub enabled_rb_pipes_mask: __u32,
5755 pub num_rb_pipes: __u32,
5756 pub num_hw_gfx_contexts: __u32,
5757 pub pcie_gen: __u32,
5758 pub ids_flags: __u64,
5759 #[doc = " Starting virtual address for UMDs."]
5760 pub virtual_address_offset: __u64,
5761 #[doc = " The maximum virtual address"]
5762 pub virtual_address_max: __u64,
5763 #[doc = " Required alignment of virtual addresses."]
5764 pub virtual_address_alignment: __u32,
5765 #[doc = " Page table entry - fragment size"]
5766 pub pte_fragment_size: __u32,
5767 pub gart_page_size: __u32,
5768 #[doc = " constant engine ram size"]
5769 pub ce_ram_size: __u32,
5770 #[doc = " video memory type info"]
5771 pub vram_type: __u32,
5772 #[doc = " video memory bit width"]
5773 pub vram_bit_width: __u32,
5774 pub vce_harvest_config: __u32,
5775 pub gc_double_offchip_lds_buf: __u32,
5776 pub prim_buf_gpu_addr: __u64,
5777 pub pos_buf_gpu_addr: __u64,
5778 pub cntl_sb_buf_gpu_addr: __u64,
5779 pub param_buf_gpu_addr: __u64,
5780 pub prim_buf_size: __u32,
5781 pub pos_buf_size: __u32,
5782 pub cntl_sb_buf_size: __u32,
5783 pub param_buf_size: __u32,
5784 pub wave_front_size: __u32,
5785 pub num_shader_visible_vgprs: __u32,
5786 pub num_cu_per_sh: __u32,
5787 pub num_tcc_blocks: __u32,
5788 pub gs_vgt_table_depth: __u32,
5789 pub gs_prim_buffer_depth: __u32,
5790 pub max_gs_waves_per_vgt: __u32,
5791 pub pcie_num_lanes: __u32,
5792 pub cu_ao_bitmap: [[__u32; 4usize]; 4usize],
5793 #[doc = " Starting high virtual address for UMDs."]
5794 pub high_va_offset: __u64,
5795 #[doc = " The maximum high virtual address"]
5796 pub high_va_max: __u64,
5797 pub pa_sc_tile_steering_override: __u32,
5798 pub tcc_disabled_mask: __u64,
5799 pub min_engine_clock: __u64,
5800 pub min_memory_clock: __u64,
5801 pub tcp_cache_size: __u32,
5802 pub num_sqc_per_wgp: __u32,
5803 pub sqc_data_cache_size: __u32,
5804 pub sqc_inst_cache_size: __u32,
5805 pub gl1c_cache_size: __u32,
5806 pub gl2c_cache_size: __u32,
5807 pub mall_size: __u64,
5808 pub enabled_rb_pipes_mask_hi: __u32,
5809 pub shadow_size: __u32,
5810 pub shadow_alignment: __u32,
5811 pub csa_size: __u32,
5812 pub csa_alignment: __u32,
5813}
5814#[repr(C)]
5815#[derive(Debug, Copy, Clone)]
5816pub struct drm_amdgpu_info_hw_ip {
5817 #[doc = " Version of h/w IP"]
5818 pub hw_ip_version_major: __u32,
5819 pub hw_ip_version_minor: __u32,
5820 #[doc = " Capabilities"]
5821 pub capabilities_flags: __u64,
5822 #[doc = " command buffer address start alignment"]
5823 pub ib_start_alignment: __u32,
5824 #[doc = " command buffer size alignment"]
5825 pub ib_size_alignment: __u32,
5826 #[doc = " Bitmask of available rings. Bit 0 means ring 0, etc."]
5827 pub available_rings: __u32,
5828 #[doc = " version info: bits 23:16 major, 15:8 minor, 7:0 revision"]
5829 pub ip_discovery_version: __u32,
5830}
5831#[repr(C)]
5832#[derive(Debug, Copy, Clone)]
5833pub struct drm_amdgpu_info_num_handles {
5834 #[doc = " Max handles as supported by firmware for UVD"]
5835 pub uvd_max_handles: __u32,
5836 #[doc = " Handles currently in use for UVD"]
5837 pub uvd_used_handles: __u32,
5838}
5839#[repr(C)]
5840#[derive(Debug, Copy, Clone)]
5841pub struct drm_amdgpu_info_vce_clock_table_entry {
5842 #[doc = " System clock"]
5843 pub sclk: __u32,
5844 #[doc = " Memory clock"]
5845 pub mclk: __u32,
5846 #[doc = " VCE clock"]
5847 pub eclk: __u32,
5848 pub pad: __u32,
5849}
5850#[repr(C)]
5851#[derive(Debug, Copy, Clone)]
5852pub struct drm_amdgpu_info_vce_clock_table {
5853 pub entries: [drm_amdgpu_info_vce_clock_table_entry; 6usize],
5854 pub num_valid_entries: __u32,
5855 pub pad: __u32,
5856}
5857#[repr(C)]
5858#[derive(Debug, Copy, Clone)]
5859pub struct drm_amdgpu_info_video_codec_info {
5860 pub valid: __u32,
5861 pub max_width: __u32,
5862 pub max_height: __u32,
5863 pub max_pixels_per_frame: __u32,
5864 pub max_level: __u32,
5865 pub pad: __u32,
5866}
5867#[repr(C)]
5868#[derive(Debug, Copy, Clone)]
5869pub struct drm_amdgpu_info_video_caps {
5870 pub codec_info: [drm_amdgpu_info_video_codec_info; 8usize],
5871}
5872#[repr(C)]
5873#[derive(Debug, Copy, Clone)]
5874pub struct drm_amdgpu_info_gpuvm_fault {
5875 pub addr: __u64,
5876 pub status: __u32,
5877 pub vmhub: __u32,
5878}
5879pub const atom_bios_header_version_def_ATOM_MAJOR_VERSION: atom_bios_header_version_def = 3;
5880pub const atom_bios_header_version_def_ATOM_MINOR_VERSION: atom_bios_header_version_def = 3;
5881pub type atom_bios_header_version_def = ::core::ffi::c_uint;
5882pub const atom_crtc_def_ATOM_CRTC1: atom_crtc_def = 0;
5883pub const atom_crtc_def_ATOM_CRTC2: atom_crtc_def = 1;
5884pub const atom_crtc_def_ATOM_CRTC3: atom_crtc_def = 2;
5885pub const atom_crtc_def_ATOM_CRTC4: atom_crtc_def = 3;
5886pub const atom_crtc_def_ATOM_CRTC5: atom_crtc_def = 4;
5887pub const atom_crtc_def_ATOM_CRTC6: atom_crtc_def = 5;
5888pub const atom_crtc_def_ATOM_CRTC_INVALID: atom_crtc_def = 255;
5889pub type atom_crtc_def = ::core::ffi::c_uint;
5890pub const atom_ppll_def_ATOM_PPLL0: atom_ppll_def = 2;
5891pub const atom_ppll_def_ATOM_GCK_DFS: atom_ppll_def = 8;
5892pub const atom_ppll_def_ATOM_FCH_CLK: atom_ppll_def = 9;
5893pub const atom_ppll_def_ATOM_DP_DTO: atom_ppll_def = 11;
5894pub const atom_ppll_def_ATOM_COMBOPHY_PLL0: atom_ppll_def = 20;
5895pub const atom_ppll_def_ATOM_COMBOPHY_PLL1: atom_ppll_def = 21;
5896pub const atom_ppll_def_ATOM_COMBOPHY_PLL2: atom_ppll_def = 22;
5897pub const atom_ppll_def_ATOM_COMBOPHY_PLL3: atom_ppll_def = 23;
5898pub const atom_ppll_def_ATOM_COMBOPHY_PLL4: atom_ppll_def = 24;
5899pub const atom_ppll_def_ATOM_COMBOPHY_PLL5: atom_ppll_def = 25;
5900pub const atom_ppll_def_ATOM_PPLL_INVALID: atom_ppll_def = 255;
5901pub type atom_ppll_def = ::core::ffi::c_uint;
5902pub const atom_dig_def_ASIC_INT_DIG1_ENCODER_ID: atom_dig_def = 3;
5903pub const atom_dig_def_ASIC_INT_DIG2_ENCODER_ID: atom_dig_def = 9;
5904pub const atom_dig_def_ASIC_INT_DIG3_ENCODER_ID: atom_dig_def = 10;
5905pub const atom_dig_def_ASIC_INT_DIG4_ENCODER_ID: atom_dig_def = 11;
5906pub const atom_dig_def_ASIC_INT_DIG5_ENCODER_ID: atom_dig_def = 12;
5907pub const atom_dig_def_ASIC_INT_DIG6_ENCODER_ID: atom_dig_def = 13;
5908pub const atom_dig_def_ASIC_INT_DIG7_ENCODER_ID: atom_dig_def = 14;
5909pub type atom_dig_def = ::core::ffi::c_uint;
5910pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP: atom_encode_mode_def = 0;
5911pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_SST: atom_encode_mode_def = 0;
5912pub const atom_encode_mode_def_ATOM_ENCODER_MODE_LVDS: atom_encode_mode_def = 1;
5913pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DVI: atom_encode_mode_def = 2;
5914pub const atom_encode_mode_def_ATOM_ENCODER_MODE_HDMI: atom_encode_mode_def = 3;
5915pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_AUDIO: atom_encode_mode_def = 5;
5916pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_MST: atom_encode_mode_def = 5;
5917pub const atom_encode_mode_def_ATOM_ENCODER_MODE_CRT: atom_encode_mode_def = 15;
5918pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DVO: atom_encode_mode_def = 16;
5919pub type atom_encode_mode_def = ::core::ffi::c_uint;
5920pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P1PLL: atom_encoder_refclk_src_def = 0;
5921pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P2PLL: atom_encoder_refclk_src_def = 1;
5922pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P3PLL: atom_encoder_refclk_src_def = 2;
5923pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_EXTCLK: atom_encoder_refclk_src_def = 3;
5924pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_INVALID: atom_encoder_refclk_src_def = 255;
5925pub type atom_encoder_refclk_src_def = ::core::ffi::c_uint;
5926pub const atom_scaler_def_ATOM_SCALER_DISABLE: atom_scaler_def = 0;
5927pub const atom_scaler_def_ATOM_SCALER_CENTER: atom_scaler_def = 1;
5928pub const atom_scaler_def_ATOM_SCALER_EXPANSION: atom_scaler_def = 2;
5929pub type atom_scaler_def = ::core::ffi::c_uint;
5930pub const atom_operation_def_ATOM_DISABLE: atom_operation_def = 0;
5931pub const atom_operation_def_ATOM_ENABLE: atom_operation_def = 1;
5932pub const atom_operation_def_ATOM_INIT: atom_operation_def = 7;
5933pub const atom_operation_def_ATOM_GET_STATUS: atom_operation_def = 8;
5934pub type atom_operation_def = ::core::ffi::c_uint;
5935pub const atom_embedded_display_op_def_ATOM_LCD_BL_OFF: atom_embedded_display_op_def = 2;
5936pub const atom_embedded_display_op_def_ATOM_LCD_BL_OM: atom_embedded_display_op_def = 3;
5937pub const atom_embedded_display_op_def_ATOM_LCD_BL_BRIGHTNESS_CONTROL:
5938 atom_embedded_display_op_def = 4;
5939pub const atom_embedded_display_op_def_ATOM_LCD_SELFTEST_START: atom_embedded_display_op_def = 5;
5940pub const atom_embedded_display_op_def_ATOM_LCD_SELFTEST_STOP: atom_embedded_display_op_def = 6;
5941pub type atom_embedded_display_op_def = ::core::ffi::c_uint;
5942pub const atom_spread_spectrum_mode_ATOM_SS_CENTER_OR_DOWN_MODE_MASK: atom_spread_spectrum_mode = 1;
5943pub const atom_spread_spectrum_mode_ATOM_SS_DOWN_SPREAD_MODE: atom_spread_spectrum_mode = 0;
5944pub const atom_spread_spectrum_mode_ATOM_SS_CENTRE_SPREAD_MODE: atom_spread_spectrum_mode = 1;
5945pub const atom_spread_spectrum_mode_ATOM_INT_OR_EXT_SS_MASK: atom_spread_spectrum_mode = 2;
5946pub const atom_spread_spectrum_mode_ATOM_INTERNAL_SS_MASK: atom_spread_spectrum_mode = 0;
5947pub const atom_spread_spectrum_mode_ATOM_EXTERNAL_SS_MASK: atom_spread_spectrum_mode = 2;
5948pub type atom_spread_spectrum_mode = ::core::ffi::c_uint;
5949pub const atom_panel_bit_per_color_PANEL_BPC_UNDEFINE: atom_panel_bit_per_color = 0;
5950pub const atom_panel_bit_per_color_PANEL_6BIT_PER_COLOR: atom_panel_bit_per_color = 1;
5951pub const atom_panel_bit_per_color_PANEL_8BIT_PER_COLOR: atom_panel_bit_per_color = 2;
5952pub const atom_panel_bit_per_color_PANEL_10BIT_PER_COLOR: atom_panel_bit_per_color = 3;
5953pub const atom_panel_bit_per_color_PANEL_12BIT_PER_COLOR: atom_panel_bit_per_color = 4;
5954pub const atom_panel_bit_per_color_PANEL_16BIT_PER_COLOR: atom_panel_bit_per_color = 5;
5955pub type atom_panel_bit_per_color = ::core::ffi::c_uint;
5956pub const atom_voltage_type_VOLTAGE_TYPE_VDDC: atom_voltage_type = 1;
5957pub const atom_voltage_type_VOLTAGE_TYPE_MVDDC: atom_voltage_type = 2;
5958pub const atom_voltage_type_VOLTAGE_TYPE_MVDDQ: atom_voltage_type = 3;
5959pub const atom_voltage_type_VOLTAGE_TYPE_VDDCI: atom_voltage_type = 4;
5960pub const atom_voltage_type_VOLTAGE_TYPE_VDDGFX: atom_voltage_type = 5;
5961pub const atom_voltage_type_VOLTAGE_TYPE_PCC: atom_voltage_type = 6;
5962pub const atom_voltage_type_VOLTAGE_TYPE_MVPP: atom_voltage_type = 7;
5963pub const atom_voltage_type_VOLTAGE_TYPE_LEDDPM: atom_voltage_type = 8;
5964pub const atom_voltage_type_VOLTAGE_TYPE_PCC_MVDD: atom_voltage_type = 9;
5965pub const atom_voltage_type_VOLTAGE_TYPE_PCIE_VDDC: atom_voltage_type = 10;
5966pub const atom_voltage_type_VOLTAGE_TYPE_PCIE_VDDR: atom_voltage_type = 11;
5967pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_1: atom_voltage_type = 17;
5968pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_2: atom_voltage_type = 18;
5969pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_3: atom_voltage_type = 19;
5970pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_4: atom_voltage_type = 20;
5971pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_5: atom_voltage_type = 21;
5972pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_6: atom_voltage_type = 22;
5973pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_7: atom_voltage_type = 23;
5974pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_8: atom_voltage_type = 24;
5975pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_9: atom_voltage_type = 25;
5976pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_10: atom_voltage_type = 26;
5977pub type atom_voltage_type = ::core::ffi::c_uint;
5978pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_GDDR5: atom_dgpu_vram_type = 80;
5979pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM2: atom_dgpu_vram_type = 96;
5980pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM2E: atom_dgpu_vram_type = 97;
5981pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_GDDR6: atom_dgpu_vram_type = 112;
5982pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM3: atom_dgpu_vram_type = 128;
5983pub type atom_dgpu_vram_type = ::core::ffi::c_uint;
5984pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 0;
5985pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 1;
5986pub const atom_dp_vs_preemph_def_DP_VS_LEVEL2_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 2;
5987pub const atom_dp_vs_preemph_def_DP_VS_LEVEL3_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 3;
5988pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 8;
5989pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 9;
5990pub const atom_dp_vs_preemph_def_DP_VS_LEVEL2_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 10;
5991pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL2: atom_dp_vs_preemph_def = 16;
5992pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL2: atom_dp_vs_preemph_def = 17;
5993pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL3: atom_dp_vs_preemph_def = 24;
5994pub type atom_dp_vs_preemph_def = ::core::ffi::c_uint;
5995pub const atombios_image_offset_OFFSET_TO_ATOM_ROM_HEADER_POINTER: atombios_image_offset = 72;
5996pub const atombios_image_offset_OFFSET_TO_ATOM_ROM_IMAGE_SIZE: atombios_image_offset = 2;
5997pub const atombios_image_offset_OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE: atombios_image_offset = 148;
5998pub const atombios_image_offset_MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE: atombios_image_offset = 20;
5999pub const atombios_image_offset_OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS: atombios_image_offset =
6000 47;
6001pub const atombios_image_offset_OFFSET_TO_GET_ATOMBIOS_STRING_START: atombios_image_offset = 110;
6002pub const atombios_image_offset_OFFSET_TO_VBIOS_PART_NUMBER: atombios_image_offset = 128;
6003pub const atombios_image_offset_OFFSET_TO_VBIOS_DATE: atombios_image_offset = 80;
6004pub type atombios_image_offset = ::core::ffi::c_uint;
6005#[doc = " Common header for all tables (Data table, Command function).\n Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.\n And the pointer actually points to this header."]
6006#[repr(C, packed)]
6007#[derive(Debug, Copy, Clone)]
6008pub struct atom_common_table_header {
6009 pub structuresize: u16,
6010 pub format_revision: u8,
6011 pub content_revision: u8,
6012}
6013#[doc = " Structure stores the ROM header."]
6014#[repr(C, packed)]
6015#[derive(Debug, Copy, Clone)]
6016pub struct atom_rom_header_v2_2 {
6017 pub table_header: atom_common_table_header,
6018 pub atom_bios_string: [u8; 4usize],
6019 pub bios_segment_address: u16,
6020 pub protectedmodeoffset: u16,
6021 pub configfilenameoffset: u16,
6022 pub crc_block_offset: u16,
6023 pub vbios_bootupmessageoffset: u16,
6024 pub int10_offset: u16,
6025 pub pcibusdevinitcode: u16,
6026 pub iobaseaddress: u16,
6027 pub subsystem_vendor_id: u16,
6028 pub subsystem_id: u16,
6029 pub pci_info_offset: u16,
6030 pub masterhwfunction_offset: u16,
6031 pub masterdatatable_offset: u16,
6032 pub reserved: u16,
6033 pub pspdirtableoffset: u32,
6034}
6035#[doc = " Structures used in Command.mtb, each function name is not given here since those function could change from time to time\n The real functionality of each function is associated with the parameter structure version when defined\n For all internal cmd function definitions, please reference to atomstruct.h"]
6036#[repr(C, packed)]
6037#[derive(Debug, Copy, Clone)]
6038pub struct atom_master_list_of_command_functions_v2_1 {
6039 pub asic_init: u16,
6040 pub cmd_function1: u16,
6041 pub cmd_function2: u16,
6042 pub cmd_function3: u16,
6043 pub digxencodercontrol: u16,
6044 pub cmd_function5: u16,
6045 pub cmd_function6: u16,
6046 pub cmd_function7: u16,
6047 pub cmd_function8: u16,
6048 pub cmd_function9: u16,
6049 pub setengineclock: u16,
6050 pub setmemoryclock: u16,
6051 pub setpixelclock: u16,
6052 pub enabledisppowergating: u16,
6053 pub cmd_function14: u16,
6054 pub cmd_function15: u16,
6055 pub cmd_function16: u16,
6056 pub cmd_function17: u16,
6057 pub cmd_function18: u16,
6058 pub cmd_function19: u16,
6059 pub cmd_function20: u16,
6060 pub cmd_function21: u16,
6061 pub cmd_function22: u16,
6062 pub cmd_function23: u16,
6063 pub cmd_function24: u16,
6064 pub cmd_function25: u16,
6065 pub cmd_function26: u16,
6066 pub cmd_function27: u16,
6067 pub cmd_function28: u16,
6068 pub cmd_function29: u16,
6069 pub cmd_function30: u16,
6070 pub cmd_function31: u16,
6071 pub cmd_function32: u16,
6072 pub cmd_function33: u16,
6073 pub blankcrtc: u16,
6074 pub enablecrtc: u16,
6075 pub cmd_function36: u16,
6076 pub cmd_function37: u16,
6077 pub cmd_function38: u16,
6078 pub cmd_function39: u16,
6079 pub cmd_function40: u16,
6080 pub getsmuclockinfo: u16,
6081 pub selectcrtc_source: u16,
6082 pub cmd_function43: u16,
6083 pub cmd_function44: u16,
6084 pub cmd_function45: u16,
6085 pub setdceclock: u16,
6086 pub getmemoryclock: u16,
6087 pub getengineclock: u16,
6088 pub setcrtc_usingdtdtiming: u16,
6089 pub externalencodercontrol: u16,
6090 pub cmd_function51: u16,
6091 pub cmd_function52: u16,
6092 pub cmd_function53: u16,
6093 pub processi2cchanneltransaction: u16,
6094 pub cmd_function55: u16,
6095 pub cmd_function56: u16,
6096 pub cmd_function57: u16,
6097 pub cmd_function58: u16,
6098 pub cmd_function59: u16,
6099 pub computegpuclockparam: u16,
6100 pub cmd_function61: u16,
6101 pub cmd_function62: u16,
6102 pub dynamicmemorysettings: u16,
6103 pub memorytraining: u16,
6104 pub cmd_function65: u16,
6105 pub cmd_function66: u16,
6106 pub setvoltage: u16,
6107 pub cmd_function68: u16,
6108 pub readefusevalue: u16,
6109 pub cmd_function70: u16,
6110 pub cmd_function71: u16,
6111 pub cmd_function72: u16,
6112 pub cmd_function73: u16,
6113 pub cmd_function74: u16,
6114 pub cmd_function75: u16,
6115 pub dig1transmittercontrol: u16,
6116 pub cmd_function77: u16,
6117 pub processauxchanneltransaction: u16,
6118 pub cmd_function79: u16,
6119 pub getvoltageinfo: u16,
6120}
6121#[repr(C)]
6122#[derive(Debug, Copy, Clone)]
6123pub struct atom_master_command_function_v2_1 {
6124 pub table_header: atom_common_table_header,
6125 pub listofcmdfunctions: atom_master_list_of_command_functions_v2_1,
6126}
6127#[doc = " Structures used in every command function"]
6128#[repr(C)]
6129#[derive(Debug, Copy, Clone)]
6130pub struct atom_function_attribute {
6131 pub _bitfield_align_1: [u8; 0],
6132 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 2usize]>,
6133}
6134impl atom_function_attribute {
6135 #[inline]
6136 pub fn ws_in_bytes(&self) -> u16 {
6137 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u16) }
6138 }
6139 #[inline]
6140 pub fn set_ws_in_bytes(&mut self, val: u16) {
6141 unsafe {
6142 let val: u16 = ::core::mem::transmute(val);
6143 self._bitfield_1.set(0usize, 8u8, val as u64)
6144 }
6145 }
6146 #[inline]
6147 pub unsafe fn ws_in_bytes_raw(this: *const Self) -> u16 {
6148 unsafe {
6149 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
6150 ::core::ptr::addr_of!((*this)._bitfield_1),
6151 0usize,
6152 8u8,
6153 ) as u16)
6154 }
6155 }
6156 #[inline]
6157 pub unsafe fn set_ws_in_bytes_raw(this: *mut Self, val: u16) {
6158 unsafe {
6159 let val: u16 = ::core::mem::transmute(val);
6160 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
6161 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
6162 0usize,
6163 8u8,
6164 val as u64,
6165 )
6166 }
6167 }
6168 #[inline]
6169 pub fn ps_in_bytes(&self) -> u16 {
6170 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 7u8) as u16) }
6171 }
6172 #[inline]
6173 pub fn set_ps_in_bytes(&mut self, val: u16) {
6174 unsafe {
6175 let val: u16 = ::core::mem::transmute(val);
6176 self._bitfield_1.set(8usize, 7u8, val as u64)
6177 }
6178 }
6179 #[inline]
6180 pub unsafe fn ps_in_bytes_raw(this: *const Self) -> u16 {
6181 unsafe {
6182 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
6183 ::core::ptr::addr_of!((*this)._bitfield_1),
6184 8usize,
6185 7u8,
6186 ) as u16)
6187 }
6188 }
6189 #[inline]
6190 pub unsafe fn set_ps_in_bytes_raw(this: *mut Self, val: u16) {
6191 unsafe {
6192 let val: u16 = ::core::mem::transmute(val);
6193 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
6194 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
6195 8usize,
6196 7u8,
6197 val as u64,
6198 )
6199 }
6200 }
6201 #[inline]
6202 pub fn updated_by_util(&self) -> u16 {
6203 unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u16) }
6204 }
6205 #[inline]
6206 pub fn set_updated_by_util(&mut self, val: u16) {
6207 unsafe {
6208 let val: u16 = ::core::mem::transmute(val);
6209 self._bitfield_1.set(15usize, 1u8, val as u64)
6210 }
6211 }
6212 #[inline]
6213 pub unsafe fn updated_by_util_raw(this: *const Self) -> u16 {
6214 unsafe {
6215 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
6216 ::core::ptr::addr_of!((*this)._bitfield_1),
6217 15usize,
6218 1u8,
6219 ) as u16)
6220 }
6221 }
6222 #[inline]
6223 pub unsafe fn set_updated_by_util_raw(this: *mut Self, val: u16) {
6224 unsafe {
6225 let val: u16 = ::core::mem::transmute(val);
6226 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
6227 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
6228 15usize,
6229 1u8,
6230 val as u64,
6231 )
6232 }
6233 }
6234 #[inline]
6235 pub fn new_bitfield_1(
6236 ws_in_bytes: u16,
6237 ps_in_bytes: u16,
6238 updated_by_util: u16,
6239 ) -> __BindgenBitfieldUnit<[u8; 2usize]> {
6240 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 2usize]> = Default::default();
6241 __bindgen_bitfield_unit.set(0usize, 8u8, {
6242 let ws_in_bytes: u16 = unsafe { ::core::mem::transmute(ws_in_bytes) };
6243 ws_in_bytes as u64
6244 });
6245 __bindgen_bitfield_unit.set(8usize, 7u8, {
6246 let ps_in_bytes: u16 = unsafe { ::core::mem::transmute(ps_in_bytes) };
6247 ps_in_bytes as u64
6248 });
6249 __bindgen_bitfield_unit.set(15usize, 1u8, {
6250 let updated_by_util: u16 = unsafe { ::core::mem::transmute(updated_by_util) };
6251 updated_by_util as u64
6252 });
6253 __bindgen_bitfield_unit
6254 }
6255}
6256#[doc = " Common header for all hw functions.\n Every function pointed by _master_list_of_hw_function has this common header.\n And the pointer actually points to this header."]
6257#[repr(C)]
6258#[derive(Debug, Copy, Clone)]
6259pub struct atom_rom_hw_function_header {
6260 pub func_header: atom_common_table_header,
6261 pub func_attrib: atom_function_attribute,
6262}
6263#[doc = " Structures used in data.mtb, each data table name is not given here since those data table could change from time to time\n The real name of each table is given when its data structure version is defined"]
6264#[repr(C, packed)]
6265#[derive(Debug, Copy, Clone)]
6266pub struct atom_master_list_of_data_tables_v2_1 {
6267 pub utilitypipeline: u16,
6268 pub multimedia_info: u16,
6269 pub smc_dpm_info: u16,
6270 pub sw_datatable3: u16,
6271 pub firmwareinfo: u16,
6272 pub sw_datatable5: u16,
6273 pub lcd_info: u16,
6274 pub sw_datatable7: u16,
6275 pub smu_info: u16,
6276 pub sw_datatable9: u16,
6277 pub sw_datatable10: u16,
6278 pub vram_usagebyfirmware: u16,
6279 pub gpio_pin_lut: u16,
6280 pub sw_datatable13: u16,
6281 pub gfx_info: u16,
6282 pub powerplayinfo: u16,
6283 pub sw_datatable16: u16,
6284 pub sw_datatable17: u16,
6285 pub sw_datatable18: u16,
6286 pub sw_datatable19: u16,
6287 pub sw_datatable20: u16,
6288 pub sw_datatable21: u16,
6289 pub displayobjectinfo: u16,
6290 pub indirectioaccess: u16,
6291 pub umc_info: u16,
6292 pub sw_datatable25: u16,
6293 pub sw_datatable26: u16,
6294 pub dce_info: u16,
6295 pub vram_info: u16,
6296 pub sw_datatable29: u16,
6297 pub integratedsysteminfo: u16,
6298 pub asic_profiling_info: u16,
6299 pub voltageobject_info: u16,
6300 pub sw_datatable33: u16,
6301 pub sw_datatable34: u16,
6302}
6303#[repr(C)]
6304#[derive(Debug, Copy, Clone)]
6305pub struct atom_master_data_table_v2_1 {
6306 pub table_header: atom_common_table_header,
6307 pub listOfdatatables: atom_master_list_of_data_tables_v2_1,
6308}
6309#[repr(C, packed)]
6310#[derive(Debug, Copy, Clone)]
6311pub struct atom_dtd_format {
6312 pub pixclk: u16,
6313 pub h_active: u16,
6314 pub h_blanking_time: u16,
6315 pub v_active: u16,
6316 pub v_blanking_time: u16,
6317 pub h_sync_offset: u16,
6318 pub h_sync_width: u16,
6319 pub v_sync_offset: u16,
6320 pub v_syncwidth: u16,
6321 pub reserved: u16,
6322 pub reserved0: u16,
6323 pub h_border: u8,
6324 pub v_border: u8,
6325 pub miscinfo: u16,
6326 pub atom_mode_id: u8,
6327 pub refreshrate: u8,
6328}
6329pub const atom_dtd_format_modemiscinfo_ATOM_HSYNC_POLARITY: atom_dtd_format_modemiscinfo = 2;
6330pub const atom_dtd_format_modemiscinfo_ATOM_VSYNC_POLARITY: atom_dtd_format_modemiscinfo = 4;
6331pub const atom_dtd_format_modemiscinfo_ATOM_H_REPLICATIONBY2: atom_dtd_format_modemiscinfo = 16;
6332pub const atom_dtd_format_modemiscinfo_ATOM_V_REPLICATIONBY2: atom_dtd_format_modemiscinfo = 32;
6333pub const atom_dtd_format_modemiscinfo_ATOM_INTERLACE: atom_dtd_format_modemiscinfo = 128;
6334pub const atom_dtd_format_modemiscinfo_ATOM_COMPOSITESYNC: atom_dtd_format_modemiscinfo = 64;
6335pub type atom_dtd_format_modemiscinfo = ::core::ffi::c_uint;
6336#[repr(C, packed)]
6337#[derive(Debug, Copy, Clone)]
6338pub struct atom_firmware_info_v3_1 {
6339 pub table_header: atom_common_table_header,
6340 pub firmware_revision: u32,
6341 pub bootup_sclk_in10khz: u32,
6342 pub bootup_mclk_in10khz: u32,
6343 pub firmware_capability: u32,
6344 pub main_call_parser_entry: u32,
6345 pub bios_scratch_reg_startaddr: u32,
6346 pub bootup_vddc_mv: u16,
6347 pub bootup_vddci_mv: u16,
6348 pub bootup_mvddc_mv: u16,
6349 pub bootup_vddgfx_mv: u16,
6350 pub mem_module_id: u8,
6351 pub coolingsolution_id: u8,
6352 pub reserved1: [u8; 2usize],
6353 pub mc_baseaddr_high: u32,
6354 pub mc_baseaddr_low: u32,
6355 pub reserved2: [u32; 6usize],
6356}
6357pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_FIRMWARE_POSTED:
6358 atombios_firmware_capability = 1;
6359pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION:
6360 atombios_firmware_capability = 2;
6361pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_WMI_SUPPORT: atombios_firmware_capability =
6362 64;
6363pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_HWEMU_ENABLE:
6364 atombios_firmware_capability = 128;
6365pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG:
6366 atombios_firmware_capability = 256;
6367pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_SRAM_ECC: atombios_firmware_capability =
6368 512;
6369pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING:
6370 atombios_firmware_capability = 1024;
6371pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT:
6372 atombios_firmware_capability = 32768;
6373pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE:
6374 atombios_firmware_capability = 131072;
6375pub type atombios_firmware_capability = ::core::ffi::c_uint;
6376pub const atom_cooling_solution_id_AIR_COOLING: atom_cooling_solution_id = 0;
6377pub const atom_cooling_solution_id_LIQUID_COOLING: atom_cooling_solution_id = 1;
6378pub type atom_cooling_solution_id = ::core::ffi::c_uint;
6379#[repr(C, packed)]
6380#[derive(Debug, Copy, Clone)]
6381pub struct atom_firmware_info_v3_2 {
6382 pub table_header: atom_common_table_header,
6383 pub firmware_revision: u32,
6384 pub bootup_sclk_in10khz: u32,
6385 pub bootup_mclk_in10khz: u32,
6386 pub firmware_capability: u32,
6387 pub main_call_parser_entry: u32,
6388 pub bios_scratch_reg_startaddr: u32,
6389 pub bootup_vddc_mv: u16,
6390 pub bootup_vddci_mv: u16,
6391 pub bootup_mvddc_mv: u16,
6392 pub bootup_vddgfx_mv: u16,
6393 pub mem_module_id: u8,
6394 pub coolingsolution_id: u8,
6395 pub reserved1: [u8; 2usize],
6396 pub mc_baseaddr_high: u32,
6397 pub mc_baseaddr_low: u32,
6398 pub board_i2c_feature_id: u8,
6399 pub board_i2c_feature_gpio_id: u8,
6400 pub board_i2c_feature_slave_addr: u8,
6401 pub reserved3: u8,
6402 pub bootup_mvddq_mv: u16,
6403 pub bootup_mvpp_mv: u16,
6404 pub zfbstartaddrin16mb: u32,
6405 pub reserved2: [u32; 3usize],
6406}
6407#[repr(C, packed)]
6408#[derive(Debug, Copy, Clone)]
6409pub struct atom_firmware_info_v3_3 {
6410 pub table_header: atom_common_table_header,
6411 pub firmware_revision: u32,
6412 pub bootup_sclk_in10khz: u32,
6413 pub bootup_mclk_in10khz: u32,
6414 pub firmware_capability: u32,
6415 pub main_call_parser_entry: u32,
6416 pub bios_scratch_reg_startaddr: u32,
6417 pub bootup_vddc_mv: u16,
6418 pub bootup_vddci_mv: u16,
6419 pub bootup_mvddc_mv: u16,
6420 pub bootup_vddgfx_mv: u16,
6421 pub mem_module_id: u8,
6422 pub coolingsolution_id: u8,
6423 pub reserved1: [u8; 2usize],
6424 pub mc_baseaddr_high: u32,
6425 pub mc_baseaddr_low: u32,
6426 pub board_i2c_feature_id: u8,
6427 pub board_i2c_feature_gpio_id: u8,
6428 pub board_i2c_feature_slave_addr: u8,
6429 pub reserved3: u8,
6430 pub bootup_mvddq_mv: u16,
6431 pub bootup_mvpp_mv: u16,
6432 pub zfbstartaddrin16mb: u32,
6433 pub pplib_pptable_id: u32,
6434 pub reserved2: [u32; 2usize],
6435}
6436#[repr(C, packed)]
6437#[derive(Debug, Copy, Clone)]
6438pub struct atom_firmware_info_v3_4 {
6439 pub table_header: atom_common_table_header,
6440 pub firmware_revision: u32,
6441 pub bootup_sclk_in10khz: u32,
6442 pub bootup_mclk_in10khz: u32,
6443 pub firmware_capability: u32,
6444 pub main_call_parser_entry: u32,
6445 pub bios_scratch_reg_startaddr: u32,
6446 pub bootup_vddc_mv: u16,
6447 pub bootup_vddci_mv: u16,
6448 pub bootup_mvddc_mv: u16,
6449 pub bootup_vddgfx_mv: u16,
6450 pub mem_module_id: u8,
6451 pub coolingsolution_id: u8,
6452 pub reserved1: [u8; 2usize],
6453 pub mc_baseaddr_high: u32,
6454 pub mc_baseaddr_low: u32,
6455 pub board_i2c_feature_id: u8,
6456 pub board_i2c_feature_gpio_id: u8,
6457 pub board_i2c_feature_slave_addr: u8,
6458 pub ras_rom_i2c_slave_addr: u8,
6459 pub bootup_mvddq_mv: u16,
6460 pub bootup_mvpp_mv: u16,
6461 pub zfbstartaddrin16mb: u32,
6462 pub pplib_pptable_id: u32,
6463 pub mvdd_ratio: u32,
6464 pub hw_bootup_vddgfx_mv: u16,
6465 pub hw_bootup_vddc_mv: u16,
6466 pub hw_bootup_mvddc_mv: u16,
6467 pub hw_bootup_vddci_mv: u16,
6468 pub maco_pwrlimit_mw: u32,
6469 pub usb_pwrlimit_mw: u32,
6470 pub fw_reserved_size_in_kb: u32,
6471 pub pspbl_init_done_reg_addr: u32,
6472 pub pspbl_init_done_value: u32,
6473 pub pspbl_init_done_check_timeout: u32,
6474 pub reserved: [u32; 2usize],
6475}
6476#[repr(C, packed)]
6477#[derive(Debug, Copy, Clone)]
6478pub struct atom_firmware_info_v3_5 {
6479 pub table_header: atom_common_table_header,
6480 pub firmware_revision: u32,
6481 pub bootup_clk_reserved: [u32; 2usize],
6482 pub firmware_capability: u32,
6483 pub fw_protect_region_size_in_kb: u32,
6484 pub bios_scratch_reg_startaddr: u32,
6485 pub bootup_voltage_reserved: [u32; 2usize],
6486 pub mem_module_id: u8,
6487 pub coolingsolution_id: u8,
6488 pub hw_blt_mode: u8,
6489 pub reserved1: u8,
6490 pub mc_baseaddr_high: u32,
6491 pub mc_baseaddr_low: u32,
6492 pub board_i2c_feature_id: u8,
6493 pub board_i2c_feature_gpio_id: u8,
6494 pub board_i2c_feature_slave_addr: u8,
6495 pub ras_rom_i2c_slave_addr: u8,
6496 pub bootup_voltage_reserved1: u32,
6497 pub zfb_reserved: u32,
6498 pub pplib_pptable_id: u32,
6499 pub hw_voltage_reserved: [u32; 3usize],
6500 pub maco_pwrlimit_mw: u32,
6501 pub usb_pwrlimit_mw: u32,
6502 pub fw_reserved_size_in_kb: u32,
6503 pub pspbl_init_reserved: [u32; 3usize],
6504 pub spi_rom_size: u32,
6505 pub support_dev_in_objinfo: u16,
6506 pub disp_phy_tunning_size: u16,
6507 pub reserved: [u32; 16usize],
6508}
6509#[repr(C, packed)]
6510#[derive(Debug, Copy, Clone)]
6511pub struct lcd_info_v2_1 {
6512 pub table_header: atom_common_table_header,
6513 pub lcd_timing: atom_dtd_format,
6514 pub backlight_pwm: u16,
6515 pub special_handle_cap: u16,
6516 pub panel_misc: u16,
6517 pub lvds_max_slink_pclk: u16,
6518 pub lvds_ss_percentage: u16,
6519 pub lvds_ss_rate_10hz: u16,
6520 pub pwr_on_digon_to_de: u8,
6521 pub pwr_on_de_to_vary_bl: u8,
6522 pub pwr_down_vary_bloff_to_de: u8,
6523 pub pwr_down_de_to_digoff: u8,
6524 pub pwr_off_delay: u8,
6525 pub pwr_on_vary_bl_to_blon: u8,
6526 pub pwr_down_bloff_to_vary_bloff: u8,
6527 pub panel_bpc: u8,
6528 pub dpcd_edp_config_cap: u8,
6529 pub dpcd_max_link_rate: u8,
6530 pub dpcd_max_lane_count: u8,
6531 pub dpcd_max_downspread: u8,
6532 pub min_allowed_bl_level: u8,
6533 pub max_allowed_bl_level: u8,
6534 pub bootup_bl_level: u8,
6535 pub dplvdsrxid: u8,
6536 pub reserved1: [u32; 8usize],
6537}
6538pub const atom_lcd_info_panel_misc_ATOM_PANEL_MISC_FPDI: atom_lcd_info_panel_misc = 2;
6539pub type atom_lcd_info_panel_misc = ::core::ffi::c_uint;
6540pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_RX_DISABLE: atom_lcd_info_dptolvds_rx_id = 0;
6541pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_COMMON_ID: atom_lcd_info_dptolvds_rx_id = 1;
6542pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_REALTEK_ID: atom_lcd_info_dptolvds_rx_id = 2;
6543pub type atom_lcd_info_dptolvds_rx_id = ::core::ffi::c_uint;
6544#[repr(C, packed)]
6545#[derive(Debug, Copy, Clone)]
6546pub struct atom_gpio_pin_assignment {
6547 pub data_a_reg_index: u32,
6548 pub gpio_bitshift: u8,
6549 pub gpio_mask_bitshift: u8,
6550 pub gpio_id: u8,
6551 pub reserved: u8,
6552}
6553pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_LANE_MUX: atom_gpio_pin_assignment_gpio_id = 15;
6554pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_ENGINE_ID_MASK: atom_gpio_pin_assignment_gpio_id =
6555 112;
6556pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_CAP: atom_gpio_pin_assignment_gpio_id = 128;
6557pub const atom_gpio_pin_assignment_gpio_id_PCIE_VDDC_CONTROL_GPIO_PINID:
6558 atom_gpio_pin_assignment_gpio_id = 56;
6559pub const atom_gpio_pin_assignment_gpio_id_PP_AC_DC_SWITCH_GPIO_PINID:
6560 atom_gpio_pin_assignment_gpio_id = 60;
6561pub const atom_gpio_pin_assignment_gpio_id_VDDC_VRHOT_GPIO_PINID: atom_gpio_pin_assignment_gpio_id =
6562 61;
6563pub const atom_gpio_pin_assignment_gpio_id_VDDC_PCC_GPIO_PINID: atom_gpio_pin_assignment_gpio_id =
6564 62;
6565pub const atom_gpio_pin_assignment_gpio_id_EFUSE_CUT_ENABLE_GPIO_PINID:
6566 atom_gpio_pin_assignment_gpio_id = 63;
6567pub const atom_gpio_pin_assignment_gpio_id_DRAM_SELF_REFRESH_GPIO_PINID:
6568 atom_gpio_pin_assignment_gpio_id = 64;
6569pub const atom_gpio_pin_assignment_gpio_id_THERMAL_INT_OUTPUT_GPIO_PINID:
6570 atom_gpio_pin_assignment_gpio_id = 65;
6571pub type atom_gpio_pin_assignment_gpio_id = ::core::ffi::c_uint;
6572#[repr(C)]
6573#[derive(Debug, Copy, Clone)]
6574pub struct atom_gpio_pin_lut_v2_1 {
6575 pub table_header: atom_common_table_header,
6576 pub gpio_pin: [atom_gpio_pin_assignment; 8usize],
6577}
6578#[repr(C, packed)]
6579#[derive(Debug, Copy, Clone)]
6580pub struct vram_usagebyfirmware_v2_1 {
6581 pub table_header: atom_common_table_header,
6582 pub start_address_in_kb: u32,
6583 pub used_by_firmware_in_kb: u16,
6584 pub used_by_driver_in_kb: u16,
6585}
6586#[repr(C, packed)]
6587#[derive(Debug, Copy, Clone)]
6588pub struct vram_usagebyfirmware_v2_2 {
6589 pub table_header: atom_common_table_header,
6590 pub fw_region_start_address_in_kb: u32,
6591 pub used_by_firmware_in_kb: u16,
6592 pub reserved: u16,
6593 pub driver_region0_start_address_in_kb: u32,
6594 pub used_by_driver_region0_in_kb: u32,
6595 pub reserved32: [u32; 7usize],
6596}
6597pub const atom_object_record_type_id_ATOM_I2C_RECORD_TYPE: atom_object_record_type_id = 1;
6598pub const atom_object_record_type_id_ATOM_HPD_INT_RECORD_TYPE: atom_object_record_type_id = 2;
6599pub const atom_object_record_type_id_ATOM_CONNECTOR_CAP_RECORD_TYPE: atom_object_record_type_id = 3;
6600pub const atom_object_record_type_id_ATOM_CONNECTOR_SPEED_UPTO: atom_object_record_type_id = 4;
6601pub const atom_object_record_type_id_ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE: atom_object_record_type_id =
6602 9;
6603pub const atom_object_record_type_id_ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE:
6604 atom_object_record_type_id = 16;
6605pub const atom_object_record_type_id_ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE:
6606 atom_object_record_type_id = 17;
6607pub const atom_object_record_type_id_ATOM_ENCODER_CAP_RECORD_TYPE: atom_object_record_type_id = 20;
6608pub const atom_object_record_type_id_ATOM_BRACKET_LAYOUT_RECORD_TYPE: atom_object_record_type_id =
6609 21;
6610pub const atom_object_record_type_id_ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE:
6611 atom_object_record_type_id = 22;
6612pub const atom_object_record_type_id_ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE:
6613 atom_object_record_type_id = 23;
6614pub const atom_object_record_type_id_ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE:
6615 atom_object_record_type_id = 25;
6616pub const atom_object_record_type_id_ATOM_RECORD_END_TYPE: atom_object_record_type_id = 255;
6617pub type atom_object_record_type_id = ::core::ffi::c_uint;
6618#[repr(C)]
6619#[derive(Debug, Copy, Clone)]
6620pub struct atom_common_record_header {
6621 pub record_type: u8,
6622 pub record_size: u8,
6623}
6624#[repr(C)]
6625#[derive(Debug, Copy, Clone)]
6626pub struct atom_i2c_record {
6627 pub record_header: atom_common_record_header,
6628 pub i2c_id: u8,
6629 pub i2c_slave_addr: u8,
6630}
6631#[repr(C)]
6632#[derive(Debug, Copy, Clone)]
6633pub struct atom_hpd_int_record {
6634 pub record_header: atom_common_record_header,
6635 pub pin_id: u8,
6636 pub plugin_pin_state: u8,
6637}
6638#[repr(C, packed)]
6639#[derive(Debug, Copy, Clone)]
6640pub struct atom_connector_caps_record {
6641 pub record_header: atom_common_record_header,
6642 pub connector_caps: u16,
6643}
6644#[repr(C, packed)]
6645#[derive(Debug, Copy, Clone)]
6646pub struct atom_connector_speed_record {
6647 pub record_header: atom_common_record_header,
6648 pub connector_max_speed: u32,
6649 pub reserved: u16,
6650}
6651pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR2: atom_encoder_caps_def = 1;
6652pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_MST_EN: atom_encoder_caps_def = 1;
6653pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR2_EN: atom_encoder_caps_def = 2;
6654pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN: atom_encoder_caps_def = 4;
6655pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR3_EN: atom_encoder_caps_def = 8;
6656pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_DP2: atom_encoder_caps_def = 16;
6657pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR10_EN: atom_encoder_caps_def = 32;
6658pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN: atom_encoder_caps_def = 64;
6659pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR20_EN: atom_encoder_caps_def = 128;
6660pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_USB_C_TYPE: atom_encoder_caps_def = 256;
6661pub type atom_encoder_caps_def = ::core::ffi::c_uint;
6662#[repr(C, packed)]
6663#[derive(Debug, Copy, Clone)]
6664pub struct atom_encoder_caps_record {
6665 pub record_header: atom_common_record_header,
6666 pub encodercaps: u32,
6667}
6668pub const atom_connector_caps_def_ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY: atom_connector_caps_def = 1;
6669pub const atom_connector_caps_def_ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL: atom_connector_caps_def =
6670 2;
6671pub type atom_connector_caps_def = ::core::ffi::c_uint;
6672#[repr(C, packed)]
6673#[derive(Debug, Copy, Clone)]
6674pub struct atom_disp_connector_caps_record {
6675 pub record_header: atom_common_record_header,
6676 pub connectcaps: u32,
6677}
6678#[repr(C)]
6679#[derive(Debug, Copy, Clone)]
6680pub struct atom_gpio_pin_control_pair {
6681 pub gpio_id: u8,
6682 pub gpio_pinstate: u8,
6683}
6684#[repr(C)]
6685#[derive(Debug, Copy, Clone)]
6686pub struct atom_object_gpio_cntl_record {
6687 pub record_header: atom_common_record_header,
6688 pub flag: u8,
6689 pub number_of_pins: u8,
6690 pub gpio: [atom_gpio_pin_control_pair; 1usize],
6691}
6692pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_INPUT:
6693 atom_gpio_pin_control_pinstate_def = 0;
6694pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_OUTPUT:
6695 atom_gpio_pin_control_pinstate_def = 16;
6696pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_HW_CONTROL:
6697 atom_gpio_pin_control_pinstate_def = 32;
6698pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_OUTPUT_STATE_MASK:
6699 atom_gpio_pin_control_pinstate_def = 1;
6700pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_OUTPUT_STATE_SHIFT:
6701 atom_gpio_pin_control_pinstate_def = 0;
6702pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_STATE_ACTIVE_LOW:
6703 atom_gpio_pin_control_pinstate_def = 0;
6704pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_STATE_ACTIVE_HIGH:
6705 atom_gpio_pin_control_pinstate_def = 1;
6706pub type atom_gpio_pin_control_pinstate_def = ::core::ffi::c_uint;
6707pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_REFCLK:
6708 atom_glsync_record_gpio_index_def = 0;
6709pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_HSYNC:
6710 atom_glsync_record_gpio_index_def = 1;
6711pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_VSYNC:
6712 atom_glsync_record_gpio_index_def = 2;
6713pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ:
6714 atom_glsync_record_gpio_index_def = 3;
6715pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT:
6716 atom_glsync_record_gpio_index_def = 4;
6717pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_INTERRUPT:
6718 atom_glsync_record_gpio_index_def = 5;
6719pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_V_RESET:
6720 atom_glsync_record_gpio_index_def = 6;
6721pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL:
6722 atom_glsync_record_gpio_index_def = 7;
6723pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL:
6724 atom_glsync_record_gpio_index_def = 8;
6725pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_MAX:
6726 atom_glsync_record_gpio_index_def = 9;
6727pub type atom_glsync_record_gpio_index_def = ::core::ffi::c_uint;
6728#[repr(C)]
6729#[derive(Debug, Copy, Clone)]
6730pub struct atom_connector_hpdpin_lut_record {
6731 pub record_header: atom_common_record_header,
6732 pub hpd_pin_map: [u8; 8usize],
6733}
6734#[repr(C)]
6735#[derive(Debug, Copy, Clone)]
6736pub struct atom_connector_auxddc_lut_record {
6737 pub record_header: atom_common_record_header,
6738 pub aux_ddc_map: [u8; 8usize],
6739}
6740#[repr(C)]
6741#[derive(Debug, Copy, Clone)]
6742pub struct atom_connector_forced_tmds_cap_record {
6743 pub record_header: atom_common_record_header,
6744 pub maxtmdsclkrate_in2_5mhz: u8,
6745 pub reserved: u8,
6746}
6747#[repr(C, packed)]
6748#[derive(Debug, Copy, Clone)]
6749pub struct atom_connector_layout_info {
6750 pub connectorobjid: u16,
6751 pub connector_type: u8,
6752 pub position: u8,
6753}
6754pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_DVI_D:
6755 atom_connector_layout_info_connector_type_def = 1;
6756pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_HDMI:
6757 atom_connector_layout_info_connector_type_def = 4;
6758pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_DISPLAY_PORT:
6759 atom_connector_layout_info_connector_type_def = 5;
6760pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_MINI_DISPLAY_PORT:
6761 atom_connector_layout_info_connector_type_def = 6;
6762pub type atom_connector_layout_info_connector_type_def = ::core::ffi::c_uint;
6763#[repr(C)]
6764#[derive(Debug, Copy, Clone)]
6765pub struct atom_bracket_layout_record {
6766 pub record_header: atom_common_record_header,
6767 pub bracketlen: u8,
6768 pub bracketwidth: u8,
6769 pub conn_num: u8,
6770 pub reserved: u8,
6771 pub conn_info: [atom_connector_layout_info; 1usize],
6772}
6773#[repr(C)]
6774#[derive(Debug, Copy, Clone)]
6775pub struct atom_bracket_layout_record_v2 {
6776 pub record_header: atom_common_record_header,
6777 pub bracketlen: u8,
6778 pub bracketwidth: u8,
6779 pub conn_num: u8,
6780 pub mini_type: u8,
6781 pub reserved1: u8,
6782 pub reserved2: u8,
6783}
6784pub const atom_connector_layout_info_mini_type_def_MINI_TYPE_NORMAL:
6785 atom_connector_layout_info_mini_type_def = 0;
6786pub const atom_connector_layout_info_mini_type_def_MINI_TYPE_MINI:
6787 atom_connector_layout_info_mini_type_def = 1;
6788pub type atom_connector_layout_info_mini_type_def = ::core::ffi::c_uint;
6789pub const atom_display_device_tag_def_ATOM_DISPLAY_LCD1_SUPPORT: atom_display_device_tag_def = 2;
6790pub const atom_display_device_tag_def_ATOM_DISPLAY_LCD2_SUPPORT: atom_display_device_tag_def = 32;
6791pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP1_SUPPORT: atom_display_device_tag_def = 8;
6792pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP2_SUPPORT: atom_display_device_tag_def = 128;
6793pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP3_SUPPORT: atom_display_device_tag_def = 512;
6794pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP4_SUPPORT: atom_display_device_tag_def = 1024;
6795pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP5_SUPPORT: atom_display_device_tag_def = 2048;
6796pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP6_SUPPORT: atom_display_device_tag_def = 64;
6797pub const atom_display_device_tag_def_ATOM_DISPLAY_DFPx_SUPPORT: atom_display_device_tag_def = 3784;
6798pub type atom_display_device_tag_def = ::core::ffi::c_uint;
6799#[repr(C, packed)]
6800#[derive(Debug, Copy, Clone)]
6801pub struct atom_display_object_path_v2 {
6802 pub display_objid: u16,
6803 pub disp_recordoffset: u16,
6804 pub encoderobjid: u16,
6805 pub extencoderobjid: u16,
6806 pub encoder_recordoffset: u16,
6807 pub extencoder_recordoffset: u16,
6808 pub device_tag: u16,
6809 pub priority_id: u8,
6810 pub reserved: u8,
6811}
6812#[repr(C, packed)]
6813#[derive(Debug, Copy, Clone)]
6814pub struct atom_display_object_path_v3 {
6815 pub display_objid: u16,
6816 pub disp_recordoffset: u16,
6817 pub encoderobjid: u16,
6818 pub reserved1: u16,
6819 pub reserved2: u16,
6820 pub reserved3: u16,
6821 pub device_tag: u16,
6822 pub reserved4: u16,
6823}
6824#[repr(C, packed)]
6825#[derive(Debug, Copy, Clone)]
6826pub struct display_object_info_table_v1_4 {
6827 pub table_header: atom_common_table_header,
6828 pub supporteddevices: u16,
6829 pub number_of_path: u8,
6830 pub reserved: u8,
6831 pub display_path: [atom_display_object_path_v2; 8usize],
6832}
6833#[repr(C, packed)]
6834#[derive(Debug, Copy, Clone)]
6835pub struct display_object_info_table_v1_5 {
6836 pub table_header: atom_common_table_header,
6837 pub supporteddevices: u16,
6838 pub number_of_path: u8,
6839 pub reserved: u8,
6840 pub display_path: [atom_display_object_path_v3; 8usize],
6841}
6842#[repr(C, packed)]
6843#[derive(Debug, Copy, Clone)]
6844pub struct atom_display_controller_info_v4_1 {
6845 pub table_header: atom_common_table_header,
6846 pub display_caps: u32,
6847 pub bootup_dispclk_10khz: u32,
6848 pub dce_refclk_10khz: u16,
6849 pub i2c_engine_refclk_10khz: u16,
6850 pub dvi_ss_percentage: u16,
6851 pub dvi_ss_rate_10hz: u16,
6852 pub hdmi_ss_percentage: u16,
6853 pub hdmi_ss_rate_10hz: u16,
6854 pub dp_ss_percentage: u16,
6855 pub dp_ss_rate_10hz: u16,
6856 pub dvi_ss_mode: u8,
6857 pub hdmi_ss_mode: u8,
6858 pub dp_ss_mode: u8,
6859 pub ss_reserved: u8,
6860 pub hardcode_mode_num: u8,
6861 pub reserved1: [u8; 3usize],
6862 pub dpphy_refclk_10khz: u16,
6863 pub reserved2: u16,
6864 pub dceip_min_ver: u8,
6865 pub dceip_max_ver: u8,
6866 pub max_disp_pipe_num: u8,
6867 pub max_vbios_active_disp_pipe_num: u8,
6868 pub max_ppll_num: u8,
6869 pub max_disp_phy_num: u8,
6870 pub max_aux_pairs: u8,
6871 pub remotedisplayconfig: u8,
6872 pub reserved3: [u8; 8usize],
6873}
6874#[repr(C, packed)]
6875#[derive(Debug, Copy, Clone)]
6876pub struct atom_display_controller_info_v4_2 {
6877 pub table_header: atom_common_table_header,
6878 pub display_caps: u32,
6879 pub bootup_dispclk_10khz: u32,
6880 pub dce_refclk_10khz: u16,
6881 pub i2c_engine_refclk_10khz: u16,
6882 pub dvi_ss_percentage: u16,
6883 pub dvi_ss_rate_10hz: u16,
6884 pub hdmi_ss_percentage: u16,
6885 pub hdmi_ss_rate_10hz: u16,
6886 pub dp_ss_percentage: u16,
6887 pub dp_ss_rate_10hz: u16,
6888 pub dvi_ss_mode: u8,
6889 pub hdmi_ss_mode: u8,
6890 pub dp_ss_mode: u8,
6891 pub ss_reserved: u8,
6892 pub dfp_hardcode_mode_num: u8,
6893 pub dfp_hardcode_refreshrate: u8,
6894 pub vga_hardcode_mode_num: u8,
6895 pub vga_hardcode_refreshrate: u8,
6896 pub dpphy_refclk_10khz: u16,
6897 pub reserved2: u16,
6898 pub dcnip_min_ver: u8,
6899 pub dcnip_max_ver: u8,
6900 pub max_disp_pipe_num: u8,
6901 pub max_vbios_active_disp_pipe_num: u8,
6902 pub max_ppll_num: u8,
6903 pub max_disp_phy_num: u8,
6904 pub max_aux_pairs: u8,
6905 pub remotedisplayconfig: u8,
6906 pub reserved3: [u8; 8usize],
6907}
6908#[repr(C, packed)]
6909#[derive(Debug, Copy, Clone)]
6910pub struct atom_display_controller_info_v4_3 {
6911 pub table_header: atom_common_table_header,
6912 pub display_caps: u32,
6913 pub bootup_dispclk_10khz: u32,
6914 pub dce_refclk_10khz: u16,
6915 pub i2c_engine_refclk_10khz: u16,
6916 pub dvi_ss_percentage: u16,
6917 pub dvi_ss_rate_10hz: u16,
6918 pub hdmi_ss_percentage: u16,
6919 pub hdmi_ss_rate_10hz: u16,
6920 pub dp_ss_percentage: u16,
6921 pub dp_ss_rate_10hz: u16,
6922 pub dvi_ss_mode: u8,
6923 pub hdmi_ss_mode: u8,
6924 pub dp_ss_mode: u8,
6925 pub ss_reserved: u8,
6926 pub dfp_hardcode_mode_num: u8,
6927 pub dfp_hardcode_refreshrate: u8,
6928 pub vga_hardcode_mode_num: u8,
6929 pub vga_hardcode_refreshrate: u8,
6930 pub dpphy_refclk_10khz: u16,
6931 pub reserved2: u16,
6932 pub dcnip_min_ver: u8,
6933 pub dcnip_max_ver: u8,
6934 pub max_disp_pipe_num: u8,
6935 pub max_vbios_active_disp_pipe_num: u8,
6936 pub max_ppll_num: u8,
6937 pub max_disp_phy_num: u8,
6938 pub max_aux_pairs: u8,
6939 pub remotedisplayconfig: u8,
6940 pub reserved3: [u8; 8usize],
6941}
6942#[repr(C, packed)]
6943#[derive(Debug, Copy, Clone)]
6944pub struct atom_display_controller_info_v4_4 {
6945 pub table_header: atom_common_table_header,
6946 pub display_caps: u32,
6947 pub bootup_dispclk_10khz: u32,
6948 pub dce_refclk_10khz: u16,
6949 pub i2c_engine_refclk_10khz: u16,
6950 pub dvi_ss_percentage: u16,
6951 pub dvi_ss_rate_10hz: u16,
6952 pub hdmi_ss_percentage: u16,
6953 pub hdmi_ss_rate_10hz: u16,
6954 pub dp_ss_percentage: u16,
6955 pub dp_ss_rate_10hz: u16,
6956 pub dvi_ss_mode: u8,
6957 pub hdmi_ss_mode: u8,
6958 pub dp_ss_mode: u8,
6959 pub ss_reserved: u8,
6960 pub dfp_hardcode_mode_num: u8,
6961 pub dfp_hardcode_refreshrate: u8,
6962 pub vga_hardcode_mode_num: u8,
6963 pub vga_hardcode_refreshrate: u8,
6964 pub dpphy_refclk_10khz: u16,
6965 pub hw_chip_id: u16,
6966 pub dcnip_min_ver: u8,
6967 pub dcnip_max_ver: u8,
6968 pub max_disp_pipe_num: u8,
6969 pub max_vbios_active_disp_pipum: u8,
6970 pub max_ppll_num: u8,
6971 pub max_disp_phy_num: u8,
6972 pub max_aux_pairs: u8,
6973 pub remotedisplayconfig: u8,
6974 pub dispclk_pll_vco_freq: u32,
6975 pub dp_ref_clk_freq: u32,
6976 pub max_mclk_chg_lat: u32,
6977 pub max_sr_exit_lat: u32,
6978 pub max_sr_enter_exit_lat: u32,
6979 pub dc_golden_table_offset: u16,
6980 pub dc_golden_table_ver: u16,
6981 pub reserved3: [u32; 3usize],
6982}
6983#[repr(C, packed)]
6984#[derive(Debug, Copy, Clone)]
6985pub struct atom_dc_golden_table_v1 {
6986 pub aux_dphy_rx_control0_val: u32,
6987 pub aux_dphy_tx_control_val: u32,
6988 pub aux_dphy_rx_control1_val: u32,
6989 pub dc_gpio_aux_ctrl_0_val: u32,
6990 pub dc_gpio_aux_ctrl_1_val: u32,
6991 pub dc_gpio_aux_ctrl_2_val: u32,
6992 pub dc_gpio_aux_ctrl_3_val: u32,
6993 pub dc_gpio_aux_ctrl_4_val: u32,
6994 pub dc_gpio_aux_ctrl_5_val: u32,
6995 pub reserved: [u32; 23usize],
6996}
6997pub const dce_info_caps_def_DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED: dce_info_caps_def = 2;
6998pub const dce_info_caps_def_DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2: dce_info_caps_def = 4;
6999pub const dce_info_caps_def_DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING: dce_info_caps_def = 8;
7000pub const dce_info_caps_def_DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: dce_info_caps_def = 32;
7001pub const dce_info_caps_def_DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: dce_info_caps_def = 64;
7002pub type dce_info_caps_def = ::core::ffi::c_uint;
7003#[repr(C, packed)]
7004#[derive(Debug, Copy, Clone)]
7005pub struct atom_display_controller_info_v4_5 {
7006 pub table_header: atom_common_table_header,
7007 pub display_caps: u32,
7008 pub bootup_dispclk_10khz: u32,
7009 pub dce_refclk_10khz: u16,
7010 pub i2c_engine_refclk_10khz: u16,
7011 pub dvi_ss_percentage: u16,
7012 pub dvi_ss_rate_10hz: u16,
7013 pub hdmi_ss_percentage: u16,
7014 pub hdmi_ss_rate_10hz: u16,
7015 pub dp_ss_percentage: u16,
7016 pub dp_ss_rate_10hz: u16,
7017 pub dvi_ss_mode: u8,
7018 pub hdmi_ss_mode: u8,
7019 pub dp_ss_mode: u8,
7020 pub ss_reserved: u8,
7021 pub dfp_hardcode_mode_num: u8,
7022 pub dfp_hardcode_refreshrate: u8,
7023 pub vga_hardcode_mode_num: u8,
7024 pub vga_hardcode_refreshrate: u8,
7025 pub dpphy_refclk_10khz: u16,
7026 pub hw_chip_id: u16,
7027 pub dcnip_min_ver: u8,
7028 pub dcnip_max_ver: u8,
7029 pub max_disp_pipe_num: u8,
7030 pub max_vbios_active_disp_pipe_num: u8,
7031 pub max_ppll_num: u8,
7032 pub max_disp_phy_num: u8,
7033 pub max_aux_pairs: u8,
7034 pub remotedisplayconfig: u8,
7035 pub dispclk_pll_vco_freq: u32,
7036 pub dp_ref_clk_freq: u32,
7037 pub max_mclk_chg_lat: u32,
7038 pub max_sr_exit_lat: u32,
7039 pub max_sr_enter_exit_lat: u32,
7040 pub dc_golden_table_offset: u16,
7041 pub dc_golden_table_ver: u16,
7042 pub aux_dphy_rx_control0_val: u32,
7043 pub aux_dphy_tx_control_val: u32,
7044 pub aux_dphy_rx_control1_val: u32,
7045 pub dc_gpio_aux_ctrl_0_val: u32,
7046 pub dc_gpio_aux_ctrl_1_val: u32,
7047 pub dc_gpio_aux_ctrl_2_val: u32,
7048 pub dc_gpio_aux_ctrl_3_val: u32,
7049 pub dc_gpio_aux_ctrl_4_val: u32,
7050 pub dc_gpio_aux_ctrl_5_val: u32,
7051 pub reserved: [u32; 26usize],
7052}
7053#[repr(C, packed)]
7054#[derive(Debug, Copy, Clone)]
7055pub struct atom_ext_display_path {
7056 pub device_tag: u16,
7057 pub device_acpi_enum: u16,
7058 pub connectorobjid: u16,
7059 pub auxddclut_index: u8,
7060 pub hpdlut_index: u8,
7061 pub ext_encoder_objid: u16,
7062 pub channelmapping: u8,
7063 pub chpninvert: u8,
7064 pub caps: u16,
7065 pub reserved: u16,
7066}
7067pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE: ext_display_path_cap_def =
7068 1;
7069pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN: ext_display_path_cap_def =
7070 2;
7071pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK: ext_display_path_cap_def =
7072 124;
7073pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204:
7074 ext_display_path_cap_def = 4;
7075pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT:
7076 ext_display_path_cap_def = 8;
7077pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175:
7078 ext_display_path_cap_def = 12;
7079pub type ext_display_path_cap_def = ::core::ffi::c_uint;
7080#[repr(C)]
7081#[derive(Debug, Copy, Clone)]
7082pub struct atom_external_display_connection_info {
7083 pub table_header: atom_common_table_header,
7084 pub guid: [u8; 16usize],
7085 pub path: [atom_ext_display_path; 7usize],
7086 pub checksum: u8,
7087 pub stereopinid: u8,
7088 pub remotedisplayconfig: u8,
7089 pub edptolvdsrxid: u8,
7090 pub fixdpvoltageswing: u8,
7091 pub reserved: [u8; 3usize],
7092}
7093#[repr(C, packed)]
7094#[derive(Debug, Copy, Clone)]
7095pub struct atom_camera_dphy_timing_param {
7096 pub profile_id: u8,
7097 pub param: u32,
7098}
7099#[repr(C, packed)]
7100#[derive(Debug, Copy, Clone)]
7101pub struct atom_camera_dphy_elec_param {
7102 pub param: [u16; 3usize],
7103}
7104#[repr(C)]
7105#[derive(Debug, Copy, Clone)]
7106pub struct atom_camera_module_info {
7107 pub module_id: u8,
7108 pub module_name: [u8; 8usize],
7109 pub timingparam: [atom_camera_dphy_timing_param; 6usize],
7110}
7111#[repr(C)]
7112#[derive(Debug, Copy, Clone)]
7113pub struct atom_camera_flashlight_info {
7114 pub flashlight_id: u8,
7115 pub name: [u8; 8usize],
7116}
7117#[repr(C, packed)]
7118#[derive(Debug, Copy, Clone)]
7119pub struct atom_camera_data {
7120 pub versionCode: u32,
7121 pub cameraInfo: [atom_camera_module_info; 3usize],
7122 pub flashInfo: atom_camera_flashlight_info,
7123 pub dphy_param: atom_camera_dphy_elec_param,
7124 pub crc_val: u32,
7125}
7126#[repr(C, packed)]
7127#[derive(Debug, Copy, Clone)]
7128pub struct atom_14nm_dpphy_dvihdmi_tuningset {
7129 pub max_symclk_in10khz: u32,
7130 pub encoder_mode: u8,
7131 pub phy_sel: u8,
7132 pub margindeemph: u16,
7133 pub deemph_6db_4: u8,
7134 pub boostadj: u8,
7135 pub tx_driver_fifty_ohms: u8,
7136 pub deemph_sel: u8,
7137}
7138#[repr(C, packed)]
7139#[derive(Debug, Copy, Clone)]
7140pub struct atom_14nm_dpphy_dp_setting {
7141 pub dp_vs_pemph_level: u8,
7142 pub margindeemph: u16,
7143 pub deemph_6db_4: u8,
7144 pub boostadj: u8,
7145}
7146#[repr(C, packed)]
7147#[derive(Debug, Copy, Clone)]
7148pub struct atom_14nm_dpphy_dp_tuningset {
7149 pub phy_sel: u8,
7150 pub version: u8,
7151 pub table_size: u16,
7152 pub reserved: u16,
7153 pub dptuning: [atom_14nm_dpphy_dp_setting; 10usize],
7154}
7155#[repr(C, packed)]
7156#[derive(Debug, Copy, Clone)]
7157pub struct atom_14nm_dig_transmitter_info_header_v4_0 {
7158 pub table_header: atom_common_table_header,
7159 pub pcie_phy_tmds_hdmi_macro_settings_offset: u16,
7160 pub uniphy_vs_emph_lookup_table_offset: u16,
7161 pub uniphy_xbar_settings_table_offset: u16,
7162}
7163#[repr(C, packed)]
7164#[derive(Debug, Copy, Clone)]
7165pub struct atom_14nm_combphy_tmds_vs_set {
7166 pub sym_clk: u8,
7167 pub dig_mode: u8,
7168 pub phy_sel: u8,
7169 pub common_mar_deemph_nom__margin_deemph_val: u16,
7170 pub common_seldeemph60__deemph_6db_4_val: u8,
7171 pub cmd_bus_global_for_tx_lane0__boostadj_val: u8,
7172 pub common_zcalcode_ctrl__tx_driver_fifty_ohms_val: u8,
7173 pub margin_deemph_lane0__deemph_sel_val: u8,
7174}
7175#[repr(C, packed)]
7176#[derive(Debug, Copy, Clone)]
7177pub struct atom_DCN_dpphy_dvihdmi_tuningset {
7178 pub max_symclk_in10khz: u32,
7179 pub encoder_mode: u8,
7180 pub phy_sel: u8,
7181 pub tx_eq_main: u8,
7182 pub tx_eq_pre: u8,
7183 pub tx_eq_post: u8,
7184 pub reserved1: u8,
7185 pub tx_vboost_lvl: u8,
7186 pub reserved2: u8,
7187}
7188#[repr(C)]
7189#[derive(Debug, Copy, Clone)]
7190pub struct atom_DCN_dpphy_dp_setting {
7191 pub dp_vs_pemph_level: u8,
7192 pub tx_eq_main: u8,
7193 pub tx_eq_pre: u8,
7194 pub tx_eq_post: u8,
7195 pub tx_vboost_lvl: u8,
7196}
7197#[repr(C, packed)]
7198#[derive(Debug, Copy, Clone)]
7199pub struct atom_DCN_dpphy_dp_tuningset {
7200 pub phy_sel: u8,
7201 pub version: u8,
7202 pub table_size: u16,
7203 pub reserved: u16,
7204 pub dptunings: [atom_DCN_dpphy_dp_setting; 10usize],
7205}
7206#[repr(C)]
7207#[derive(Debug, Copy, Clone)]
7208pub struct atom_i2c_reg_info {
7209 pub ucI2cRegIndex: u8,
7210 pub ucI2cRegVal: u8,
7211}
7212#[repr(C)]
7213#[derive(Debug, Copy, Clone)]
7214pub struct atom_hdmi_retimer_redriver_set {
7215 pub HdmiSlvAddr: u8,
7216 pub HdmiRegNum: u8,
7217 pub Hdmi6GRegNum: u8,
7218 pub HdmiRegSetting: [atom_i2c_reg_info; 9usize],
7219 pub Hdmi6GhzRegSetting: [atom_i2c_reg_info; 3usize],
7220}
7221#[repr(C, packed)]
7222#[derive(Debug, Copy, Clone)]
7223pub struct atom_integrated_system_info_v1_11 {
7224 pub table_header: atom_common_table_header,
7225 pub vbios_misc: u32,
7226 pub gpucapinfo: u32,
7227 pub system_config: u32,
7228 pub cpucapinfo: u32,
7229 pub gpuclk_ss_percentage: u16,
7230 pub gpuclk_ss_type: u16,
7231 pub lvds_ss_percentage: u16,
7232 pub lvds_ss_rate_10hz: u16,
7233 pub hdmi_ss_percentage: u16,
7234 pub hdmi_ss_rate_10hz: u16,
7235 pub dvi_ss_percentage: u16,
7236 pub dvi_ss_rate_10hz: u16,
7237 pub dpphy_override: u16,
7238 pub lvds_misc: u16,
7239 pub backlight_pwm_hz: u16,
7240 pub memorytype: u8,
7241 pub umachannelnumber: u8,
7242 pub pwr_on_digon_to_de: u8,
7243 pub pwr_on_de_to_vary_bl: u8,
7244 pub pwr_down_vary_bloff_to_de: u8,
7245 pub pwr_down_de_to_digoff: u8,
7246 pub pwr_off_delay: u8,
7247 pub pwr_on_vary_bl_to_blon: u8,
7248 pub pwr_down_bloff_to_vary_bloff: u8,
7249 pub min_allowed_bl_level: u8,
7250 pub htc_hyst_limit: u8,
7251 pub htc_tmp_limit: u8,
7252 pub reserved1: u8,
7253 pub reserved2: u8,
7254 pub extdispconninfo: atom_external_display_connection_info,
7255 pub dvi_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
7256 pub hdmi_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
7257 pub hdmi6g_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
7258 pub dp_tuningset: atom_14nm_dpphy_dp_tuningset,
7259 pub dp_hbr3_tuningset: atom_14nm_dpphy_dp_tuningset,
7260 pub camera_info: atom_camera_data,
7261 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
7262 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
7263 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
7264 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
7265 pub dp_hbr_tuningset: atom_14nm_dpphy_dp_tuningset,
7266 pub dp_hbr2_tuningset: atom_14nm_dpphy_dp_tuningset,
7267 pub edp_tuningset: atom_14nm_dpphy_dp_tuningset,
7268 pub reserved: [u32; 66usize],
7269}
7270#[repr(C, packed)]
7271#[derive(Debug, Copy, Clone)]
7272pub struct atom_integrated_system_info_v1_12 {
7273 pub table_header: atom_common_table_header,
7274 pub vbios_misc: u32,
7275 pub gpucapinfo: u32,
7276 pub system_config: u32,
7277 pub cpucapinfo: u32,
7278 pub gpuclk_ss_percentage: u16,
7279 pub gpuclk_ss_type: u16,
7280 pub lvds_ss_percentage: u16,
7281 pub lvds_ss_rate_10hz: u16,
7282 pub hdmi_ss_percentage: u16,
7283 pub hdmi_ss_rate_10hz: u16,
7284 pub dvi_ss_percentage: u16,
7285 pub dvi_ss_rate_10hz: u16,
7286 pub dpphy_override: u16,
7287 pub lvds_misc: u16,
7288 pub backlight_pwm_hz: u16,
7289 pub memorytype: u8,
7290 pub umachannelnumber: u8,
7291 pub pwr_on_digon_to_de: u8,
7292 pub pwr_on_de_to_vary_bl: u8,
7293 pub pwr_down_vary_bloff_to_de: u8,
7294 pub pwr_down_de_to_digoff: u8,
7295 pub pwr_off_delay: u8,
7296 pub pwr_on_vary_bl_to_blon: u8,
7297 pub pwr_down_bloff_to_vary_bloff: u8,
7298 pub min_allowed_bl_level: u8,
7299 pub htc_hyst_limit: u8,
7300 pub htc_tmp_limit: u8,
7301 pub reserved1: u8,
7302 pub reserved2: u8,
7303 pub extdispconninfo: atom_external_display_connection_info,
7304 pub TMDS_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7305 pub hdmiCLK5_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7306 pub hdmiCLK8_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7307 pub rbr_tuningset: atom_DCN_dpphy_dp_tuningset,
7308 pub hbr3_tuningset: atom_DCN_dpphy_dp_tuningset,
7309 pub camera_info: atom_camera_data,
7310 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
7311 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
7312 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
7313 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
7314 pub hbr_tuningset: atom_DCN_dpphy_dp_tuningset,
7315 pub hbr2_tuningset: atom_DCN_dpphy_dp_tuningset,
7316 pub edp_tunings: atom_DCN_dpphy_dp_tuningset,
7317 pub hdmiCLK6_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7318 pub reserved: [u32; 63usize],
7319}
7320#[repr(C, packed)]
7321#[derive(Debug, Copy, Clone)]
7322pub struct edp_info_table {
7323 pub edp_backlight_pwm_hz: u16,
7324 pub edp_ss_percentage: u16,
7325 pub edp_ss_rate_10hz: u16,
7326 pub reserved1: u16,
7327 pub reserved2: u32,
7328 pub edp_pwr_on_off_delay: u8,
7329 pub edp_pwr_on_vary_bl_to_blon: u8,
7330 pub edp_pwr_down_bloff_to_vary_bloff: u8,
7331 pub edp_panel_bpc: u8,
7332 pub edp_bootup_bl_level: u8,
7333 pub reserved3: [u8; 3usize],
7334 pub reserved4: [u32; 3usize],
7335}
7336#[repr(C, packed)]
7337#[derive(Debug, Copy, Clone)]
7338pub struct atom_integrated_system_info_v2_1 {
7339 pub table_header: atom_common_table_header,
7340 pub vbios_misc: u32,
7341 pub gpucapinfo: u32,
7342 pub system_config: u32,
7343 pub cpucapinfo: u32,
7344 pub gpuclk_ss_percentage: u16,
7345 pub gpuclk_ss_type: u16,
7346 pub dpphy_override: u16,
7347 pub memorytype: u8,
7348 pub umachannelnumber: u8,
7349 pub htc_hyst_limit: u8,
7350 pub htc_tmp_limit: u8,
7351 pub reserved1: u8,
7352 pub reserved2: u8,
7353 pub edp1_info: edp_info_table,
7354 pub edp2_info: edp_info_table,
7355 pub reserved3: [u32; 8usize],
7356 pub extdispconninfo: atom_external_display_connection_info,
7357 pub TMDS_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7358 pub hdmiCLK5_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7359 pub hdmiCLK6_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7360 pub hdmiCLK8_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
7361 pub reserved4: [u32; 6usize],
7362 pub rbr_tuningset: atom_DCN_dpphy_dp_tuningset,
7363 pub hbr_tuningset: atom_DCN_dpphy_dp_tuningset,
7364 pub hbr2_tuningset: atom_DCN_dpphy_dp_tuningset,
7365 pub hbr3_tuningset: atom_DCN_dpphy_dp_tuningset,
7366 pub edp_tunings: atom_DCN_dpphy_dp_tuningset,
7367 pub reserved5: [u32; 28usize],
7368 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
7369 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
7370 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
7371 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
7372 pub reserved6: [u32; 30usize],
7373 pub reserved7: [u32; 32usize],
7374}
7375#[repr(C, packed)]
7376#[derive(Debug, Copy, Clone)]
7377pub struct atom_n6_display_phy_tuning_set {
7378 pub display_signal_type: u8,
7379 pub phy_sel: u8,
7380 pub preset_level: u8,
7381 pub reserved1: u8,
7382 pub reserved2: u32,
7383 pub speed_upto: u32,
7384 pub tx_vboost_level: u8,
7385 pub tx_vreg_v2i: u8,
7386 pub tx_vregdrv_byp: u8,
7387 pub tx_term_cntl: u8,
7388 pub tx_peak_level: u8,
7389 pub tx_slew_en: u8,
7390 pub tx_eq_pre: u8,
7391 pub tx_eq_main: u8,
7392 pub tx_eq_post: u8,
7393 pub tx_en_inv_pre: u8,
7394 pub tx_en_inv_post: u8,
7395 pub reserved3: u8,
7396 pub reserved4: u32,
7397 pub reserved5: u32,
7398 pub reserved6: u32,
7399}
7400#[repr(C)]
7401#[derive(Debug, Copy, Clone)]
7402pub struct atom_display_phy_tuning_info {
7403 pub table_header: atom_common_table_header,
7404 pub disp_phy_tuning: [atom_n6_display_phy_tuning_set; 1usize],
7405}
7406#[repr(C, packed)]
7407#[derive(Debug, Copy, Clone)]
7408pub struct atom_integrated_system_info_v2_2 {
7409 pub table_header: atom_common_table_header,
7410 pub vbios_misc: u32,
7411 pub gpucapinfo: u32,
7412 pub system_config: u32,
7413 pub cpucapinfo: u32,
7414 pub gpuclk_ss_percentage: u16,
7415 pub gpuclk_ss_type: u16,
7416 pub dpphy_override: u16,
7417 pub memorytype: u8,
7418 pub umachannelnumber: u8,
7419 pub htc_hyst_limit: u8,
7420 pub htc_tmp_limit: u8,
7421 pub reserved1: u8,
7422 pub reserved2: u8,
7423 pub edp1_info: edp_info_table,
7424 pub edp2_info: edp_info_table,
7425 pub reserved3: [u32; 8usize],
7426 pub extdispconninfo: atom_external_display_connection_info,
7427 pub reserved4: [u32; 189usize],
7428}
7429pub const atom_system_vbiosmisc_def_INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT:
7430 atom_system_vbiosmisc_def = 1;
7431pub type atom_system_vbiosmisc_def = ::core::ffi::c_uint;
7432pub const atom_system_gpucapinf_def_SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS: atom_system_gpucapinf_def =
7433 16;
7434pub type atom_system_gpucapinf_def = ::core::ffi::c_uint;
7435pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DVI_TUNINGSET:
7436 atom_sysinfo_dpphy_override_def = 1;
7437pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_HDMI_TUNINGSET:
7438 atom_sysinfo_dpphy_override_def = 2;
7439pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_HDMI6G_TUNINGSET:
7440 atom_sysinfo_dpphy_override_def = 4;
7441pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DP_TUNINGSET:
7442 atom_sysinfo_dpphy_override_def = 8;
7443pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DP_HBR3_TUNINGSET:
7444 atom_sysinfo_dpphy_override_def = 16;
7445pub type atom_sysinfo_dpphy_override_def = ::core::ffi::c_uint;
7446pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_888_FPDI_MODE:
7447 atom_sys_info_lvds_misc_def = 1;
7448pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_888_BPC_MODE: atom_sys_info_lvds_misc_def =
7449 4;
7450pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_OVERRIDE_EN: atom_sys_info_lvds_misc_def =
7451 8;
7452pub type atom_sys_info_lvds_misc_def = ::core::ffi::c_uint;
7453#[doc = "< Assign 01 to Other"]
7454pub const atom_dmi_t17_mem_type_def_OtherMemType: atom_dmi_t17_mem_type_def = 1;
7455#[doc = "< Assign 02 to Unknown"]
7456pub const atom_dmi_t17_mem_type_def_UnknownMemType: atom_dmi_t17_mem_type_def = 2;
7457#[doc = "< Assign 03 to DRAM"]
7458pub const atom_dmi_t17_mem_type_def_DramMemType: atom_dmi_t17_mem_type_def = 3;
7459#[doc = "< Assign 04 to EDRAM"]
7460pub const atom_dmi_t17_mem_type_def_EdramMemType: atom_dmi_t17_mem_type_def = 4;
7461#[doc = "< Assign 05 to VRAM"]
7462pub const atom_dmi_t17_mem_type_def_VramMemType: atom_dmi_t17_mem_type_def = 5;
7463#[doc = "< Assign 06 to SRAM"]
7464pub const atom_dmi_t17_mem_type_def_SramMemType: atom_dmi_t17_mem_type_def = 6;
7465#[doc = "< Assign 07 to RAM"]
7466pub const atom_dmi_t17_mem_type_def_RamMemType: atom_dmi_t17_mem_type_def = 7;
7467#[doc = "< Assign 08 to ROM"]
7468pub const atom_dmi_t17_mem_type_def_RomMemType: atom_dmi_t17_mem_type_def = 8;
7469#[doc = "< Assign 09 to Flash"]
7470pub const atom_dmi_t17_mem_type_def_FlashMemType: atom_dmi_t17_mem_type_def = 9;
7471#[doc = "< Assign 10 to EEPROM"]
7472pub const atom_dmi_t17_mem_type_def_EepromMemType: atom_dmi_t17_mem_type_def = 10;
7473#[doc = "< Assign 11 to FEPROM"]
7474pub const atom_dmi_t17_mem_type_def_FepromMemType: atom_dmi_t17_mem_type_def = 11;
7475#[doc = "< Assign 12 to EPROM"]
7476pub const atom_dmi_t17_mem_type_def_EpromMemType: atom_dmi_t17_mem_type_def = 12;
7477#[doc = "< Assign 13 to CDRAM"]
7478pub const atom_dmi_t17_mem_type_def_CdramMemType: atom_dmi_t17_mem_type_def = 13;
7479#[doc = "< Assign 14 to 3DRAM"]
7480pub const atom_dmi_t17_mem_type_def_ThreeDramMemType: atom_dmi_t17_mem_type_def = 14;
7481#[doc = "< Assign 15 to SDRAM"]
7482pub const atom_dmi_t17_mem_type_def_SdramMemType: atom_dmi_t17_mem_type_def = 15;
7483#[doc = "< Assign 16 to SGRAM"]
7484pub const atom_dmi_t17_mem_type_def_SgramMemType: atom_dmi_t17_mem_type_def = 16;
7485#[doc = "< Assign 17 to RDRAM"]
7486pub const atom_dmi_t17_mem_type_def_RdramMemType: atom_dmi_t17_mem_type_def = 17;
7487#[doc = "< Assign 18 to DDR"]
7488pub const atom_dmi_t17_mem_type_def_DdrMemType: atom_dmi_t17_mem_type_def = 18;
7489#[doc = "< Assign 19 to DDR2"]
7490pub const atom_dmi_t17_mem_type_def_Ddr2MemType: atom_dmi_t17_mem_type_def = 19;
7491#[doc = "< Assign 20 to DDR2 FB-DIMM"]
7492pub const atom_dmi_t17_mem_type_def_Ddr2FbdimmMemType: atom_dmi_t17_mem_type_def = 20;
7493#[doc = "< Assign 24 to DDR3"]
7494pub const atom_dmi_t17_mem_type_def_Ddr3MemType: atom_dmi_t17_mem_type_def = 24;
7495#[doc = "< Assign 25 to FBD2"]
7496pub const atom_dmi_t17_mem_type_def_Fbd2MemType: atom_dmi_t17_mem_type_def = 25;
7497#[doc = "< Assign 26 to DDR4"]
7498pub const atom_dmi_t17_mem_type_def_Ddr4MemType: atom_dmi_t17_mem_type_def = 26;
7499#[doc = "< Assign 27 to LPDDR"]
7500pub const atom_dmi_t17_mem_type_def_LpDdrMemType: atom_dmi_t17_mem_type_def = 27;
7501#[doc = "< Assign 28 to LPDDR2"]
7502pub const atom_dmi_t17_mem_type_def_LpDdr2MemType: atom_dmi_t17_mem_type_def = 28;
7503#[doc = "< Assign 29 to LPDDR3"]
7504pub const atom_dmi_t17_mem_type_def_LpDdr3MemType: atom_dmi_t17_mem_type_def = 29;
7505#[doc = "< Assign 30 to LPDDR4"]
7506pub const atom_dmi_t17_mem_type_def_LpDdr4MemType: atom_dmi_t17_mem_type_def = 30;
7507#[doc = "< Assign 31 to GDDR6"]
7508pub const atom_dmi_t17_mem_type_def_GDdr6MemType: atom_dmi_t17_mem_type_def = 31;
7509#[doc = "< Assign 32 to HBM"]
7510pub const atom_dmi_t17_mem_type_def_HbmMemType: atom_dmi_t17_mem_type_def = 32;
7511#[doc = "< Assign 33 to HBM2"]
7512pub const atom_dmi_t17_mem_type_def_Hbm2MemType: atom_dmi_t17_mem_type_def = 33;
7513#[doc = "< Assign 34 to DDR5"]
7514pub const atom_dmi_t17_mem_type_def_Ddr5MemType: atom_dmi_t17_mem_type_def = 34;
7515#[doc = "< Assign 35 to LPDDR5"]
7516pub const atom_dmi_t17_mem_type_def_LpDdr5MemType: atom_dmi_t17_mem_type_def = 35;
7517pub type atom_dmi_t17_mem_type_def = ::core::ffi::c_uint;
7518#[repr(C, packed)]
7519#[derive(Debug, Copy, Clone)]
7520pub struct atom_fusion_system_info_v4 {
7521 pub sysinfo: atom_integrated_system_info_v1_11,
7522 pub powerplayinfo: [u32; 256usize],
7523}
7524#[repr(C, packed)]
7525#[derive(Debug, Copy, Clone)]
7526pub struct atom_gfx_info_v2_2 {
7527 pub table_header: atom_common_table_header,
7528 pub gfxip_min_ver: u8,
7529 pub gfxip_max_ver: u8,
7530 pub max_shader_engines: u8,
7531 pub max_tile_pipes: u8,
7532 pub max_cu_per_sh: u8,
7533 pub max_sh_per_se: u8,
7534 pub max_backends_per_se: u8,
7535 pub max_texture_channel_caches: u8,
7536 pub regaddr_cp_dma_src_addr: u32,
7537 pub regaddr_cp_dma_src_addr_hi: u32,
7538 pub regaddr_cp_dma_dst_addr: u32,
7539 pub regaddr_cp_dma_dst_addr_hi: u32,
7540 pub regaddr_cp_dma_command: u32,
7541 pub regaddr_cp_status: u32,
7542 pub regaddr_rlc_gpu_clock_32: u32,
7543 pub rlc_gpu_timer_refclk: u32,
7544}
7545#[repr(C, packed)]
7546#[derive(Debug, Copy, Clone)]
7547pub struct atom_gfx_info_v2_3 {
7548 pub table_header: atom_common_table_header,
7549 pub gfxip_min_ver: u8,
7550 pub gfxip_max_ver: u8,
7551 pub max_shader_engines: u8,
7552 pub max_tile_pipes: u8,
7553 pub max_cu_per_sh: u8,
7554 pub max_sh_per_se: u8,
7555 pub max_backends_per_se: u8,
7556 pub max_texture_channel_caches: u8,
7557 pub regaddr_cp_dma_src_addr: u32,
7558 pub regaddr_cp_dma_src_addr_hi: u32,
7559 pub regaddr_cp_dma_dst_addr: u32,
7560 pub regaddr_cp_dma_dst_addr_hi: u32,
7561 pub regaddr_cp_dma_command: u32,
7562 pub regaddr_cp_status: u32,
7563 pub regaddr_rlc_gpu_clock_32: u32,
7564 pub rlc_gpu_timer_refclk: u32,
7565 pub active_cu_per_sh: u8,
7566 pub active_rb_per_se: u8,
7567 pub gcgoldenoffset: u16,
7568 pub rm21_sram_vmin_value: u32,
7569}
7570#[repr(C, packed)]
7571#[derive(Debug, Copy, Clone)]
7572pub struct atom_gfx_info_v2_4 {
7573 pub table_header: atom_common_table_header,
7574 pub gfxip_min_ver: u8,
7575 pub gfxip_max_ver: u8,
7576 pub max_shader_engines: u8,
7577 pub reserved: u8,
7578 pub max_cu_per_sh: u8,
7579 pub max_sh_per_se: u8,
7580 pub max_backends_per_se: u8,
7581 pub max_texture_channel_caches: u8,
7582 pub regaddr_cp_dma_src_addr: u32,
7583 pub regaddr_cp_dma_src_addr_hi: u32,
7584 pub regaddr_cp_dma_dst_addr: u32,
7585 pub regaddr_cp_dma_dst_addr_hi: u32,
7586 pub regaddr_cp_dma_command: u32,
7587 pub regaddr_cp_status: u32,
7588 pub regaddr_rlc_gpu_clock_32: u32,
7589 pub rlc_gpu_timer_refclk: u32,
7590 pub active_cu_per_sh: u8,
7591 pub active_rb_per_se: u8,
7592 pub gcgoldenoffset: u16,
7593 pub gc_num_gprs: u16,
7594 pub gc_gsprim_buff_depth: u16,
7595 pub gc_parameter_cache_depth: u16,
7596 pub gc_wave_size: u16,
7597 pub gc_max_waves_per_simd: u16,
7598 pub gc_lds_size: u16,
7599 pub gc_num_max_gs_thds: u8,
7600 pub gc_gs_table_depth: u8,
7601 pub gc_double_offchip_lds_buffer: u8,
7602 pub gc_max_scratch_slots_per_cu: u8,
7603 pub sram_rm_fuses_val: u32,
7604 pub sram_custom_rm_fuses_val: u32,
7605}
7606#[repr(C, packed)]
7607#[derive(Debug, Copy, Clone)]
7608pub struct atom_gfx_info_v2_7 {
7609 pub table_header: atom_common_table_header,
7610 pub gfxip_min_ver: u8,
7611 pub gfxip_max_ver: u8,
7612 pub max_shader_engines: u8,
7613 pub reserved: u8,
7614 pub max_cu_per_sh: u8,
7615 pub max_sh_per_se: u8,
7616 pub max_backends_per_se: u8,
7617 pub max_texture_channel_caches: u8,
7618 pub regaddr_cp_dma_src_addr: u32,
7619 pub regaddr_cp_dma_src_addr_hi: u32,
7620 pub regaddr_cp_dma_dst_addr: u32,
7621 pub regaddr_cp_dma_dst_addr_hi: u32,
7622 pub regaddr_cp_dma_command: u32,
7623 pub regaddr_cp_status: u32,
7624 pub regaddr_rlc_gpu_clock_32: u32,
7625 pub rlc_gpu_timer_refclk: u32,
7626 pub active_cu_per_sh: u8,
7627 pub active_rb_per_se: u8,
7628 pub gcgoldenoffset: u16,
7629 pub gc_num_gprs: u16,
7630 pub gc_gsprim_buff_depth: u16,
7631 pub gc_parameter_cache_depth: u16,
7632 pub gc_wave_size: u16,
7633 pub gc_max_waves_per_simd: u16,
7634 pub gc_lds_size: u16,
7635 pub gc_num_max_gs_thds: u8,
7636 pub gc_gs_table_depth: u8,
7637 pub gc_double_offchip_lds_buffer: u8,
7638 pub gc_max_scratch_slots_per_cu: u8,
7639 pub sram_rm_fuses_val: u32,
7640 pub sram_custom_rm_fuses_val: u32,
7641 pub cut_cu: u8,
7642 pub active_cu_total: u8,
7643 pub cu_reserved: [u8; 2usize],
7644 pub gc_config: u32,
7645 pub inactive_cu_per_se: [u8; 8usize],
7646 pub reserved2: [u32; 6usize],
7647}
7648#[repr(C, packed)]
7649#[derive(Debug, Copy, Clone)]
7650pub struct atom_gfx_info_v3_0 {
7651 pub table_header: atom_common_table_header,
7652 pub gfxip_min_ver: u8,
7653 pub gfxip_max_ver: u8,
7654 pub max_shader_engines: u8,
7655 pub max_tile_pipes: u8,
7656 pub max_cu_per_sh: u8,
7657 pub max_sh_per_se: u8,
7658 pub max_backends_per_se: u8,
7659 pub max_texture_channel_caches: u8,
7660 pub regaddr_lsdma_queue0_rb_rptr: u32,
7661 pub regaddr_lsdma_queue0_rb_rptr_hi: u32,
7662 pub regaddr_lsdma_queue0_rb_wptr: u32,
7663 pub regaddr_lsdma_queue0_rb_wptr_hi: u32,
7664 pub regaddr_lsdma_command: u32,
7665 pub regaddr_lsdma_status: u32,
7666 pub regaddr_golden_tsc_count_lower: u32,
7667 pub golden_tsc_count_lower_refclk: u32,
7668 pub active_wgp_per_se: u8,
7669 pub active_rb_per_se: u8,
7670 pub active_se: u8,
7671 pub reserved1: u8,
7672 pub sram_rm_fuses_val: u32,
7673 pub sram_custom_rm_fuses_val: u32,
7674 pub inactive_sa_mask: u32,
7675 pub gc_config: u32,
7676 pub inactive_wgp: [u8; 16usize],
7677 pub inactive_rb: [u8; 16usize],
7678 pub gdfll_as_wait_ctrl_val: u32,
7679 pub gdfll_as_step_ctrl_val: u32,
7680 pub reserved: [u32; 8usize],
7681}
7682#[repr(C, packed)]
7683#[derive(Debug, Copy, Clone)]
7684pub struct atom_smu_info_v3_1 {
7685 pub table_header: atom_common_table_header,
7686 pub smuip_min_ver: u8,
7687 pub smuip_max_ver: u8,
7688 pub smu_rsd1: u8,
7689 pub gpuclk_ss_mode: u8,
7690 pub sclk_ss_percentage: u16,
7691 pub sclk_ss_rate_10hz: u16,
7692 pub gpuclk_ss_percentage: u16,
7693 pub gpuclk_ss_rate_10hz: u16,
7694 pub core_refclk_10khz: u32,
7695 pub ac_dc_gpio_bit: u8,
7696 pub ac_dc_polarity: u8,
7697 pub vr0hot_gpio_bit: u8,
7698 pub vr0hot_polarity: u8,
7699 pub vr1hot_gpio_bit: u8,
7700 pub vr1hot_polarity: u8,
7701 pub fw_ctf_gpio_bit: u8,
7702 pub fw_ctf_polarity: u8,
7703}
7704#[repr(C, packed)]
7705#[derive(Debug, Copy, Clone)]
7706pub struct atom_smu_info_v3_2 {
7707 pub table_header: atom_common_table_header,
7708 pub smuip_min_ver: u8,
7709 pub smuip_max_ver: u8,
7710 pub smu_rsd1: u8,
7711 pub gpuclk_ss_mode: u8,
7712 pub sclk_ss_percentage: u16,
7713 pub sclk_ss_rate_10hz: u16,
7714 pub gpuclk_ss_percentage: u16,
7715 pub gpuclk_ss_rate_10hz: u16,
7716 pub core_refclk_10khz: u32,
7717 pub ac_dc_gpio_bit: u8,
7718 pub ac_dc_polarity: u8,
7719 pub vr0hot_gpio_bit: u8,
7720 pub vr0hot_polarity: u8,
7721 pub vr1hot_gpio_bit: u8,
7722 pub vr1hot_polarity: u8,
7723 pub fw_ctf_gpio_bit: u8,
7724 pub fw_ctf_polarity: u8,
7725 pub pcc_gpio_bit: u8,
7726 pub pcc_gpio_polarity: u8,
7727 pub smugoldenoffset: u16,
7728 pub gpupll_vco_freq_10khz: u32,
7729 pub bootup_smnclk_10khz: u32,
7730 pub bootup_socclk_10khz: u32,
7731 pub bootup_mp0clk_10khz: u32,
7732 pub bootup_mp1clk_10khz: u32,
7733 pub bootup_lclk_10khz: u32,
7734 pub bootup_dcefclk_10khz: u32,
7735 pub ctf_threshold_override_value: u32,
7736 pub reserved: [u32; 5usize],
7737}
7738#[repr(C, packed)]
7739#[derive(Debug, Copy, Clone)]
7740pub struct atom_smu_info_v3_3 {
7741 pub table_header: atom_common_table_header,
7742 pub smuip_min_ver: u8,
7743 pub smuip_max_ver: u8,
7744 pub waflclk_ss_mode: u8,
7745 pub gpuclk_ss_mode: u8,
7746 pub sclk_ss_percentage: u16,
7747 pub sclk_ss_rate_10hz: u16,
7748 pub gpuclk_ss_percentage: u16,
7749 pub gpuclk_ss_rate_10hz: u16,
7750 pub core_refclk_10khz: u32,
7751 pub ac_dc_gpio_bit: u8,
7752 pub ac_dc_polarity: u8,
7753 pub vr0hot_gpio_bit: u8,
7754 pub vr0hot_polarity: u8,
7755 pub vr1hot_gpio_bit: u8,
7756 pub vr1hot_polarity: u8,
7757 pub fw_ctf_gpio_bit: u8,
7758 pub fw_ctf_polarity: u8,
7759 pub pcc_gpio_bit: u8,
7760 pub pcc_gpio_polarity: u8,
7761 pub smugoldenoffset: u16,
7762 pub gpupll_vco_freq_10khz: u32,
7763 pub bootup_smnclk_10khz: u32,
7764 pub bootup_socclk_10khz: u32,
7765 pub bootup_mp0clk_10khz: u32,
7766 pub bootup_mp1clk_10khz: u32,
7767 pub bootup_lclk_10khz: u32,
7768 pub bootup_dcefclk_10khz: u32,
7769 pub ctf_threshold_override_value: u32,
7770 pub syspll3_0_vco_freq_10khz: u32,
7771 pub syspll3_1_vco_freq_10khz: u32,
7772 pub bootup_fclk_10khz: u32,
7773 pub bootup_waflclk_10khz: u32,
7774 pub smu_info_caps: u32,
7775 pub waflclk_ss_percentage: u16,
7776 pub smuinitoffset: u16,
7777 pub reserved: u32,
7778}
7779#[repr(C, packed)]
7780#[derive(Debug, Copy, Clone)]
7781pub struct atom_smu_info_v3_5 {
7782 pub table_header: atom_common_table_header,
7783 pub smuip_min_ver: u8,
7784 pub smuip_max_ver: u8,
7785 pub waflclk_ss_mode: u8,
7786 pub gpuclk_ss_mode: u8,
7787 pub sclk_ss_percentage: u16,
7788 pub sclk_ss_rate_10hz: u16,
7789 pub gpuclk_ss_percentage: u16,
7790 pub gpuclk_ss_rate_10hz: u16,
7791 pub core_refclk_10khz: u32,
7792 pub syspll0_1_vco_freq_10khz: u32,
7793 pub syspll0_2_vco_freq_10khz: u32,
7794 pub pcc_gpio_bit: u8,
7795 pub pcc_gpio_polarity: u8,
7796 pub smugoldenoffset: u16,
7797 pub syspll0_0_vco_freq_10khz: u32,
7798 pub bootup_smnclk_10khz: u32,
7799 pub bootup_socclk_10khz: u32,
7800 pub bootup_mp0clk_10khz: u32,
7801 pub bootup_mp1clk_10khz: u32,
7802 pub bootup_lclk_10khz: u32,
7803 pub bootup_dcefclk_10khz: u32,
7804 pub ctf_threshold_override_value: u32,
7805 pub syspll3_0_vco_freq_10khz: u32,
7806 pub syspll3_1_vco_freq_10khz: u32,
7807 pub bootup_fclk_10khz: u32,
7808 pub bootup_waflclk_10khz: u32,
7809 pub smu_info_caps: u32,
7810 pub waflclk_ss_percentage: u16,
7811 pub smuinitoffset: u16,
7812 pub bootup_dprefclk_10khz: u32,
7813 pub bootup_usbclk_10khz: u32,
7814 pub smb_slave_address: u32,
7815 pub cg_fdo_ctrl0_val: u32,
7816 pub cg_fdo_ctrl1_val: u32,
7817 pub cg_fdo_ctrl2_val: u32,
7818 pub gdfll_as_wait_ctrl_val: u32,
7819 pub gdfll_as_step_ctrl_val: u32,
7820 pub bootup_dtbclk_10khz: u32,
7821 pub fclk_syspll_refclk_10khz: u32,
7822 pub smusvi_svc0_val: u32,
7823 pub smusvi_svc1_val: u32,
7824 pub smusvi_svd0_val: u32,
7825 pub smusvi_svd1_val: u32,
7826 pub smusvi_svt0_val: u32,
7827 pub smusvi_svt1_val: u32,
7828 pub cg_tach_ctrl_val: u32,
7829 pub cg_pump_ctrl1_val: u32,
7830 pub cg_pump_tach_ctrl_val: u32,
7831 pub thm_ctf_delay_val: u32,
7832 pub thm_thermal_int_ctrl_val: u32,
7833 pub thm_tmon_config_val: u32,
7834 pub reserved: [u32; 16usize],
7835}
7836#[repr(C, packed)]
7837#[derive(Debug, Copy, Clone)]
7838pub struct atom_smu_info_v3_6 {
7839 pub table_header: atom_common_table_header,
7840 pub smuip_min_ver: u8,
7841 pub smuip_max_ver: u8,
7842 pub waflclk_ss_mode: u8,
7843 pub gpuclk_ss_mode: u8,
7844 pub sclk_ss_percentage: u16,
7845 pub sclk_ss_rate_10hz: u16,
7846 pub gpuclk_ss_percentage: u16,
7847 pub gpuclk_ss_rate_10hz: u16,
7848 pub core_refclk_10khz: u32,
7849 pub syspll0_1_vco_freq_10khz: u32,
7850 pub syspll0_2_vco_freq_10khz: u32,
7851 pub pcc_gpio_bit: u8,
7852 pub pcc_gpio_polarity: u8,
7853 pub smugoldenoffset: u16,
7854 pub syspll0_0_vco_freq_10khz: u32,
7855 pub bootup_smnclk_10khz: u32,
7856 pub bootup_socclk_10khz: u32,
7857 pub bootup_mp0clk_10khz: u32,
7858 pub bootup_mp1clk_10khz: u32,
7859 pub bootup_lclk_10khz: u32,
7860 pub bootup_dxioclk_10khz: u32,
7861 pub ctf_threshold_override_value: u32,
7862 pub syspll3_0_vco_freq_10khz: u32,
7863 pub syspll3_1_vco_freq_10khz: u32,
7864 pub bootup_fclk_10khz: u32,
7865 pub bootup_waflclk_10khz: u32,
7866 pub smu_info_caps: u32,
7867 pub waflclk_ss_percentage: u16,
7868 pub smuinitoffset: u16,
7869 pub bootup_gfxavsclk_10khz: u32,
7870 pub bootup_mpioclk_10khz: u32,
7871 pub smb_slave_address: u32,
7872 pub cg_fdo_ctrl0_val: u32,
7873 pub cg_fdo_ctrl1_val: u32,
7874 pub cg_fdo_ctrl2_val: u32,
7875 pub gdfll_as_wait_ctrl_val: u32,
7876 pub gdfll_as_step_ctrl_val: u32,
7877 pub reserved_clk: u32,
7878 pub fclk_syspll_refclk_10khz: u32,
7879 pub smusvi_svc0_val: u32,
7880 pub smusvi_svc1_val: u32,
7881 pub smusvi_svd0_val: u32,
7882 pub smusvi_svd1_val: u32,
7883 pub smusvi_svt0_val: u32,
7884 pub smusvi_svt1_val: u32,
7885 pub cg_tach_ctrl_val: u32,
7886 pub cg_pump_ctrl1_val: u32,
7887 pub cg_pump_tach_ctrl_val: u32,
7888 pub thm_ctf_delay_val: u32,
7889 pub thm_thermal_int_ctrl_val: u32,
7890 pub thm_tmon_config_val: u32,
7891 pub bootup_vclk_10khz: u32,
7892 pub bootup_dclk_10khz: u32,
7893 pub smu_gpiopad_pu_en_val: u32,
7894 pub smu_gpiopad_pd_en_val: u32,
7895 pub reserved: [u32; 12usize],
7896}
7897#[repr(C, packed)]
7898#[derive(Debug, Copy, Clone)]
7899pub struct atom_smu_info_v4_0 {
7900 pub table_header: atom_common_table_header,
7901 pub bootup_gfxclk_bypass_10khz: u32,
7902 pub bootup_usrclk_10khz: u32,
7903 pub bootup_csrclk_10khz: u32,
7904 pub core_refclk_10khz: u32,
7905 pub syspll1_vco_freq_10khz: u32,
7906 pub syspll2_vco_freq_10khz: u32,
7907 pub pcc_gpio_bit: u8,
7908 pub pcc_gpio_polarity: u8,
7909 pub bootup_vddusr_mv: u16,
7910 pub syspll0_vco_freq_10khz: u32,
7911 pub bootup_smnclk_10khz: u32,
7912 pub bootup_socclk_10khz: u32,
7913 pub bootup_mp0clk_10khz: u32,
7914 pub bootup_mp1clk_10khz: u32,
7915 pub bootup_lclk_10khz: u32,
7916 pub bootup_dcefclk_10khz: u32,
7917 pub ctf_threshold_override_value: u32,
7918 pub syspll3_vco_freq_10khz: u32,
7919 pub mm_syspll_vco_freq_10khz: u32,
7920 pub bootup_fclk_10khz: u32,
7921 pub bootup_waflclk_10khz: u32,
7922 pub smu_info_caps: u32,
7923 pub waflclk_ss_percentage: u16,
7924 pub smuinitoffset: u16,
7925 pub bootup_dprefclk_10khz: u32,
7926 pub bootup_usbclk_10khz: u32,
7927 pub smb_slave_address: u32,
7928 pub cg_fdo_ctrl0_val: u32,
7929 pub cg_fdo_ctrl1_val: u32,
7930 pub cg_fdo_ctrl2_val: u32,
7931 pub gdfll_as_wait_ctrl_val: u32,
7932 pub gdfll_as_step_ctrl_val: u32,
7933 pub bootup_dtbclk_10khz: u32,
7934 pub fclk_syspll_refclk_10khz: u32,
7935 pub smusvi_svc0_val: u32,
7936 pub smusvi_svc1_val: u32,
7937 pub smusvi_svd0_val: u32,
7938 pub smusvi_svd1_val: u32,
7939 pub smusvi_svt0_val: u32,
7940 pub smusvi_svt1_val: u32,
7941 pub cg_tach_ctrl_val: u32,
7942 pub cg_pump_ctrl1_val: u32,
7943 pub cg_pump_tach_ctrl_val: u32,
7944 pub thm_ctf_delay_val: u32,
7945 pub thm_thermal_int_ctrl_val: u32,
7946 pub thm_tmon_config_val: u32,
7947 pub smbus_timing_cntrl0_val: u32,
7948 pub smbus_timing_cntrl1_val: u32,
7949 pub smbus_timing_cntrl2_val: u32,
7950 pub pwr_disp_timer_global_control_val: u32,
7951 pub bootup_mpioclk_10khz: u32,
7952 pub bootup_dclk0_10khz: u32,
7953 pub bootup_vclk0_10khz: u32,
7954 pub bootup_dclk1_10khz: u32,
7955 pub bootup_vclk1_10khz: u32,
7956 pub bootup_baco400clk_10khz: u32,
7957 pub bootup_baco1200clk_bypass_10khz: u32,
7958 pub bootup_baco700clk_bypass_10khz: u32,
7959 pub reserved: [u32; 16usize],
7960}
7961#[repr(C, packed)]
7962#[derive(Debug, Copy, Clone)]
7963pub struct atom_smc_dpm_info_v4_1 {
7964 pub table_header: atom_common_table_header,
7965 pub liquid1_i2c_address: u8,
7966 pub liquid2_i2c_address: u8,
7967 pub vr_i2c_address: u8,
7968 pub plx_i2c_address: u8,
7969 pub liquid_i2c_linescl: u8,
7970 pub liquid_i2c_linesda: u8,
7971 pub vr_i2c_linescl: u8,
7972 pub vr_i2c_linesda: u8,
7973 pub plx_i2c_linescl: u8,
7974 pub plx_i2c_linesda: u8,
7975 pub vrsensorpresent: u8,
7976 pub liquidsensorpresent: u8,
7977 pub maxvoltagestepgfx: u16,
7978 pub maxvoltagestepsoc: u16,
7979 pub vddgfxvrmapping: u8,
7980 pub vddsocvrmapping: u8,
7981 pub vddmem0vrmapping: u8,
7982 pub vddmem1vrmapping: u8,
7983 pub gfxulvphasesheddingmask: u8,
7984 pub soculvphasesheddingmask: u8,
7985 pub padding8_v: [u8; 2usize],
7986 pub gfxmaxcurrent: u16,
7987 pub gfxoffset: u8,
7988 pub padding_telemetrygfx: u8,
7989 pub socmaxcurrent: u16,
7990 pub socoffset: u8,
7991 pub padding_telemetrysoc: u8,
7992 pub mem0maxcurrent: u16,
7993 pub mem0offset: u8,
7994 pub padding_telemetrymem0: u8,
7995 pub mem1maxcurrent: u16,
7996 pub mem1offset: u8,
7997 pub padding_telemetrymem1: u8,
7998 pub acdcgpio: u8,
7999 pub acdcpolarity: u8,
8000 pub vr0hotgpio: u8,
8001 pub vr0hotpolarity: u8,
8002 pub vr1hotgpio: u8,
8003 pub vr1hotpolarity: u8,
8004 pub padding1: u8,
8005 pub padding2: u8,
8006 pub ledpin0: u8,
8007 pub ledpin1: u8,
8008 pub ledpin2: u8,
8009 pub padding8_4: u8,
8010 pub pllgfxclkspreadenabled: u8,
8011 pub pllgfxclkspreadpercent: u8,
8012 pub pllgfxclkspreadfreq: u16,
8013 pub uclkspreadenabled: u8,
8014 pub uclkspreadpercent: u8,
8015 pub uclkspreadfreq: u16,
8016 pub socclkspreadenabled: u8,
8017 pub socclkspreadpercent: u8,
8018 pub socclkspreadfreq: u16,
8019 pub acggfxclkspreadenabled: u8,
8020 pub acggfxclkspreadpercent: u8,
8021 pub acggfxclkspreadfreq: u16,
8022 pub Vr2_I2C_address: u8,
8023 pub padding_vr2: [u8; 3usize],
8024 pub boardreserved: [u32; 9usize],
8025}
8026#[repr(C, packed)]
8027#[derive(Debug, Copy, Clone)]
8028pub struct atom_smc_dpm_info_v4_3 {
8029 pub table_header: atom_common_table_header,
8030 pub liquid1_i2c_address: u8,
8031 pub liquid2_i2c_address: u8,
8032 pub vr_i2c_address: u8,
8033 pub plx_i2c_address: u8,
8034 pub liquid_i2c_linescl: u8,
8035 pub liquid_i2c_linesda: u8,
8036 pub vr_i2c_linescl: u8,
8037 pub vr_i2c_linesda: u8,
8038 pub plx_i2c_linescl: u8,
8039 pub plx_i2c_linesda: u8,
8040 pub vrsensorpresent: u8,
8041 pub liquidsensorpresent: u8,
8042 pub maxvoltagestepgfx: u16,
8043 pub maxvoltagestepsoc: u16,
8044 pub vddgfxvrmapping: u8,
8045 pub vddsocvrmapping: u8,
8046 pub vddmem0vrmapping: u8,
8047 pub vddmem1vrmapping: u8,
8048 pub gfxulvphasesheddingmask: u8,
8049 pub soculvphasesheddingmask: u8,
8050 pub externalsensorpresent: u8,
8051 pub padding8_v: u8,
8052 pub gfxmaxcurrent: u16,
8053 pub gfxoffset: u8,
8054 pub padding_telemetrygfx: u8,
8055 pub socmaxcurrent: u16,
8056 pub socoffset: u8,
8057 pub padding_telemetrysoc: u8,
8058 pub mem0maxcurrent: u16,
8059 pub mem0offset: u8,
8060 pub padding_telemetrymem0: u8,
8061 pub mem1maxcurrent: u16,
8062 pub mem1offset: u8,
8063 pub padding_telemetrymem1: u8,
8064 pub acdcgpio: u8,
8065 pub acdcpolarity: u8,
8066 pub vr0hotgpio: u8,
8067 pub vr0hotpolarity: u8,
8068 pub vr1hotgpio: u8,
8069 pub vr1hotpolarity: u8,
8070 pub padding1: u8,
8071 pub padding2: u8,
8072 pub ledpin0: u8,
8073 pub ledpin1: u8,
8074 pub ledpin2: u8,
8075 pub padding8_4: u8,
8076 pub pllgfxclkspreadenabled: u8,
8077 pub pllgfxclkspreadpercent: u8,
8078 pub pllgfxclkspreadfreq: u16,
8079 pub uclkspreadenabled: u8,
8080 pub uclkspreadpercent: u8,
8081 pub uclkspreadfreq: u16,
8082 pub fclkspreadenabled: u8,
8083 pub fclkspreadpercent: u8,
8084 pub fclkspreadfreq: u16,
8085 pub fllgfxclkspreadenabled: u8,
8086 pub fllgfxclkspreadpercent: u8,
8087 pub fllgfxclkspreadfreq: u16,
8088 pub boardreserved: [u32; 10usize],
8089}
8090#[repr(C, packed)]
8091#[derive(Debug, Copy, Clone)]
8092pub struct smudpm_i2ccontrollerconfig_t {
8093 pub enabled: u32,
8094 pub slaveaddress: u32,
8095 pub controllerport: u32,
8096 pub controllername: u32,
8097 pub thermalthrottler: u32,
8098 pub i2cprotocol: u32,
8099 pub i2cspeed: u32,
8100}
8101#[repr(C, packed)]
8102#[derive(Debug, Copy, Clone)]
8103pub struct atom_smc_dpm_info_v4_4 {
8104 pub table_header: atom_common_table_header,
8105 pub i2c_padding: [u32; 3usize],
8106 pub maxvoltagestepgfx: u16,
8107 pub maxvoltagestepsoc: u16,
8108 pub vddgfxvrmapping: u8,
8109 pub vddsocvrmapping: u8,
8110 pub vddmem0vrmapping: u8,
8111 pub vddmem1vrmapping: u8,
8112 pub gfxulvphasesheddingmask: u8,
8113 pub soculvphasesheddingmask: u8,
8114 pub externalsensorpresent: u8,
8115 pub padding8_v: u8,
8116 pub gfxmaxcurrent: u16,
8117 pub gfxoffset: u8,
8118 pub padding_telemetrygfx: u8,
8119 pub socmaxcurrent: u16,
8120 pub socoffset: u8,
8121 pub padding_telemetrysoc: u8,
8122 pub mem0maxcurrent: u16,
8123 pub mem0offset: u8,
8124 pub padding_telemetrymem0: u8,
8125 pub mem1maxcurrent: u16,
8126 pub mem1offset: u8,
8127 pub padding_telemetrymem1: u8,
8128 pub acdcgpio: u8,
8129 pub acdcpolarity: u8,
8130 pub vr0hotgpio: u8,
8131 pub vr0hotpolarity: u8,
8132 pub vr1hotgpio: u8,
8133 pub vr1hotpolarity: u8,
8134 pub padding1: u8,
8135 pub padding2: u8,
8136 pub ledpin0: u8,
8137 pub ledpin1: u8,
8138 pub ledpin2: u8,
8139 pub padding8_4: u8,
8140 pub pllgfxclkspreadenabled: u8,
8141 pub pllgfxclkspreadpercent: u8,
8142 pub pllgfxclkspreadfreq: u16,
8143 pub uclkspreadenabled: u8,
8144 pub uclkspreadpercent: u8,
8145 pub uclkspreadfreq: u16,
8146 pub fclkspreadenabled: u8,
8147 pub fclkspreadpercent: u8,
8148 pub fclkspreadfreq: u16,
8149 pub fllgfxclkspreadenabled: u8,
8150 pub fllgfxclkspreadpercent: u8,
8151 pub fllgfxclkspreadfreq: u16,
8152 pub i2ccontrollers: [smudpm_i2ccontrollerconfig_t; 7usize],
8153 pub boardreserved: [u32; 10usize],
8154}
8155pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX:
8156 smudpm_v4_5_i2ccontrollername_e = 0;
8157pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC:
8158 smudpm_v4_5_i2ccontrollername_e = 1;
8159pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI:
8160 smudpm_v4_5_i2ccontrollername_e = 2;
8161pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD:
8162 smudpm_v4_5_i2ccontrollername_e = 3;
8163pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0:
8164 smudpm_v4_5_i2ccontrollername_e = 4;
8165pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1:
8166 smudpm_v4_5_i2ccontrollername_e = 5;
8167pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_PLX:
8168 smudpm_v4_5_i2ccontrollername_e = 6;
8169pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_SPARE:
8170 smudpm_v4_5_i2ccontrollername_e = 7;
8171pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_COUNT:
8172 smudpm_v4_5_i2ccontrollername_e = 8;
8173pub type smudpm_v4_5_i2ccontrollername_e = ::core::ffi::c_uint;
8174pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE:
8175 smudpm_v4_5_i2ccontrollerthrottler_e = 0;
8176pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX:
8177 smudpm_v4_5_i2ccontrollerthrottler_e = 1;
8178pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC:
8179 smudpm_v4_5_i2ccontrollerthrottler_e = 2;
8180pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI:
8181 smudpm_v4_5_i2ccontrollerthrottler_e = 3;
8182pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD:
8183 smudpm_v4_5_i2ccontrollerthrottler_e = 4;
8184pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0:
8185 smudpm_v4_5_i2ccontrollerthrottler_e = 5;
8186pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1:
8187 smudpm_v4_5_i2ccontrollerthrottler_e = 6;
8188pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX:
8189 smudpm_v4_5_i2ccontrollerthrottler_e = 7;
8190pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT:
8191 smudpm_v4_5_i2ccontrollerthrottler_e = 8;
8192pub type smudpm_v4_5_i2ccontrollerthrottler_e = ::core::ffi::c_uint;
8193pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0:
8194 smudpm_v4_5_i2ccontrollerprotocol_e = 0;
8195pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1:
8196 smudpm_v4_5_i2ccontrollerprotocol_e = 1;
8197pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0:
8198 smudpm_v4_5_i2ccontrollerprotocol_e = 2;
8199pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1:
8200 smudpm_v4_5_i2ccontrollerprotocol_e = 3;
8201pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0:
8202 smudpm_v4_5_i2ccontrollerprotocol_e = 4;
8203pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1:
8204 smudpm_v4_5_i2ccontrollerprotocol_e = 5;
8205pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT:
8206 smudpm_v4_5_i2ccontrollerprotocol_e = 6;
8207pub type smudpm_v4_5_i2ccontrollerprotocol_e = ::core::ffi::c_uint;
8208#[repr(C, packed)]
8209#[derive(Debug, Copy, Clone)]
8210pub struct smudpm_i2c_controller_config_v2 {
8211 pub Enabled: u8,
8212 pub Speed: u8,
8213 pub Padding: [u8; 2usize],
8214 pub SlaveAddress: u32,
8215 pub ControllerPort: u8,
8216 pub ControllerName: u8,
8217 pub ThermalThrotter: u8,
8218 pub I2cProtocol: u8,
8219}
8220#[repr(C, packed)]
8221#[derive(Debug, Copy, Clone)]
8222pub struct atom_smc_dpm_info_v4_5 {
8223 pub table_header: atom_common_table_header,
8224 pub I2cControllers: [smudpm_i2c_controller_config_v2; 8usize],
8225 pub MaxVoltageStepGfx: u16,
8226 pub MaxVoltageStepSoc: u16,
8227 pub VddGfxVrMapping: u8,
8228 pub VddSocVrMapping: u8,
8229 pub VddMem0VrMapping: u8,
8230 pub VddMem1VrMapping: u8,
8231 pub GfxUlvPhaseSheddingMask: u8,
8232 pub SocUlvPhaseSheddingMask: u8,
8233 pub ExternalSensorPresent: u8,
8234 pub Padding8_V: u8,
8235 pub GfxMaxCurrent: u16,
8236 pub GfxOffset: u8,
8237 pub Padding_TelemetryGfx: u8,
8238 pub SocMaxCurrent: u16,
8239 pub SocOffset: u8,
8240 pub Padding_TelemetrySoc: u8,
8241 pub Mem0MaxCurrent: u16,
8242 pub Mem0Offset: u8,
8243 pub Padding_TelemetryMem0: u8,
8244 pub Mem1MaxCurrent: u16,
8245 pub Mem1Offset: u8,
8246 pub Padding_TelemetryMem1: u8,
8247 pub AcDcGpio: u8,
8248 pub AcDcPolarity: u8,
8249 pub VR0HotGpio: u8,
8250 pub VR0HotPolarity: u8,
8251 pub VR1HotGpio: u8,
8252 pub VR1HotPolarity: u8,
8253 pub GthrGpio: u8,
8254 pub GthrPolarity: u8,
8255 pub LedPin0: u8,
8256 pub LedPin1: u8,
8257 pub LedPin2: u8,
8258 pub padding8_4: u8,
8259 pub PllGfxclkSpreadEnabled: u8,
8260 pub PllGfxclkSpreadPercent: u8,
8261 pub PllGfxclkSpreadFreq: u16,
8262 pub DfllGfxclkSpreadEnabled: u8,
8263 pub DfllGfxclkSpreadPercent: u8,
8264 pub DfllGfxclkSpreadFreq: u16,
8265 pub UclkSpreadEnabled: u8,
8266 pub UclkSpreadPercent: u8,
8267 pub UclkSpreadFreq: u16,
8268 pub SoclkSpreadEnabled: u8,
8269 pub SocclkSpreadPercent: u8,
8270 pub SocclkSpreadFreq: u16,
8271 pub TotalBoardPower: u16,
8272 pub BoardPadding: u16,
8273 pub MvddRatio: u32,
8274 pub BoardReserved: [u32; 9usize],
8275}
8276#[repr(C, packed)]
8277#[derive(Debug, Copy, Clone)]
8278pub struct atom_smc_dpm_info_v4_6 {
8279 pub table_header: atom_common_table_header,
8280 pub i2c_padding: [u32; 3usize],
8281 pub maxvoltagestepgfx: u16,
8282 pub maxvoltagestepsoc: u16,
8283 pub vddgfxvrmapping: u8,
8284 pub vddsocvrmapping: u8,
8285 pub vddmemvrmapping: u8,
8286 pub boardvrmapping: u8,
8287 pub gfxulvphasesheddingmask: u8,
8288 pub externalsensorpresent: u8,
8289 pub padding8_v: [u8; 2usize],
8290 pub gfxmaxcurrent: u16,
8291 pub gfxoffset: u8,
8292 pub padding_telemetrygfx: u8,
8293 pub socmaxcurrent: u16,
8294 pub socoffset: u8,
8295 pub padding_telemetrysoc: u8,
8296 pub memmaxcurrent: u16,
8297 pub memoffset: u8,
8298 pub padding_telemetrymem: u8,
8299 pub boardmaxcurrent: u16,
8300 pub boardoffset: u8,
8301 pub padding_telemetryboardinput: u8,
8302 pub vr0hotgpio: u8,
8303 pub vr0hotpolarity: u8,
8304 pub vr1hotgpio: u8,
8305 pub vr1hotpolarity: u8,
8306 pub pllgfxclkspreadenabled: u8,
8307 pub pllgfxclkspreadpercent: u8,
8308 pub pllgfxclkspreadfreq: u16,
8309 pub uclkspreadenabled: u8,
8310 pub uclkspreadpercent: u8,
8311 pub uclkspreadfreq: u16,
8312 pub fclkspreadenabled: u8,
8313 pub fclkspreadpercent: u8,
8314 pub fclkspreadfreq: u16,
8315 pub fllgfxclkspreadenabled: u8,
8316 pub fllgfxclkspreadpercent: u8,
8317 pub fllgfxclkspreadfreq: u16,
8318 pub i2ccontrollers: [smudpm_i2c_controller_config_v2; 8usize],
8319 pub memorychannelenabled: u32,
8320 pub drambitwidth: u8,
8321 pub paddingmem: [u8; 3usize],
8322 pub totalboardpower: u16,
8323 pub boardpadding: u16,
8324 pub xgmilinkspeed: [u8; 4usize],
8325 pub xgmilinkwidth: [u8; 4usize],
8326 pub xgmifclkfreq: [u16; 4usize],
8327 pub xgmisocvoltage: [u16; 4usize],
8328 pub boardreserved: [u32; 10usize],
8329}
8330#[repr(C, packed)]
8331#[derive(Debug, Copy, Clone)]
8332pub struct atom_smc_dpm_info_v4_7 {
8333 pub table_header: atom_common_table_header,
8334 pub I2cControllers: [smudpm_i2c_controller_config_v2; 8usize],
8335 pub MaxVoltageStepGfx: u16,
8336 pub MaxVoltageStepSoc: u16,
8337 pub VddGfxVrMapping: u8,
8338 pub VddSocVrMapping: u8,
8339 pub VddMem0VrMapping: u8,
8340 pub VddMem1VrMapping: u8,
8341 pub GfxUlvPhaseSheddingMask: u8,
8342 pub SocUlvPhaseSheddingMask: u8,
8343 pub ExternalSensorPresent: u8,
8344 pub Padding8_V: u8,
8345 pub GfxMaxCurrent: u16,
8346 pub GfxOffset: u8,
8347 pub Padding_TelemetryGfx: u8,
8348 pub SocMaxCurrent: u16,
8349 pub SocOffset: u8,
8350 pub Padding_TelemetrySoc: u8,
8351 pub Mem0MaxCurrent: u16,
8352 pub Mem0Offset: u8,
8353 pub Padding_TelemetryMem0: u8,
8354 pub Mem1MaxCurrent: u16,
8355 pub Mem1Offset: u8,
8356 pub Padding_TelemetryMem1: u8,
8357 pub AcDcGpio: u8,
8358 pub AcDcPolarity: u8,
8359 pub VR0HotGpio: u8,
8360 pub VR0HotPolarity: u8,
8361 pub VR1HotGpio: u8,
8362 pub VR1HotPolarity: u8,
8363 pub GthrGpio: u8,
8364 pub GthrPolarity: u8,
8365 pub LedPin0: u8,
8366 pub LedPin1: u8,
8367 pub LedPin2: u8,
8368 pub padding8_4: u8,
8369 pub PllGfxclkSpreadEnabled: u8,
8370 pub PllGfxclkSpreadPercent: u8,
8371 pub PllGfxclkSpreadFreq: u16,
8372 pub DfllGfxclkSpreadEnabled: u8,
8373 pub DfllGfxclkSpreadPercent: u8,
8374 pub DfllGfxclkSpreadFreq: u16,
8375 pub UclkSpreadEnabled: u8,
8376 pub UclkSpreadPercent: u8,
8377 pub UclkSpreadFreq: u16,
8378 pub SoclkSpreadEnabled: u8,
8379 pub SocclkSpreadPercent: u8,
8380 pub SocclkSpreadFreq: u16,
8381 pub TotalBoardPower: u16,
8382 pub BoardPadding: u16,
8383 pub MvddRatio: u32,
8384 pub GpioI2cScl: u8,
8385 pub GpioI2cSda: u8,
8386 pub GpioPadding: u16,
8387 pub LedPin3: u8,
8388 pub LedPin4: u8,
8389 pub LedEnableMask: u16,
8390 pub PowerLimitScalar: [u8; 4usize],
8391 pub MvddUlvPhaseSheddingMask: u8,
8392 pub VddciUlvPhaseSheddingMask: u8,
8393 pub Padding8_Psi1: u8,
8394 pub Padding8_Psi2: u8,
8395 pub BoardReserved: [u32; 5usize],
8396}
8397#[repr(C)]
8398#[derive(Debug, Copy, Clone)]
8399pub struct smudpm_i2c_controller_config_v3 {
8400 pub Enabled: u8,
8401 pub Speed: u8,
8402 pub SlaveAddress: u8,
8403 pub ControllerPort: u8,
8404 pub ControllerName: u8,
8405 pub ThermalThrotter: u8,
8406 pub I2cProtocol: u8,
8407 pub PaddingConfig: u8,
8408}
8409#[repr(C, packed)]
8410#[derive(Debug, Copy, Clone)]
8411pub struct atom_smc_dpm_info_v4_9 {
8412 pub table_header: atom_common_table_header,
8413 pub I2cControllers: [smudpm_i2c_controller_config_v3; 16usize],
8414 pub GpioScl: u8,
8415 pub GpioSda: u8,
8416 pub FchUsbPdSlaveAddr: u8,
8417 pub I2cSpare: u8,
8418 pub VddGfxVrMapping: u8,
8419 pub VddSocVrMapping: u8,
8420 pub VddMem0VrMapping: u8,
8421 pub VddMem1VrMapping: u8,
8422 pub GfxUlvPhaseSheddingMask: u8,
8423 pub SocUlvPhaseSheddingMask: u8,
8424 pub VddciUlvPhaseSheddingMask: u8,
8425 pub MvddUlvPhaseSheddingMask: u8,
8426 pub GfxMaxCurrent: u16,
8427 pub GfxOffset: u8,
8428 pub Padding_TelemetryGfx: u8,
8429 pub SocMaxCurrent: u16,
8430 pub SocOffset: u8,
8431 pub Padding_TelemetrySoc: u8,
8432 pub Mem0MaxCurrent: u16,
8433 pub Mem0Offset: u8,
8434 pub Padding_TelemetryMem0: u8,
8435 pub Mem1MaxCurrent: u16,
8436 pub Mem1Offset: u8,
8437 pub Padding_TelemetryMem1: u8,
8438 pub MvddRatio: u32,
8439 pub AcDcGpio: u8,
8440 pub AcDcPolarity: u8,
8441 pub VR0HotGpio: u8,
8442 pub VR0HotPolarity: u8,
8443 pub VR1HotGpio: u8,
8444 pub VR1HotPolarity: u8,
8445 pub GthrGpio: u8,
8446 pub GthrPolarity: u8,
8447 pub LedPin0: u8,
8448 pub LedPin1: u8,
8449 pub LedPin2: u8,
8450 pub LedEnableMask: u8,
8451 pub LedPcie: u8,
8452 pub LedError: u8,
8453 pub LedSpare1: [u8; 2usize],
8454 pub PllGfxclkSpreadEnabled: u8,
8455 pub PllGfxclkSpreadPercent: u8,
8456 pub PllGfxclkSpreadFreq: u16,
8457 pub DfllGfxclkSpreadEnabled: u8,
8458 pub DfllGfxclkSpreadPercent: u8,
8459 pub DfllGfxclkSpreadFreq: u16,
8460 pub UclkSpreadEnabled: u8,
8461 pub UclkSpreadPercent: u8,
8462 pub UclkSpreadFreq: u16,
8463 pub FclkSpreadEnabled: u8,
8464 pub FclkSpreadPercent: u8,
8465 pub FclkSpreadFreq: u16,
8466 pub MemoryChannelEnabled: u32,
8467 pub DramBitWidth: u8,
8468 pub PaddingMem1: [u8; 3usize],
8469 pub TotalBoardPower: u16,
8470 pub BoardPowerPadding: u16,
8471 pub XgmiLinkSpeed: [u8; 4usize],
8472 pub XgmiLinkWidth: [u8; 4usize],
8473 pub XgmiFclkFreq: [u16; 4usize],
8474 pub XgmiSocVoltage: [u16; 4usize],
8475 pub BoardReserved: [u32; 16usize],
8476}
8477#[repr(C, packed)]
8478#[derive(Debug, Copy, Clone)]
8479pub struct atom_smc_dpm_info_v4_10 {
8480 pub table_header: atom_common_table_header,
8481 pub GfxMaxCurrent: u16,
8482 pub GfxOffset: u8,
8483 pub Padding_TelemetryGfx: u8,
8484 pub SocMaxCurrent: u16,
8485 pub SocOffset: u8,
8486 pub Padding_TelemetrySoc: u8,
8487 pub MemMaxCurrent: u16,
8488 pub MemOffset: u8,
8489 pub Padding_TelemetryMem: u8,
8490 pub BoardMaxCurrent: u16,
8491 pub BoardOffset: u8,
8492 pub Padding_TelemetryBoardInput: u8,
8493 pub BoardVoltageCoeffA: u32,
8494 pub BoardVoltageCoeffB: u32,
8495 pub VR0HotGpio: u8,
8496 pub VR0HotPolarity: u8,
8497 pub VR1HotGpio: u8,
8498 pub VR1HotPolarity: u8,
8499 pub UclkSpreadEnabled: u8,
8500 pub UclkSpreadPercent: u8,
8501 pub UclkSpreadFreq: u16,
8502 pub FclkSpreadEnabled: u8,
8503 pub FclkSpreadPercent: u8,
8504 pub FclkSpreadFreq: u16,
8505 pub I2cControllers: [smudpm_i2c_controller_config_v3; 8usize],
8506 pub GpioI2cScl: u8,
8507 pub GpioI2cSda: u8,
8508 pub spare5: u16,
8509 pub reserved: [u32; 16usize],
8510}
8511#[repr(C, packed)]
8512#[derive(Debug, Copy, Clone)]
8513pub struct atom_asic_profiling_info_v4_1 {
8514 pub table_header: atom_common_table_header,
8515 pub maxvddc: u32,
8516 pub minvddc: u32,
8517 pub avfs_meannsigma_acontant0: u32,
8518 pub avfs_meannsigma_acontant1: u32,
8519 pub avfs_meannsigma_acontant2: u32,
8520 pub avfs_meannsigma_dc_tol_sigma: u16,
8521 pub avfs_meannsigma_platform_mean: u16,
8522 pub avfs_meannsigma_platform_sigma: u16,
8523 pub gb_vdroop_table_cksoff_a0: u32,
8524 pub gb_vdroop_table_cksoff_a1: u32,
8525 pub gb_vdroop_table_cksoff_a2: u32,
8526 pub gb_vdroop_table_ckson_a0: u32,
8527 pub gb_vdroop_table_ckson_a1: u32,
8528 pub gb_vdroop_table_ckson_a2: u32,
8529 pub avfsgb_fuse_table_cksoff_m1: u32,
8530 pub avfsgb_fuse_table_cksoff_m2: u32,
8531 pub avfsgb_fuse_table_cksoff_b: u32,
8532 pub avfsgb_fuse_table_ckson_m1: u32,
8533 pub avfsgb_fuse_table_ckson_m2: u32,
8534 pub avfsgb_fuse_table_ckson_b: u32,
8535 pub max_voltage_0_25mv: u16,
8536 pub enable_gb_vdroop_table_cksoff: u8,
8537 pub enable_gb_vdroop_table_ckson: u8,
8538 pub enable_gb_fuse_table_cksoff: u8,
8539 pub enable_gb_fuse_table_ckson: u8,
8540 pub psm_age_comfactor: u16,
8541 pub enable_apply_avfs_cksoff_voltage: u8,
8542 pub reserved: u8,
8543 pub dispclk2gfxclk_a: u32,
8544 pub dispclk2gfxclk_b: u32,
8545 pub dispclk2gfxclk_c: u32,
8546 pub pixclk2gfxclk_a: u32,
8547 pub pixclk2gfxclk_b: u32,
8548 pub pixclk2gfxclk_c: u32,
8549 pub dcefclk2gfxclk_a: u32,
8550 pub dcefclk2gfxclk_b: u32,
8551 pub dcefclk2gfxclk_c: u32,
8552 pub phyclk2gfxclk_a: u32,
8553 pub phyclk2gfxclk_b: u32,
8554 pub phyclk2gfxclk_c: u32,
8555}
8556#[repr(C, packed)]
8557#[derive(Debug, Copy, Clone)]
8558pub struct atom_asic_profiling_info_v4_2 {
8559 pub table_header: atom_common_table_header,
8560 pub maxvddc: u32,
8561 pub minvddc: u32,
8562 pub avfs_meannsigma_acontant0: u32,
8563 pub avfs_meannsigma_acontant1: u32,
8564 pub avfs_meannsigma_acontant2: u32,
8565 pub avfs_meannsigma_dc_tol_sigma: u16,
8566 pub avfs_meannsigma_platform_mean: u16,
8567 pub avfs_meannsigma_platform_sigma: u16,
8568 pub gb_vdroop_table_cksoff_a0: u32,
8569 pub gb_vdroop_table_cksoff_a1: u32,
8570 pub gb_vdroop_table_cksoff_a2: u32,
8571 pub gb_vdroop_table_ckson_a0: u32,
8572 pub gb_vdroop_table_ckson_a1: u32,
8573 pub gb_vdroop_table_ckson_a2: u32,
8574 pub avfsgb_fuse_table_cksoff_m1: u32,
8575 pub avfsgb_fuse_table_cksoff_m2: u32,
8576 pub avfsgb_fuse_table_cksoff_b: u32,
8577 pub avfsgb_fuse_table_ckson_m1: u32,
8578 pub avfsgb_fuse_table_ckson_m2: u32,
8579 pub avfsgb_fuse_table_ckson_b: u32,
8580 pub max_voltage_0_25mv: u16,
8581 pub enable_gb_vdroop_table_cksoff: u8,
8582 pub enable_gb_vdroop_table_ckson: u8,
8583 pub enable_gb_fuse_table_cksoff: u8,
8584 pub enable_gb_fuse_table_ckson: u8,
8585 pub psm_age_comfactor: u16,
8586 pub enable_apply_avfs_cksoff_voltage: u8,
8587 pub reserved: u8,
8588 pub dispclk2gfxclk_a: u32,
8589 pub dispclk2gfxclk_b: u32,
8590 pub dispclk2gfxclk_c: u32,
8591 pub pixclk2gfxclk_a: u32,
8592 pub pixclk2gfxclk_b: u32,
8593 pub pixclk2gfxclk_c: u32,
8594 pub dcefclk2gfxclk_a: u32,
8595 pub dcefclk2gfxclk_b: u32,
8596 pub dcefclk2gfxclk_c: u32,
8597 pub phyclk2gfxclk_a: u32,
8598 pub phyclk2gfxclk_b: u32,
8599 pub phyclk2gfxclk_c: u32,
8600 pub acg_gb_vdroop_table_a0: u32,
8601 pub acg_gb_vdroop_table_a1: u32,
8602 pub acg_gb_vdroop_table_a2: u32,
8603 pub acg_avfsgb_fuse_table_m1: u32,
8604 pub acg_avfsgb_fuse_table_m2: u32,
8605 pub acg_avfsgb_fuse_table_b: u32,
8606 pub enable_acg_gb_vdroop_table: u8,
8607 pub enable_acg_gb_fuse_table: u8,
8608 pub acg_dispclk2gfxclk_a: u32,
8609 pub acg_dispclk2gfxclk_b: u32,
8610 pub acg_dispclk2gfxclk_c: u32,
8611 pub acg_pixclk2gfxclk_a: u32,
8612 pub acg_pixclk2gfxclk_b: u32,
8613 pub acg_pixclk2gfxclk_c: u32,
8614 pub acg_dcefclk2gfxclk_a: u32,
8615 pub acg_dcefclk2gfxclk_b: u32,
8616 pub acg_dcefclk2gfxclk_c: u32,
8617 pub acg_phyclk2gfxclk_a: u32,
8618 pub acg_phyclk2gfxclk_b: u32,
8619 pub acg_phyclk2gfxclk_c: u32,
8620}
8621#[repr(C, packed)]
8622#[derive(Debug, Copy, Clone)]
8623pub struct atom_multimedia_info_v2_1 {
8624 pub table_header: atom_common_table_header,
8625 pub uvdip_min_ver: u8,
8626 pub uvdip_max_ver: u8,
8627 pub vceip_min_ver: u8,
8628 pub vceip_max_ver: u8,
8629 pub uvd_enc_max_input_width_pixels: u16,
8630 pub uvd_enc_max_input_height_pixels: u16,
8631 pub vce_enc_max_input_width_pixels: u16,
8632 pub vce_enc_max_input_height_pixels: u16,
8633 pub uvd_enc_max_bandwidth: u32,
8634 pub vce_enc_max_bandwidth: u32,
8635}
8636#[repr(C, packed)]
8637#[derive(Debug, Copy, Clone)]
8638pub struct atom_umc_info_v3_1 {
8639 pub table_header: atom_common_table_header,
8640 pub ucode_version: u32,
8641 pub ucode_rom_startaddr: u32,
8642 pub ucode_length: u32,
8643 pub umc_reg_init_offset: u16,
8644 pub customer_ucode_name_offset: u16,
8645 pub mclk_ss_percentage: u16,
8646 pub mclk_ss_rate_10hz: u16,
8647 pub umcip_min_ver: u8,
8648 pub umcip_max_ver: u8,
8649 pub vram_type: u8,
8650 pub umc_config: u8,
8651 pub mem_refclk_10khz: u32,
8652}
8653pub const atom_umc_config_def_UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE: atom_umc_config_def = 1;
8654pub const atom_umc_config_def_UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE: atom_umc_config_def = 2;
8655pub const atom_umc_config_def_UMC_CONFIG__ENABLE_HBM_LANE_REPAIR: atom_umc_config_def = 4;
8656pub const atom_umc_config_def_UMC_CONFIG__ENABLE_BANK_HARVESTING: atom_umc_config_def = 8;
8657pub const atom_umc_config_def_UMC_CONFIG__ENABLE_PHY_REINIT: atom_umc_config_def = 16;
8658pub const atom_umc_config_def_UMC_CONFIG__DISABLE_UCODE_CHKSTATUS: atom_umc_config_def = 32;
8659pub type atom_umc_config_def = ::core::ffi::c_uint;
8660#[repr(C, packed)]
8661#[derive(Debug, Copy, Clone)]
8662pub struct atom_umc_info_v3_2 {
8663 pub table_header: atom_common_table_header,
8664 pub ucode_version: u32,
8665 pub ucode_rom_startaddr: u32,
8666 pub ucode_length: u32,
8667 pub umc_reg_init_offset: u16,
8668 pub customer_ucode_name_offset: u16,
8669 pub mclk_ss_percentage: u16,
8670 pub mclk_ss_rate_10hz: u16,
8671 pub umcip_min_ver: u8,
8672 pub umcip_max_ver: u8,
8673 pub vram_type: u8,
8674 pub umc_config: u8,
8675 pub mem_refclk_10khz: u32,
8676 pub pstate_uclk_10khz: [u32; 4usize],
8677 pub umcgoldenoffset: u16,
8678 pub densitygoldenoffset: u16,
8679}
8680#[repr(C, packed)]
8681#[derive(Debug, Copy, Clone)]
8682pub struct atom_umc_info_v3_3 {
8683 pub table_header: atom_common_table_header,
8684 pub ucode_reserved: u32,
8685 pub ucode_rom_startaddr: u32,
8686 pub ucode_length: u32,
8687 pub umc_reg_init_offset: u16,
8688 pub customer_ucode_name_offset: u16,
8689 pub mclk_ss_percentage: u16,
8690 pub mclk_ss_rate_10hz: u16,
8691 pub umcip_min_ver: u8,
8692 pub umcip_max_ver: u8,
8693 pub vram_type: u8,
8694 pub umc_config: u8,
8695 pub mem_refclk_10khz: u32,
8696 pub pstate_uclk_10khz: [u32; 4usize],
8697 pub umcgoldenoffset: u16,
8698 pub densitygoldenoffset: u16,
8699 pub umc_config1: u32,
8700 pub bist_data_startaddr: u32,
8701 pub reserved: [u32; 2usize],
8702}
8703pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN: atom_umc_config1_def =
8704 1;
8705pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_AUTO_FRAMING: atom_umc_config1_def = 2;
8706pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA: atom_umc_config1_def = 4;
8707pub const atom_umc_config1_def_UMC_CONFIG1__DISABLE_STROBE_MODE: atom_umc_config1_def = 8;
8708pub const atom_umc_config1_def_UMC_CONFIG1__DEBUG_DATA_PARITY_EN: atom_umc_config1_def = 16;
8709pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_ECC_CAPABLE: atom_umc_config1_def = 65536;
8710pub type atom_umc_config1_def = ::core::ffi::c_uint;
8711#[repr(C, packed)]
8712#[derive(Debug, Copy, Clone)]
8713pub struct atom_umc_info_v4_0 {
8714 pub table_header: atom_common_table_header,
8715 pub ucode_reserved: [u32; 5usize],
8716 pub umcip_min_ver: u8,
8717 pub umcip_max_ver: u8,
8718 pub vram_type: u8,
8719 pub umc_config: u8,
8720 pub mem_refclk_10khz: u32,
8721 pub clk_reserved: [u32; 4usize],
8722 pub golden_reserved: u32,
8723 pub umc_config1: u32,
8724 pub reserved: [u32; 2usize],
8725 pub channel_num: u8,
8726 pub channel_width: u8,
8727 pub channel_reserve: [u8; 2usize],
8728 pub umc_info_reserved: [u8; 16usize],
8729}
8730#[repr(C, packed)]
8731#[derive(Debug, Copy, Clone)]
8732pub struct atom_vram_module_v9 {
8733 pub memory_size: u32,
8734 pub channel_enable: u32,
8735 pub max_mem_clk: u32,
8736 pub reserved: [u16; 3usize],
8737 pub mem_voltage: u16,
8738 pub vram_module_size: u16,
8739 pub ext_memory_id: u8,
8740 pub memory_type: u8,
8741 pub channel_num: u8,
8742 pub channel_width: u8,
8743 pub density: u8,
8744 pub tunningset_id: u8,
8745 pub vender_rev_id: u8,
8746 pub refreshrate: u8,
8747 pub hbm_ven_rev_id: u8,
8748 pub vram_rsd2: u8,
8749 pub dram_pnstring: [::core::ffi::c_char; 20usize],
8750}
8751#[repr(C, packed)]
8752#[derive(Debug, Copy, Clone)]
8753pub struct atom_vram_info_header_v2_3 {
8754 pub table_header: atom_common_table_header,
8755 pub mem_adjust_tbloffset: u16,
8756 pub mem_clk_patch_tbloffset: u16,
8757 pub mc_adjust_pertile_tbloffset: u16,
8758 pub mc_phyinit_tbloffset: u16,
8759 pub dram_data_remap_tbloffset: u16,
8760 pub tmrs_seq_offset: u16,
8761 pub post_ucode_init_offset: u16,
8762 pub vram_rsd2: u16,
8763 pub vram_module_num: u8,
8764 pub umcip_min_ver: u8,
8765 pub umcip_max_ver: u8,
8766 pub mc_phy_tile_num: u8,
8767 pub vram_module: [atom_vram_module_v9; 16usize],
8768}
8769#[repr(C, packed)]
8770#[derive(Debug, Copy, Clone)]
8771pub struct atom_vram_module_v3_0 {
8772 pub density: u8,
8773 pub tunningset_id: u8,
8774 pub ext_memory_id: u8,
8775 pub dram_vendor_id: u8,
8776 pub dram_info_offset: u16,
8777 pub mem_tuning_offset: u16,
8778 pub tmrs_seq_offset: u16,
8779 pub reserved1: u16,
8780 pub dram_size_per_ch: u32,
8781 pub reserved: [u32; 3usize],
8782 pub dram_pnstring: [::core::ffi::c_char; 40usize],
8783}
8784#[repr(C, packed)]
8785#[derive(Debug, Copy, Clone)]
8786pub struct atom_vram_info_header_v3_0 {
8787 pub table_header: atom_common_table_header,
8788 pub mem_tuning_table_offset: u16,
8789 pub dram_info_table_offset: u16,
8790 pub tmrs_table_offset: u16,
8791 pub mc_init_table_offset: u16,
8792 pub dram_data_remap_table_offset: u16,
8793 pub umc_emuinittable_offset: u16,
8794 pub reserved_sub_table_offset: [u16; 2usize],
8795 pub vram_module_num: u8,
8796 pub umcip_min_ver: u8,
8797 pub umcip_max_ver: u8,
8798 pub mc_phy_tile_num: u8,
8799 pub memory_type: u8,
8800 pub channel_num: u8,
8801 pub channel_width: u8,
8802 pub reserved1: u8,
8803 pub channel_enable: u32,
8804 pub channel1_enable: u32,
8805 pub feature_enable: u32,
8806 pub feature1_enable: u32,
8807 pub hardcode_mem_size: u32,
8808 pub reserved4: [u32; 4usize],
8809 pub vram_module: [atom_vram_module_v3_0; 8usize],
8810}
8811#[repr(C)]
8812#[derive(Debug, Copy, Clone)]
8813pub struct atom_umc_register_addr_info {
8814 pub _bitfield_align_1: [u8; 0],
8815 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8816}
8817impl atom_umc_register_addr_info {
8818 #[inline]
8819 pub fn umc_register_addr(&self) -> u32 {
8820 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8821 }
8822 #[inline]
8823 pub fn set_umc_register_addr(&mut self, val: u32) {
8824 unsafe {
8825 let val: u32 = ::core::mem::transmute(val);
8826 self._bitfield_1.set(0usize, 24u8, val as u64)
8827 }
8828 }
8829 #[inline]
8830 pub unsafe fn umc_register_addr_raw(this: *const Self) -> u32 {
8831 unsafe {
8832 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8833 ::core::ptr::addr_of!((*this)._bitfield_1),
8834 0usize,
8835 24u8,
8836 ) as u32)
8837 }
8838 }
8839 #[inline]
8840 pub unsafe fn set_umc_register_addr_raw(this: *mut Self, val: u32) {
8841 unsafe {
8842 let val: u32 = ::core::mem::transmute(val);
8843 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8844 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8845 0usize,
8846 24u8,
8847 val as u64,
8848 )
8849 }
8850 }
8851 #[inline]
8852 pub fn umc_reg_type_ind(&self) -> u32 {
8853 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
8854 }
8855 #[inline]
8856 pub fn set_umc_reg_type_ind(&mut self, val: u32) {
8857 unsafe {
8858 let val: u32 = ::core::mem::transmute(val);
8859 self._bitfield_1.set(24usize, 1u8, val as u64)
8860 }
8861 }
8862 #[inline]
8863 pub unsafe fn umc_reg_type_ind_raw(this: *const Self) -> u32 {
8864 unsafe {
8865 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8866 ::core::ptr::addr_of!((*this)._bitfield_1),
8867 24usize,
8868 1u8,
8869 ) as u32)
8870 }
8871 }
8872 #[inline]
8873 pub unsafe fn set_umc_reg_type_ind_raw(this: *mut Self, val: u32) {
8874 unsafe {
8875 let val: u32 = ::core::mem::transmute(val);
8876 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8877 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8878 24usize,
8879 1u8,
8880 val as u64,
8881 )
8882 }
8883 }
8884 #[inline]
8885 pub fn umc_reg_rsvd(&self) -> u32 {
8886 unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 7u8) as u32) }
8887 }
8888 #[inline]
8889 pub fn set_umc_reg_rsvd(&mut self, val: u32) {
8890 unsafe {
8891 let val: u32 = ::core::mem::transmute(val);
8892 self._bitfield_1.set(25usize, 7u8, val as u64)
8893 }
8894 }
8895 #[inline]
8896 pub unsafe fn umc_reg_rsvd_raw(this: *const Self) -> u32 {
8897 unsafe {
8898 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8899 ::core::ptr::addr_of!((*this)._bitfield_1),
8900 25usize,
8901 7u8,
8902 ) as u32)
8903 }
8904 }
8905 #[inline]
8906 pub unsafe fn set_umc_reg_rsvd_raw(this: *mut Self, val: u32) {
8907 unsafe {
8908 let val: u32 = ::core::mem::transmute(val);
8909 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8910 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8911 25usize,
8912 7u8,
8913 val as u64,
8914 )
8915 }
8916 }
8917 #[inline]
8918 pub fn new_bitfield_1(
8919 umc_register_addr: u32,
8920 umc_reg_type_ind: u32,
8921 umc_reg_rsvd: u32,
8922 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
8923 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
8924 __bindgen_bitfield_unit.set(0usize, 24u8, {
8925 let umc_register_addr: u32 = unsafe { ::core::mem::transmute(umc_register_addr) };
8926 umc_register_addr as u64
8927 });
8928 __bindgen_bitfield_unit.set(24usize, 1u8, {
8929 let umc_reg_type_ind: u32 = unsafe { ::core::mem::transmute(umc_reg_type_ind) };
8930 umc_reg_type_ind as u64
8931 });
8932 __bindgen_bitfield_unit.set(25usize, 7u8, {
8933 let umc_reg_rsvd: u32 = unsafe { ::core::mem::transmute(umc_reg_rsvd) };
8934 umc_reg_rsvd as u64
8935 });
8936 __bindgen_bitfield_unit
8937 }
8938}
8939pub const atom_umc_register_addr_info_flag_b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS:
8940 atom_umc_register_addr_info_flag = 1;
8941pub type atom_umc_register_addr_info_flag = ::core::ffi::c_uint;
8942#[repr(C, packed)]
8943#[derive(Copy, Clone)]
8944pub union atom_umc_register_addr_info_access {
8945 pub umc_reg_addr: atom_umc_register_addr_info,
8946 pub u32umc_reg_addr: u32,
8947}
8948#[repr(C)]
8949#[derive(Debug, Copy, Clone)]
8950pub struct atom_umc_reg_setting_id_config {
8951 pub _bitfield_align_1: [u8; 0],
8952 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8953}
8954impl atom_umc_reg_setting_id_config {
8955 #[inline]
8956 pub fn memclockrange(&self) -> u32 {
8957 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8958 }
8959 #[inline]
8960 pub fn set_memclockrange(&mut self, val: u32) {
8961 unsafe {
8962 let val: u32 = ::core::mem::transmute(val);
8963 self._bitfield_1.set(0usize, 24u8, val as u64)
8964 }
8965 }
8966 #[inline]
8967 pub unsafe fn memclockrange_raw(this: *const Self) -> u32 {
8968 unsafe {
8969 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8970 ::core::ptr::addr_of!((*this)._bitfield_1),
8971 0usize,
8972 24u8,
8973 ) as u32)
8974 }
8975 }
8976 #[inline]
8977 pub unsafe fn set_memclockrange_raw(this: *mut Self, val: u32) {
8978 unsafe {
8979 let val: u32 = ::core::mem::transmute(val);
8980 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8981 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8982 0usize,
8983 24u8,
8984 val as u64,
8985 )
8986 }
8987 }
8988 #[inline]
8989 pub fn mem_blk_id(&self) -> u32 {
8990 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
8991 }
8992 #[inline]
8993 pub fn set_mem_blk_id(&mut self, val: u32) {
8994 unsafe {
8995 let val: u32 = ::core::mem::transmute(val);
8996 self._bitfield_1.set(24usize, 8u8, val as u64)
8997 }
8998 }
8999 #[inline]
9000 pub unsafe fn mem_blk_id_raw(this: *const Self) -> u32 {
9001 unsafe {
9002 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9003 ::core::ptr::addr_of!((*this)._bitfield_1),
9004 24usize,
9005 8u8,
9006 ) as u32)
9007 }
9008 }
9009 #[inline]
9010 pub unsafe fn set_mem_blk_id_raw(this: *mut Self, val: u32) {
9011 unsafe {
9012 let val: u32 = ::core::mem::transmute(val);
9013 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9014 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9015 24usize,
9016 8u8,
9017 val as u64,
9018 )
9019 }
9020 }
9021 #[inline]
9022 pub fn new_bitfield_1(
9023 memclockrange: u32,
9024 mem_blk_id: u32,
9025 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9026 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9027 __bindgen_bitfield_unit.set(0usize, 24u8, {
9028 let memclockrange: u32 = unsafe { ::core::mem::transmute(memclockrange) };
9029 memclockrange as u64
9030 });
9031 __bindgen_bitfield_unit.set(24usize, 8u8, {
9032 let mem_blk_id: u32 = unsafe { ::core::mem::transmute(mem_blk_id) };
9033 mem_blk_id as u64
9034 });
9035 __bindgen_bitfield_unit
9036 }
9037}
9038#[repr(C, packed)]
9039#[derive(Copy, Clone)]
9040pub union atom_umc_reg_setting_id_config_access {
9041 pub umc_id_access: atom_umc_reg_setting_id_config,
9042 pub u32umc_id_access: u32,
9043}
9044#[repr(C, packed)]
9045#[derive(Copy, Clone)]
9046pub struct atom_umc_reg_setting_data_block {
9047 pub block_id: atom_umc_reg_setting_id_config_access,
9048 pub u32umc_reg_data: [u32; 1usize],
9049}
9050#[repr(C, packed)]
9051#[derive(Copy, Clone)]
9052pub struct atom_umc_init_reg_block {
9053 pub umc_reg_num: u16,
9054 pub reserved: u16,
9055 pub umc_reg_list: [atom_umc_register_addr_info_access; 1usize],
9056 pub umc_reg_setting_list: [atom_umc_reg_setting_data_block; 1usize],
9057}
9058#[repr(C, packed)]
9059#[derive(Debug, Copy, Clone)]
9060pub struct atom_vram_module_v10 {
9061 pub memory_size: u32,
9062 pub channel_enable: u32,
9063 pub max_mem_clk: u32,
9064 pub reserved: [u16; 3usize],
9065 pub mem_voltage: u16,
9066 pub vram_module_size: u16,
9067 pub ext_memory_id: u8,
9068 pub memory_type: u8,
9069 pub channel_num: u8,
9070 pub channel_width: u8,
9071 pub density: u8,
9072 pub tunningset_id: u8,
9073 pub vender_rev_id: u8,
9074 pub refreshrate: u8,
9075 pub vram_flags: u8,
9076 pub vram_rsd2: u8,
9077 pub gddr6_mr10: u16,
9078 pub gddr6_mr1: u16,
9079 pub gddr6_mr2: u16,
9080 pub gddr6_mr7: u16,
9081 pub dram_pnstring: [::core::ffi::c_char; 20usize],
9082}
9083#[repr(C, packed)]
9084#[derive(Debug, Copy, Clone)]
9085pub struct atom_vram_info_header_v2_4 {
9086 pub table_header: atom_common_table_header,
9087 pub mem_adjust_tbloffset: u16,
9088 pub mem_clk_patch_tbloffset: u16,
9089 pub mc_adjust_pertile_tbloffset: u16,
9090 pub mc_phyinit_tbloffset: u16,
9091 pub dram_data_remap_tbloffset: u16,
9092 pub reserved: u16,
9093 pub post_ucode_init_offset: u16,
9094 pub vram_rsd2: u16,
9095 pub vram_module_num: u8,
9096 pub umcip_min_ver: u8,
9097 pub umcip_max_ver: u8,
9098 pub mc_phy_tile_num: u8,
9099 pub vram_module: [atom_vram_module_v10; 16usize],
9100}
9101#[repr(C, packed)]
9102#[derive(Debug, Copy, Clone)]
9103pub struct atom_vram_module_v11 {
9104 pub memory_size: u32,
9105 pub channel_enable: u32,
9106 pub mem_voltage: u16,
9107 pub vram_module_size: u16,
9108 pub ext_memory_id: u8,
9109 pub memory_type: u8,
9110 pub channel_num: u8,
9111 pub channel_width: u8,
9112 pub density: u8,
9113 pub tunningset_id: u8,
9114 pub reserved: [u16; 4usize],
9115 pub vender_rev_id: u8,
9116 pub refreshrate: u8,
9117 pub vram_flags: u8,
9118 pub vram_rsd2: u8,
9119 pub gddr6_mr10: u16,
9120 pub gddr6_mr0: u16,
9121 pub gddr6_mr1: u16,
9122 pub gddr6_mr2: u16,
9123 pub gddr6_mr4: u16,
9124 pub gddr6_mr7: u16,
9125 pub gddr6_mr8: u16,
9126 pub dram_pnstring: [::core::ffi::c_char; 40usize],
9127}
9128#[repr(C, packed)]
9129#[derive(Debug, Copy, Clone)]
9130pub struct atom_gddr6_ac_timing_v2_5 {
9131 pub u32umc_id_access: u32,
9132 pub RL: u8,
9133 pub WL: u8,
9134 pub tRAS: u8,
9135 pub tRC: u8,
9136 pub tREFI: u16,
9137 pub tRFC: u8,
9138 pub tRFCpb: u8,
9139 pub tRREFD: u8,
9140 pub tRCDRD: u8,
9141 pub tRCDWR: u8,
9142 pub tRP: u8,
9143 pub tRRDS: u8,
9144 pub tRRDL: u8,
9145 pub tWR: u8,
9146 pub tWTRS: u8,
9147 pub tWTRL: u8,
9148 pub tFAW: u8,
9149 pub tCCDS: u8,
9150 pub tCCDL: u8,
9151 pub tCRCRL: u8,
9152 pub tCRCWL: u8,
9153 pub tCKE: u8,
9154 pub tCKSRE: u8,
9155 pub tCKSRX: u8,
9156 pub tRTPS: u8,
9157 pub tRTPL: u8,
9158 pub tMRD: u8,
9159 pub tMOD: u8,
9160 pub tXS: u8,
9161 pub tXHP: u8,
9162 pub tXSMRS: u8,
9163 pub tXSH: u32,
9164 pub tPD: u8,
9165 pub tXP: u8,
9166 pub tCPDED: u8,
9167 pub tACTPDE: u8,
9168 pub tPREPDE: u8,
9169 pub tREFPDE: u8,
9170 pub tMRSPDEN: u8,
9171 pub tRDSRE: u8,
9172 pub tWRSRE: u8,
9173 pub tPPD: u8,
9174 pub tCCDMW: u8,
9175 pub tWTRTR: u8,
9176 pub tLTLTR: u8,
9177 pub tREFTR: u8,
9178 pub VNDR: u8,
9179 pub reserved: [u8; 9usize],
9180}
9181#[repr(C, packed)]
9182#[derive(Debug, Copy, Clone)]
9183pub struct atom_gddr6_bit_byte_remap {
9184 pub dphy_byteremap: u32,
9185 pub dphy_bitremap0: u32,
9186 pub dphy_bitremap1: u32,
9187 pub dphy_bitremap2: u32,
9188 pub aphy_bitremap0: u32,
9189 pub aphy_bitremap1: u32,
9190 pub phy_dram: u32,
9191}
9192#[repr(C, packed)]
9193#[derive(Debug, Copy, Clone)]
9194pub struct atom_gddr6_dram_data_remap {
9195 pub table_size: u32,
9196 pub phyintf_ck_inverted: [u8; 8usize],
9197 pub bit_byte_remap: [atom_gddr6_bit_byte_remap; 16usize],
9198}
9199#[repr(C, packed)]
9200#[derive(Debug, Copy, Clone)]
9201pub struct atom_vram_info_header_v2_5 {
9202 pub table_header: atom_common_table_header,
9203 pub mem_adjust_tbloffset: u16,
9204 pub gddr6_ac_timing_offset: u16,
9205 pub mc_adjust_pertile_tbloffset: u16,
9206 pub mc_phyinit_tbloffset: u16,
9207 pub dram_data_remap_tbloffset: u16,
9208 pub reserved: u16,
9209 pub post_ucode_init_offset: u16,
9210 pub strobe_mode_patch_tbloffset: u16,
9211 pub vram_module_num: u8,
9212 pub umcip_min_ver: u8,
9213 pub umcip_max_ver: u8,
9214 pub mc_phy_tile_num: u8,
9215 pub vram_module: [atom_vram_module_v11; 16usize],
9216}
9217#[repr(C, packed)]
9218#[derive(Debug, Copy, Clone)]
9219pub struct atom_vram_info_header_v2_6 {
9220 pub table_header: atom_common_table_header,
9221 pub mem_adjust_tbloffset: u16,
9222 pub mem_clk_patch_tbloffset: u16,
9223 pub mc_adjust_pertile_tbloffset: u16,
9224 pub mc_phyinit_tbloffset: u16,
9225 pub dram_data_remap_tbloffset: u16,
9226 pub tmrs_seq_offset: u16,
9227 pub post_ucode_init_offset: u16,
9228 pub vram_rsd2: u16,
9229 pub vram_module_num: u8,
9230 pub umcip_min_ver: u8,
9231 pub umcip_max_ver: u8,
9232 pub mc_phy_tile_num: u8,
9233 pub vram_module: [atom_vram_module_v9; 16usize],
9234}
9235#[repr(C, packed)]
9236#[derive(Debug, Copy, Clone)]
9237pub struct atom_i2c_data_entry {
9238 pub i2c_reg_index: u16,
9239 pub i2c_reg_data: u16,
9240}
9241#[repr(C, packed)]
9242#[derive(Debug, Copy, Clone)]
9243pub struct atom_voltage_object_header_v4 {
9244 pub voltage_type: u8,
9245 pub voltage_mode: u8,
9246 pub object_size: u16,
9247}
9248pub const atom_voltage_object_mode_VOLTAGE_OBJ_GPIO_LUT: atom_voltage_object_mode = 0;
9249pub const atom_voltage_object_mode_VOLTAGE_OBJ_VR_I2C_INIT_SEQ: atom_voltage_object_mode = 3;
9250pub const atom_voltage_object_mode_VOLTAGE_OBJ_PHASE_LUT: atom_voltage_object_mode = 4;
9251pub const atom_voltage_object_mode_VOLTAGE_OBJ_SVID2: atom_voltage_object_mode = 7;
9252pub const atom_voltage_object_mode_VOLTAGE_OBJ_EVV: atom_voltage_object_mode = 8;
9253pub const atom_voltage_object_mode_VOLTAGE_OBJ_MERGED_POWER: atom_voltage_object_mode = 9;
9254pub type atom_voltage_object_mode = ::core::ffi::c_uint;
9255#[repr(C)]
9256#[derive(Debug, Copy, Clone)]
9257pub struct atom_i2c_voltage_object_v4 {
9258 pub header: atom_voltage_object_header_v4,
9259 pub regulator_id: u8,
9260 pub i2c_id: u8,
9261 pub i2c_slave_addr: u8,
9262 pub i2c_control_offset: u8,
9263 pub i2c_flag: u8,
9264 pub i2c_speed: u8,
9265 pub reserved: [u8; 2usize],
9266 pub i2cdatalut: [atom_i2c_data_entry; 1usize],
9267}
9268pub const atom_i2c_voltage_control_flag_VOLTAGE_DATA_ONE_BYTE: atom_i2c_voltage_control_flag = 0;
9269pub const atom_i2c_voltage_control_flag_VOLTAGE_DATA_TWO_BYTE: atom_i2c_voltage_control_flag = 1;
9270pub type atom_i2c_voltage_control_flag = ::core::ffi::c_uint;
9271#[repr(C, packed)]
9272#[derive(Debug, Copy, Clone)]
9273pub struct atom_voltage_gpio_map_lut {
9274 pub voltage_gpio_reg_val: u32,
9275 pub voltage_level_mv: u16,
9276}
9277#[repr(C, packed)]
9278#[derive(Debug, Copy, Clone)]
9279pub struct atom_gpio_voltage_object_v4 {
9280 pub header: atom_voltage_object_header_v4,
9281 pub gpio_control_id: u8,
9282 pub gpio_entry_num: u8,
9283 pub phase_delay_us: u8,
9284 pub reserved: u8,
9285 pub gpio_mask_val: u32,
9286 pub voltage_gpio_lut: [atom_voltage_gpio_map_lut; 1usize],
9287}
9288#[repr(C, packed)]
9289#[derive(Debug, Copy, Clone)]
9290pub struct atom_svid2_voltage_object_v4 {
9291 pub header: atom_voltage_object_header_v4,
9292 pub loadline_psi1: u8,
9293 pub psi0_l_vid_thresd: u8,
9294 pub psi0_enable: u8,
9295 pub maxvstep: u8,
9296 pub telemetry_offset: u8,
9297 pub telemetry_gain: u8,
9298 pub reserved1: u16,
9299}
9300#[repr(C)]
9301#[derive(Debug, Copy, Clone)]
9302pub struct atom_merged_voltage_object_v4 {
9303 pub header: atom_voltage_object_header_v4,
9304 pub merged_powerrail_type: u8,
9305 pub reserved: [u8; 3usize],
9306}
9307#[repr(C)]
9308#[derive(Copy, Clone)]
9309pub union atom_voltage_object_v4 {
9310 pub gpio_voltage_obj: atom_gpio_voltage_object_v4,
9311 pub i2c_voltage_obj: atom_i2c_voltage_object_v4,
9312 pub svid2_voltage_obj: atom_svid2_voltage_object_v4,
9313 pub merged_voltage_obj: atom_merged_voltage_object_v4,
9314}
9315#[repr(C)]
9316#[derive(Copy, Clone)]
9317pub struct atom_voltage_objects_info_v4_1 {
9318 pub table_header: atom_common_table_header,
9319 pub voltage_object: [atom_voltage_object_v4; 1usize],
9320}
9321#[repr(C)]
9322#[derive(Debug, Copy, Clone)]
9323pub struct asic_init_engine_parameters {
9324 pub _bitfield_align_1: [u8; 0],
9325 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9326}
9327impl asic_init_engine_parameters {
9328 #[inline]
9329 pub fn sclkfreqin10khz(&self) -> u32 {
9330 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9331 }
9332 #[inline]
9333 pub fn set_sclkfreqin10khz(&mut self, val: u32) {
9334 unsafe {
9335 let val: u32 = ::core::mem::transmute(val);
9336 self._bitfield_1.set(0usize, 24u8, val as u64)
9337 }
9338 }
9339 #[inline]
9340 pub unsafe fn sclkfreqin10khz_raw(this: *const Self) -> u32 {
9341 unsafe {
9342 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9343 ::core::ptr::addr_of!((*this)._bitfield_1),
9344 0usize,
9345 24u8,
9346 ) as u32)
9347 }
9348 }
9349 #[inline]
9350 pub unsafe fn set_sclkfreqin10khz_raw(this: *mut Self, val: u32) {
9351 unsafe {
9352 let val: u32 = ::core::mem::transmute(val);
9353 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9354 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9355 0usize,
9356 24u8,
9357 val as u64,
9358 )
9359 }
9360 }
9361 #[inline]
9362 pub fn engineflag(&self) -> u32 {
9363 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9364 }
9365 #[inline]
9366 pub fn set_engineflag(&mut self, val: u32) {
9367 unsafe {
9368 let val: u32 = ::core::mem::transmute(val);
9369 self._bitfield_1.set(24usize, 8u8, val as u64)
9370 }
9371 }
9372 #[inline]
9373 pub unsafe fn engineflag_raw(this: *const Self) -> u32 {
9374 unsafe {
9375 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9376 ::core::ptr::addr_of!((*this)._bitfield_1),
9377 24usize,
9378 8u8,
9379 ) as u32)
9380 }
9381 }
9382 #[inline]
9383 pub unsafe fn set_engineflag_raw(this: *mut Self, val: u32) {
9384 unsafe {
9385 let val: u32 = ::core::mem::transmute(val);
9386 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9387 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9388 24usize,
9389 8u8,
9390 val as u64,
9391 )
9392 }
9393 }
9394 #[inline]
9395 pub fn new_bitfield_1(
9396 sclkfreqin10khz: u32,
9397 engineflag: u32,
9398 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9399 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9400 __bindgen_bitfield_unit.set(0usize, 24u8, {
9401 let sclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(sclkfreqin10khz) };
9402 sclkfreqin10khz as u64
9403 });
9404 __bindgen_bitfield_unit.set(24usize, 8u8, {
9405 let engineflag: u32 = unsafe { ::core::mem::transmute(engineflag) };
9406 engineflag as u64
9407 });
9408 __bindgen_bitfield_unit
9409 }
9410}
9411#[repr(C)]
9412#[derive(Debug, Copy, Clone)]
9413pub struct asic_init_mem_parameters {
9414 pub _bitfield_align_1: [u8; 0],
9415 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9416}
9417impl asic_init_mem_parameters {
9418 #[inline]
9419 pub fn mclkfreqin10khz(&self) -> u32 {
9420 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9421 }
9422 #[inline]
9423 pub fn set_mclkfreqin10khz(&mut self, val: u32) {
9424 unsafe {
9425 let val: u32 = ::core::mem::transmute(val);
9426 self._bitfield_1.set(0usize, 24u8, val as u64)
9427 }
9428 }
9429 #[inline]
9430 pub unsafe fn mclkfreqin10khz_raw(this: *const Self) -> u32 {
9431 unsafe {
9432 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9433 ::core::ptr::addr_of!((*this)._bitfield_1),
9434 0usize,
9435 24u8,
9436 ) as u32)
9437 }
9438 }
9439 #[inline]
9440 pub unsafe fn set_mclkfreqin10khz_raw(this: *mut Self, val: u32) {
9441 unsafe {
9442 let val: u32 = ::core::mem::transmute(val);
9443 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9444 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9445 0usize,
9446 24u8,
9447 val as u64,
9448 )
9449 }
9450 }
9451 #[inline]
9452 pub fn memflag(&self) -> u32 {
9453 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9454 }
9455 #[inline]
9456 pub fn set_memflag(&mut self, val: u32) {
9457 unsafe {
9458 let val: u32 = ::core::mem::transmute(val);
9459 self._bitfield_1.set(24usize, 8u8, val as u64)
9460 }
9461 }
9462 #[inline]
9463 pub unsafe fn memflag_raw(this: *const Self) -> u32 {
9464 unsafe {
9465 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9466 ::core::ptr::addr_of!((*this)._bitfield_1),
9467 24usize,
9468 8u8,
9469 ) as u32)
9470 }
9471 }
9472 #[inline]
9473 pub unsafe fn set_memflag_raw(this: *mut Self, val: u32) {
9474 unsafe {
9475 let val: u32 = ::core::mem::transmute(val);
9476 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9477 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9478 24usize,
9479 8u8,
9480 val as u64,
9481 )
9482 }
9483 }
9484 #[inline]
9485 pub fn new_bitfield_1(
9486 mclkfreqin10khz: u32,
9487 memflag: u32,
9488 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9489 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9490 __bindgen_bitfield_unit.set(0usize, 24u8, {
9491 let mclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(mclkfreqin10khz) };
9492 mclkfreqin10khz as u64
9493 });
9494 __bindgen_bitfield_unit.set(24usize, 8u8, {
9495 let memflag: u32 = unsafe { ::core::mem::transmute(memflag) };
9496 memflag as u64
9497 });
9498 __bindgen_bitfield_unit
9499 }
9500}
9501#[repr(C)]
9502#[derive(Debug, Copy, Clone)]
9503pub struct asic_init_parameters_v2_1 {
9504 pub engineparam: asic_init_engine_parameters,
9505 pub memparam: asic_init_mem_parameters,
9506}
9507#[repr(C, packed)]
9508#[derive(Debug, Copy, Clone)]
9509pub struct asic_init_ps_allocation_v2_1 {
9510 pub param: asic_init_parameters_v2_1,
9511 pub reserved: [u32; 16usize],
9512}
9513pub const atom_asic_init_engine_flag_b3NORMAL_ENGINE_INIT: atom_asic_init_engine_flag = 0;
9514pub const atom_asic_init_engine_flag_b3SRIOV_SKIP_ASIC_INIT: atom_asic_init_engine_flag = 2;
9515pub const atom_asic_init_engine_flag_b3SRIOV_LOAD_UCODE: atom_asic_init_engine_flag = 64;
9516pub type atom_asic_init_engine_flag = ::core::ffi::c_uint;
9517pub const atom_asic_init_mem_flag_b3NORMAL_MEM_INIT: atom_asic_init_mem_flag = 0;
9518pub const atom_asic_init_mem_flag_b3DRAM_SELF_REFRESH_EXIT: atom_asic_init_mem_flag = 32;
9519pub type atom_asic_init_mem_flag = ::core::ffi::c_uint;
9520#[repr(C, packed)]
9521#[derive(Debug, Copy, Clone)]
9522pub struct set_engine_clock_parameters_v2_1 {
9523 pub _bitfield_align_1: [u8; 0],
9524 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9525 pub reserved: [u32; 10usize],
9526}
9527impl set_engine_clock_parameters_v2_1 {
9528 #[inline]
9529 pub fn sclkfreqin10khz(&self) -> u32 {
9530 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9531 }
9532 #[inline]
9533 pub fn set_sclkfreqin10khz(&mut self, val: u32) {
9534 unsafe {
9535 let val: u32 = ::core::mem::transmute(val);
9536 self._bitfield_1.set(0usize, 24u8, val as u64)
9537 }
9538 }
9539 #[inline]
9540 pub unsafe fn sclkfreqin10khz_raw(this: *const Self) -> u32 {
9541 unsafe {
9542 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9543 ::core::ptr::addr_of!((*this)._bitfield_1),
9544 0usize,
9545 24u8,
9546 ) as u32)
9547 }
9548 }
9549 #[inline]
9550 pub unsafe fn set_sclkfreqin10khz_raw(this: *mut Self, val: u32) {
9551 unsafe {
9552 let val: u32 = ::core::mem::transmute(val);
9553 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9554 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9555 0usize,
9556 24u8,
9557 val as u64,
9558 )
9559 }
9560 }
9561 #[inline]
9562 pub fn sclkflag(&self) -> u32 {
9563 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9564 }
9565 #[inline]
9566 pub fn set_sclkflag(&mut self, val: u32) {
9567 unsafe {
9568 let val: u32 = ::core::mem::transmute(val);
9569 self._bitfield_1.set(24usize, 8u8, val as u64)
9570 }
9571 }
9572 #[inline]
9573 pub unsafe fn sclkflag_raw(this: *const Self) -> u32 {
9574 unsafe {
9575 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9576 ::core::ptr::addr_of!((*this)._bitfield_1),
9577 24usize,
9578 8u8,
9579 ) as u32)
9580 }
9581 }
9582 #[inline]
9583 pub unsafe fn set_sclkflag_raw(this: *mut Self, val: u32) {
9584 unsafe {
9585 let val: u32 = ::core::mem::transmute(val);
9586 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9587 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9588 24usize,
9589 8u8,
9590 val as u64,
9591 )
9592 }
9593 }
9594 #[inline]
9595 pub fn new_bitfield_1(
9596 sclkfreqin10khz: u32,
9597 sclkflag: u32,
9598 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9599 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9600 __bindgen_bitfield_unit.set(0usize, 24u8, {
9601 let sclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(sclkfreqin10khz) };
9602 sclkfreqin10khz as u64
9603 });
9604 __bindgen_bitfield_unit.set(24usize, 8u8, {
9605 let sclkflag: u32 = unsafe { ::core::mem::transmute(sclkflag) };
9606 sclkflag as u64
9607 });
9608 __bindgen_bitfield_unit
9609 }
9610}
9611#[repr(C, packed)]
9612#[derive(Debug, Copy, Clone)]
9613pub struct set_engine_clock_ps_allocation_v2_1 {
9614 pub clockinfo: set_engine_clock_parameters_v2_1,
9615 pub reserved: [u32; 10usize],
9616}
9617pub const atom_set_engine_mem_clock_flag_b3NORMAL_CHANGE_CLOCK: atom_set_engine_mem_clock_flag = 0;
9618pub const atom_set_engine_mem_clock_flag_b3FIRST_TIME_CHANGE_CLOCK: atom_set_engine_mem_clock_flag =
9619 8;
9620pub const atom_set_engine_mem_clock_flag_b3STORE_DPM_TRAINGING: atom_set_engine_mem_clock_flag = 64;
9621pub type atom_set_engine_mem_clock_flag = ::core::ffi::c_uint;
9622#[repr(C, packed)]
9623#[derive(Debug, Copy, Clone)]
9624pub struct get_engine_clock_parameter {
9625 pub sclk_10khz: u32,
9626 pub reserved: u32,
9627}
9628#[repr(C, packed)]
9629#[derive(Debug, Copy, Clone)]
9630pub struct set_memory_clock_parameters_v2_1 {
9631 pub _bitfield_align_1: [u8; 0],
9632 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9633 pub reserved: [u32; 10usize],
9634}
9635impl set_memory_clock_parameters_v2_1 {
9636 #[inline]
9637 pub fn mclkfreqin10khz(&self) -> u32 {
9638 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9639 }
9640 #[inline]
9641 pub fn set_mclkfreqin10khz(&mut self, val: u32) {
9642 unsafe {
9643 let val: u32 = ::core::mem::transmute(val);
9644 self._bitfield_1.set(0usize, 24u8, val as u64)
9645 }
9646 }
9647 #[inline]
9648 pub unsafe fn mclkfreqin10khz_raw(this: *const Self) -> u32 {
9649 unsafe {
9650 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9651 ::core::ptr::addr_of!((*this)._bitfield_1),
9652 0usize,
9653 24u8,
9654 ) as u32)
9655 }
9656 }
9657 #[inline]
9658 pub unsafe fn set_mclkfreqin10khz_raw(this: *mut Self, val: u32) {
9659 unsafe {
9660 let val: u32 = ::core::mem::transmute(val);
9661 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9662 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9663 0usize,
9664 24u8,
9665 val as u64,
9666 )
9667 }
9668 }
9669 #[inline]
9670 pub fn mclkflag(&self) -> u32 {
9671 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9672 }
9673 #[inline]
9674 pub fn set_mclkflag(&mut self, val: u32) {
9675 unsafe {
9676 let val: u32 = ::core::mem::transmute(val);
9677 self._bitfield_1.set(24usize, 8u8, val as u64)
9678 }
9679 }
9680 #[inline]
9681 pub unsafe fn mclkflag_raw(this: *const Self) -> u32 {
9682 unsafe {
9683 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9684 ::core::ptr::addr_of!((*this)._bitfield_1),
9685 24usize,
9686 8u8,
9687 ) as u32)
9688 }
9689 }
9690 #[inline]
9691 pub unsafe fn set_mclkflag_raw(this: *mut Self, val: u32) {
9692 unsafe {
9693 let val: u32 = ::core::mem::transmute(val);
9694 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9695 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9696 24usize,
9697 8u8,
9698 val as u64,
9699 )
9700 }
9701 }
9702 #[inline]
9703 pub fn new_bitfield_1(
9704 mclkfreqin10khz: u32,
9705 mclkflag: u32,
9706 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9707 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9708 __bindgen_bitfield_unit.set(0usize, 24u8, {
9709 let mclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(mclkfreqin10khz) };
9710 mclkfreqin10khz as u64
9711 });
9712 __bindgen_bitfield_unit.set(24usize, 8u8, {
9713 let mclkflag: u32 = unsafe { ::core::mem::transmute(mclkflag) };
9714 mclkflag as u64
9715 });
9716 __bindgen_bitfield_unit
9717 }
9718}
9719#[repr(C, packed)]
9720#[derive(Debug, Copy, Clone)]
9721pub struct set_memory_clock_ps_allocation_v2_1 {
9722 pub clockinfo: set_memory_clock_parameters_v2_1,
9723 pub reserved: [u32; 10usize],
9724}
9725#[repr(C, packed)]
9726#[derive(Debug, Copy, Clone)]
9727pub struct get_memory_clock_parameter {
9728 pub mclk_10khz: u32,
9729 pub reserved: u32,
9730}
9731#[repr(C, packed)]
9732#[derive(Debug, Copy, Clone)]
9733pub struct set_voltage_parameters_v1_4 {
9734 pub voltagetype: u8,
9735 pub command: u8,
9736 pub vlevel_mv: u16,
9737}
9738pub const atom_set_voltage_command_ATOM_SET_VOLTAGE: atom_set_voltage_command = 0;
9739pub const atom_set_voltage_command_ATOM_INIT_VOLTAGE_REGULATOR: atom_set_voltage_command = 3;
9740pub const atom_set_voltage_command_ATOM_SET_VOLTAGE_PHASE: atom_set_voltage_command = 4;
9741pub const atom_set_voltage_command_ATOM_GET_LEAKAGE_ID: atom_set_voltage_command = 8;
9742pub type atom_set_voltage_command = ::core::ffi::c_uint;
9743#[repr(C, packed)]
9744#[derive(Debug, Copy, Clone)]
9745pub struct set_voltage_ps_allocation_v1_4 {
9746 pub setvoltageparam: set_voltage_parameters_v1_4,
9747 pub reserved: [u32; 10usize],
9748}
9749pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK: atom_gpu_clock_type = 0;
9750pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK: atom_gpu_clock_type = 1;
9751pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_UCLK: atom_gpu_clock_type = 2;
9752pub type atom_gpu_clock_type = ::core::ffi::c_uint;
9753#[repr(C, packed)]
9754#[derive(Debug, Copy, Clone)]
9755pub struct compute_gpu_clock_input_parameter_v1_8 {
9756 pub _bitfield_align_1: [u8; 0],
9757 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9758 pub reserved: [u32; 5usize],
9759}
9760impl compute_gpu_clock_input_parameter_v1_8 {
9761 #[inline]
9762 pub fn gpuclock_10khz(&self) -> u32 {
9763 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9764 }
9765 #[inline]
9766 pub fn set_gpuclock_10khz(&mut self, val: u32) {
9767 unsafe {
9768 let val: u32 = ::core::mem::transmute(val);
9769 self._bitfield_1.set(0usize, 24u8, val as u64)
9770 }
9771 }
9772 #[inline]
9773 pub unsafe fn gpuclock_10khz_raw(this: *const Self) -> u32 {
9774 unsafe {
9775 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9776 ::core::ptr::addr_of!((*this)._bitfield_1),
9777 0usize,
9778 24u8,
9779 ) as u32)
9780 }
9781 }
9782 #[inline]
9783 pub unsafe fn set_gpuclock_10khz_raw(this: *mut Self, val: u32) {
9784 unsafe {
9785 let val: u32 = ::core::mem::transmute(val);
9786 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9787 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9788 0usize,
9789 24u8,
9790 val as u64,
9791 )
9792 }
9793 }
9794 #[inline]
9795 pub fn gpu_clock_type(&self) -> u32 {
9796 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9797 }
9798 #[inline]
9799 pub fn set_gpu_clock_type(&mut self, val: u32) {
9800 unsafe {
9801 let val: u32 = ::core::mem::transmute(val);
9802 self._bitfield_1.set(24usize, 8u8, val as u64)
9803 }
9804 }
9805 #[inline]
9806 pub unsafe fn gpu_clock_type_raw(this: *const Self) -> u32 {
9807 unsafe {
9808 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9809 ::core::ptr::addr_of!((*this)._bitfield_1),
9810 24usize,
9811 8u8,
9812 ) as u32)
9813 }
9814 }
9815 #[inline]
9816 pub unsafe fn set_gpu_clock_type_raw(this: *mut Self, val: u32) {
9817 unsafe {
9818 let val: u32 = ::core::mem::transmute(val);
9819 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9820 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9821 24usize,
9822 8u8,
9823 val as u64,
9824 )
9825 }
9826 }
9827 #[inline]
9828 pub fn new_bitfield_1(
9829 gpuclock_10khz: u32,
9830 gpu_clock_type: u32,
9831 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9832 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9833 __bindgen_bitfield_unit.set(0usize, 24u8, {
9834 let gpuclock_10khz: u32 = unsafe { ::core::mem::transmute(gpuclock_10khz) };
9835 gpuclock_10khz as u64
9836 });
9837 __bindgen_bitfield_unit.set(24usize, 8u8, {
9838 let gpu_clock_type: u32 = unsafe { ::core::mem::transmute(gpu_clock_type) };
9839 gpu_clock_type as u64
9840 });
9841 __bindgen_bitfield_unit
9842 }
9843}
9844#[repr(C, packed)]
9845#[derive(Debug, Copy, Clone)]
9846pub struct compute_gpu_clock_output_parameter_v1_8 {
9847 pub _bitfield_align_1: [u8; 0],
9848 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9849 pub pll_fb_mult: u32,
9850 pub pll_ss_fbsmult: u32,
9851 pub pll_ss_slew_frac: u16,
9852 pub pll_ss_enable: u8,
9853 pub reserved: u8,
9854 pub reserved1: [u32; 2usize],
9855}
9856impl compute_gpu_clock_output_parameter_v1_8 {
9857 #[inline]
9858 pub fn gpuclock_10khz(&self) -> u32 {
9859 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9860 }
9861 #[inline]
9862 pub fn set_gpuclock_10khz(&mut self, val: u32) {
9863 unsafe {
9864 let val: u32 = ::core::mem::transmute(val);
9865 self._bitfield_1.set(0usize, 24u8, val as u64)
9866 }
9867 }
9868 #[inline]
9869 pub unsafe fn gpuclock_10khz_raw(this: *const Self) -> u32 {
9870 unsafe {
9871 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9872 ::core::ptr::addr_of!((*this)._bitfield_1),
9873 0usize,
9874 24u8,
9875 ) as u32)
9876 }
9877 }
9878 #[inline]
9879 pub unsafe fn set_gpuclock_10khz_raw(this: *mut Self, val: u32) {
9880 unsafe {
9881 let val: u32 = ::core::mem::transmute(val);
9882 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9883 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9884 0usize,
9885 24u8,
9886 val as u64,
9887 )
9888 }
9889 }
9890 #[inline]
9891 pub fn dfs_did(&self) -> u32 {
9892 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9893 }
9894 #[inline]
9895 pub fn set_dfs_did(&mut self, val: u32) {
9896 unsafe {
9897 let val: u32 = ::core::mem::transmute(val);
9898 self._bitfield_1.set(24usize, 8u8, val as u64)
9899 }
9900 }
9901 #[inline]
9902 pub unsafe fn dfs_did_raw(this: *const Self) -> u32 {
9903 unsafe {
9904 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9905 ::core::ptr::addr_of!((*this)._bitfield_1),
9906 24usize,
9907 8u8,
9908 ) as u32)
9909 }
9910 }
9911 #[inline]
9912 pub unsafe fn set_dfs_did_raw(this: *mut Self, val: u32) {
9913 unsafe {
9914 let val: u32 = ::core::mem::transmute(val);
9915 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9916 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9917 24usize,
9918 8u8,
9919 val as u64,
9920 )
9921 }
9922 }
9923 #[inline]
9924 pub fn new_bitfield_1(
9925 gpuclock_10khz: u32,
9926 dfs_did: u32,
9927 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9928 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9929 __bindgen_bitfield_unit.set(0usize, 24u8, {
9930 let gpuclock_10khz: u32 = unsafe { ::core::mem::transmute(gpuclock_10khz) };
9931 gpuclock_10khz as u64
9932 });
9933 __bindgen_bitfield_unit.set(24usize, 8u8, {
9934 let dfs_did: u32 = unsafe { ::core::mem::transmute(dfs_did) };
9935 dfs_did as u64
9936 });
9937 __bindgen_bitfield_unit
9938 }
9939}
9940#[repr(C, packed)]
9941#[derive(Debug, Copy, Clone)]
9942pub struct read_efuse_input_parameters_v3_1 {
9943 pub efuse_start_index: u16,
9944 pub reserved: u8,
9945 pub bitslen: u8,
9946}
9947#[repr(C, packed)]
9948#[derive(Copy, Clone)]
9949pub union read_efuse_value_parameters_v3_1 {
9950 pub efuse_info: read_efuse_input_parameters_v3_1,
9951 pub efusevalue: u32,
9952}
9953#[repr(C)]
9954#[derive(Debug, Copy, Clone)]
9955pub struct atom_get_smu_clock_info_parameters_v3_1 {
9956 pub syspll_id: u8,
9957 pub clk_id: u8,
9958 pub command: u8,
9959 pub dfsdid: u8,
9960}
9961pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ:
9962 atom_get_smu_clock_info_command = 0;
9963pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ:
9964 atom_get_smu_clock_info_command = 1;
9965pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ:
9966 atom_get_smu_clock_info_command = 2;
9967pub type atom_get_smu_clock_info_command = ::core::ffi::c_uint;
9968pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_SMNCLK_ID: atom_smu9_syspll0_clock_id = 0;
9969pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_SOCCLK_ID: atom_smu9_syspll0_clock_id = 1;
9970pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_MP0CLK_ID: atom_smu9_syspll0_clock_id = 2;
9971pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_MP1CLK_ID: atom_smu9_syspll0_clock_id = 3;
9972pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_LCLK_ID: atom_smu9_syspll0_clock_id = 4;
9973pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DCLK_ID: atom_smu9_syspll0_clock_id = 5;
9974pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_VCLK_ID: atom_smu9_syspll0_clock_id = 6;
9975pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_ECLK_ID: atom_smu9_syspll0_clock_id = 7;
9976pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DCEFCLK_ID: atom_smu9_syspll0_clock_id = 8;
9977pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DPREFCLK_ID: atom_smu9_syspll0_clock_id = 10;
9978pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DISPCLK_ID: atom_smu9_syspll0_clock_id = 11;
9979pub type atom_smu9_syspll0_clock_id = ::core::ffi::c_uint;
9980pub const atom_smu11_syspll_id_SMU11_SYSPLL0_ID: atom_smu11_syspll_id = 0;
9981pub const atom_smu11_syspll_id_SMU11_SYSPLL1_0_ID: atom_smu11_syspll_id = 1;
9982pub const atom_smu11_syspll_id_SMU11_SYSPLL1_1_ID: atom_smu11_syspll_id = 2;
9983pub const atom_smu11_syspll_id_SMU11_SYSPLL1_2_ID: atom_smu11_syspll_id = 3;
9984pub const atom_smu11_syspll_id_SMU11_SYSPLL2_ID: atom_smu11_syspll_id = 4;
9985pub const atom_smu11_syspll_id_SMU11_SYSPLL3_0_ID: atom_smu11_syspll_id = 5;
9986pub const atom_smu11_syspll_id_SMU11_SYSPLL3_1_ID: atom_smu11_syspll_id = 6;
9987pub type atom_smu11_syspll_id = ::core::ffi::c_uint;
9988pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_ECLK_ID: atom_smu11_syspll0_clock_id = 0;
9989pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_SOCCLK_ID: atom_smu11_syspll0_clock_id = 1;
9990pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_MP0CLK_ID: atom_smu11_syspll0_clock_id = 2;
9991pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_DCLK_ID: atom_smu11_syspll0_clock_id = 3;
9992pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_VCLK_ID: atom_smu11_syspll0_clock_id = 4;
9993pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_DCEFCLK_ID: atom_smu11_syspll0_clock_id = 5;
9994pub type atom_smu11_syspll0_clock_id = ::core::ffi::c_uint;
9995pub const atom_smu11_syspll1_0_clock_id_SMU11_SYSPLL1_0_UCLKA_ID: atom_smu11_syspll1_0_clock_id = 0;
9996pub type atom_smu11_syspll1_0_clock_id = ::core::ffi::c_uint;
9997pub const atom_smu11_syspll1_1_clock_id_SMU11_SYSPLL1_0_UCLKB_ID: atom_smu11_syspll1_1_clock_id = 0;
9998pub type atom_smu11_syspll1_1_clock_id = ::core::ffi::c_uint;
9999pub const atom_smu11_syspll1_2_clock_id_SMU11_SYSPLL1_0_FCLK_ID: atom_smu11_syspll1_2_clock_id = 0;
10000pub type atom_smu11_syspll1_2_clock_id = ::core::ffi::c_uint;
10001pub const atom_smu11_syspll2_clock_id_SMU11_SYSPLL2_GFXCLK_ID: atom_smu11_syspll2_clock_id = 0;
10002pub type atom_smu11_syspll2_clock_id = ::core::ffi::c_uint;
10003pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_WAFCLK_ID: atom_smu11_syspll3_0_clock_id =
10004 0;
10005pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_DISPCLK_ID: atom_smu11_syspll3_0_clock_id =
10006 1;
10007pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_DPREFCLK_ID: atom_smu11_syspll3_0_clock_id =
10008 2;
10009pub type atom_smu11_syspll3_0_clock_id = ::core::ffi::c_uint;
10010pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_MP1CLK_ID: atom_smu11_syspll3_1_clock_id =
10011 0;
10012pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_SMNCLK_ID: atom_smu11_syspll3_1_clock_id =
10013 1;
10014pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_LCLK_ID: atom_smu11_syspll3_1_clock_id = 2;
10015pub type atom_smu11_syspll3_1_clock_id = ::core::ffi::c_uint;
10016pub const atom_smu12_syspll_id_SMU12_SYSPLL0_ID: atom_smu12_syspll_id = 0;
10017pub const atom_smu12_syspll_id_SMU12_SYSPLL1_ID: atom_smu12_syspll_id = 1;
10018pub const atom_smu12_syspll_id_SMU12_SYSPLL2_ID: atom_smu12_syspll_id = 2;
10019pub const atom_smu12_syspll_id_SMU12_SYSPLL3_0_ID: atom_smu12_syspll_id = 3;
10020pub const atom_smu12_syspll_id_SMU12_SYSPLL3_1_ID: atom_smu12_syspll_id = 4;
10021pub type atom_smu12_syspll_id = ::core::ffi::c_uint;
10022pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SMNCLK_ID: atom_smu12_syspll0_clock_id = 0;
10023pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SOCCLK_ID: atom_smu12_syspll0_clock_id = 1;
10024pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP0CLK_ID: atom_smu12_syspll0_clock_id = 2;
10025pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP1CLK_ID: atom_smu12_syspll0_clock_id = 3;
10026pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP2CLK_ID: atom_smu12_syspll0_clock_id = 4;
10027pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_VCLK_ID: atom_smu12_syspll0_clock_id = 5;
10028pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_LCLK_ID: atom_smu12_syspll0_clock_id = 6;
10029pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_DCLK_ID: atom_smu12_syspll0_clock_id = 7;
10030pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_ACLK_ID: atom_smu12_syspll0_clock_id = 8;
10031pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_ISPCLK_ID: atom_smu12_syspll0_clock_id = 9;
10032pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SHUBCLK_ID: atom_smu12_syspll0_clock_id = 10;
10033pub type atom_smu12_syspll0_clock_id = ::core::ffi::c_uint;
10034pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DISPCLK_ID: atom_smu12_syspll1_clock_id = 0;
10035pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DPPCLK_ID: atom_smu12_syspll1_clock_id = 1;
10036pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DPREFCLK_ID: atom_smu12_syspll1_clock_id = 2;
10037pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DCFCLK_ID: atom_smu12_syspll1_clock_id = 3;
10038pub type atom_smu12_syspll1_clock_id = ::core::ffi::c_uint;
10039pub const atom_smu12_syspll2_clock_id_SMU12_SYSPLL2_Pre_GFXCLK_ID: atom_smu12_syspll2_clock_id = 0;
10040pub type atom_smu12_syspll2_clock_id = ::core::ffi::c_uint;
10041pub const atom_smu12_syspll3_0_clock_id_SMU12_SYSPLL3_0_FCLK_ID: atom_smu12_syspll3_0_clock_id = 0;
10042pub type atom_smu12_syspll3_0_clock_id = ::core::ffi::c_uint;
10043pub const atom_smu12_syspll3_1_clock_id_SMU12_SYSPLL3_1_UMCCLK_ID: atom_smu12_syspll3_1_clock_id =
10044 0;
10045pub type atom_smu12_syspll3_1_clock_id = ::core::ffi::c_uint;
10046#[repr(C)]
10047#[derive(Copy, Clone)]
10048pub struct atom_get_smu_clock_info_output_parameters_v3_1 {
10049 pub atom_smu_outputclkfreq: atom_get_smu_clock_info_output_parameters_v3_1__bindgen_ty_1,
10050}
10051#[repr(C, packed)]
10052#[derive(Copy, Clone)]
10053pub union atom_get_smu_clock_info_output_parameters_v3_1__bindgen_ty_1 {
10054 pub smu_clock_freq_hz: u32,
10055 pub syspllvcofreq_10khz: u32,
10056 pub sysspllrefclk_10khz: u32,
10057}
10058pub const atom_dynamic_memory_setting_command_COMPUTE_MEMORY_PLL_PARAM:
10059 atom_dynamic_memory_setting_command = 1;
10060pub const atom_dynamic_memory_setting_command_COMPUTE_ENGINE_PLL_PARAM:
10061 atom_dynamic_memory_setting_command = 2;
10062pub const atom_dynamic_memory_setting_command_ADJUST_MC_SETTING_PARAM:
10063 atom_dynamic_memory_setting_command = 3;
10064pub type atom_dynamic_memory_setting_command = ::core::ffi::c_uint;
10065#[repr(C, packed)]
10066#[derive(Debug, Copy, Clone)]
10067pub struct dynamic_mclk_settings_parameters_v2_1 {
10068 pub _bitfield_align_1: [u8; 0],
10069 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
10070 pub reserved: u32,
10071}
10072impl dynamic_mclk_settings_parameters_v2_1 {
10073 #[inline]
10074 pub fn mclk_10khz(&self) -> u32 {
10075 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
10076 }
10077 #[inline]
10078 pub fn set_mclk_10khz(&mut self, val: u32) {
10079 unsafe {
10080 let val: u32 = ::core::mem::transmute(val);
10081 self._bitfield_1.set(0usize, 24u8, val as u64)
10082 }
10083 }
10084 #[inline]
10085 pub unsafe fn mclk_10khz_raw(this: *const Self) -> u32 {
10086 unsafe {
10087 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
10088 ::core::ptr::addr_of!((*this)._bitfield_1),
10089 0usize,
10090 24u8,
10091 ) as u32)
10092 }
10093 }
10094 #[inline]
10095 pub unsafe fn set_mclk_10khz_raw(this: *mut Self, val: u32) {
10096 unsafe {
10097 let val: u32 = ::core::mem::transmute(val);
10098 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
10099 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
10100 0usize,
10101 24u8,
10102 val as u64,
10103 )
10104 }
10105 }
10106 #[inline]
10107 pub fn command(&self) -> u32 {
10108 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
10109 }
10110 #[inline]
10111 pub fn set_command(&mut self, val: u32) {
10112 unsafe {
10113 let val: u32 = ::core::mem::transmute(val);
10114 self._bitfield_1.set(24usize, 8u8, val as u64)
10115 }
10116 }
10117 #[inline]
10118 pub unsafe fn command_raw(this: *const Self) -> u32 {
10119 unsafe {
10120 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
10121 ::core::ptr::addr_of!((*this)._bitfield_1),
10122 24usize,
10123 8u8,
10124 ) as u32)
10125 }
10126 }
10127 #[inline]
10128 pub unsafe fn set_command_raw(this: *mut Self, val: u32) {
10129 unsafe {
10130 let val: u32 = ::core::mem::transmute(val);
10131 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
10132 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
10133 24usize,
10134 8u8,
10135 val as u64,
10136 )
10137 }
10138 }
10139 #[inline]
10140 pub fn new_bitfield_1(mclk_10khz: u32, command: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
10141 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
10142 __bindgen_bitfield_unit.set(0usize, 24u8, {
10143 let mclk_10khz: u32 = unsafe { ::core::mem::transmute(mclk_10khz) };
10144 mclk_10khz as u64
10145 });
10146 __bindgen_bitfield_unit.set(24usize, 8u8, {
10147 let command: u32 = unsafe { ::core::mem::transmute(command) };
10148 command as u64
10149 });
10150 __bindgen_bitfield_unit
10151 }
10152}
10153#[repr(C, packed)]
10154#[derive(Debug, Copy, Clone)]
10155pub struct dynamic_sclk_settings_parameters_v2_1 {
10156 pub _bitfield_align_1: [u8; 0],
10157 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
10158 pub mclk_10khz: u32,
10159 pub reserved: u32,
10160}
10161impl dynamic_sclk_settings_parameters_v2_1 {
10162 #[inline]
10163 pub fn sclk_10khz(&self) -> u32 {
10164 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
10165 }
10166 #[inline]
10167 pub fn set_sclk_10khz(&mut self, val: u32) {
10168 unsafe {
10169 let val: u32 = ::core::mem::transmute(val);
10170 self._bitfield_1.set(0usize, 24u8, val as u64)
10171 }
10172 }
10173 #[inline]
10174 pub unsafe fn sclk_10khz_raw(this: *const Self) -> u32 {
10175 unsafe {
10176 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
10177 ::core::ptr::addr_of!((*this)._bitfield_1),
10178 0usize,
10179 24u8,
10180 ) as u32)
10181 }
10182 }
10183 #[inline]
10184 pub unsafe fn set_sclk_10khz_raw(this: *mut Self, val: u32) {
10185 unsafe {
10186 let val: u32 = ::core::mem::transmute(val);
10187 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
10188 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
10189 0usize,
10190 24u8,
10191 val as u64,
10192 )
10193 }
10194 }
10195 #[inline]
10196 pub fn command(&self) -> u32 {
10197 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
10198 }
10199 #[inline]
10200 pub fn set_command(&mut self, val: u32) {
10201 unsafe {
10202 let val: u32 = ::core::mem::transmute(val);
10203 self._bitfield_1.set(24usize, 8u8, val as u64)
10204 }
10205 }
10206 #[inline]
10207 pub unsafe fn command_raw(this: *const Self) -> u32 {
10208 unsafe {
10209 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
10210 ::core::ptr::addr_of!((*this)._bitfield_1),
10211 24usize,
10212 8u8,
10213 ) as u32)
10214 }
10215 }
10216 #[inline]
10217 pub unsafe fn set_command_raw(this: *mut Self, val: u32) {
10218 unsafe {
10219 let val: u32 = ::core::mem::transmute(val);
10220 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
10221 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
10222 24usize,
10223 8u8,
10224 val as u64,
10225 )
10226 }
10227 }
10228 #[inline]
10229 pub fn new_bitfield_1(sclk_10khz: u32, command: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
10230 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
10231 __bindgen_bitfield_unit.set(0usize, 24u8, {
10232 let sclk_10khz: u32 = unsafe { ::core::mem::transmute(sclk_10khz) };
10233 sclk_10khz as u64
10234 });
10235 __bindgen_bitfield_unit.set(24usize, 8u8, {
10236 let command: u32 = unsafe { ::core::mem::transmute(command) };
10237 command as u64
10238 });
10239 __bindgen_bitfield_unit
10240 }
10241}
10242#[repr(C)]
10243#[derive(Copy, Clone)]
10244pub union dynamic_memory_settings_parameters_v2_1 {
10245 pub mclk_setting: dynamic_mclk_settings_parameters_v2_1,
10246 pub sclk_setting: dynamic_sclk_settings_parameters_v2_1,
10247}
10248pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_REINIT:
10249 atom_umc6_0_ucode_function_call_enum_id = 0;
10250pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH:
10251 atom_umc6_0_ucode_function_call_enum_id = 1;
10252pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH:
10253 atom_umc6_0_ucode_function_call_enum_id = 2;
10254pub type atom_umc6_0_ucode_function_call_enum_id = ::core::ffi::c_uint;
10255#[repr(C, packed)]
10256#[derive(Debug, Copy, Clone)]
10257pub struct memory_training_parameters_v2_1 {
10258 pub ucode_func_id: u8,
10259 pub ucode_reserved: [u8; 3usize],
10260 pub reserved: [u32; 5usize],
10261}
10262#[repr(C, packed)]
10263#[derive(Debug, Copy, Clone)]
10264pub struct set_pixel_clock_parameter_v1_7 {
10265 pub pixclk_100hz: u32,
10266 pub pll_id: u8,
10267 pub encoderobjid: u8,
10268 pub encoder_mode: u8,
10269 pub miscinfo: u8,
10270 pub crtc_id: u8,
10271 pub deep_color_ratio: u8,
10272 pub reserved1: [u8; 2usize],
10273 pub reserved2: u32,
10274}
10275pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL:
10276 atom_set_pixel_clock_v1_7_misc_info = 1;
10277pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_PROG_PHYPLL:
10278 atom_set_pixel_clock_v1_7_misc_info = 2;
10279pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_YUV420_MODE:
10280 atom_set_pixel_clock_v1_7_misc_info = 4;
10281pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN:
10282 atom_set_pixel_clock_v1_7_misc_info = 8;
10283pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC:
10284 atom_set_pixel_clock_v1_7_misc_info = 48;
10285pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN:
10286 atom_set_pixel_clock_v1_7_misc_info = 0;
10287pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE:
10288 atom_set_pixel_clock_v1_7_misc_info = 16;
10289pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK:
10290 atom_set_pixel_clock_v1_7_misc_info = 32;
10291pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD:
10292 atom_set_pixel_clock_v1_7_misc_info = 48;
10293pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE:
10294 atom_set_pixel_clock_v1_7_misc_info = 64;
10295pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS:
10296 atom_set_pixel_clock_v1_7_misc_info = 128;
10297pub type atom_set_pixel_clock_v1_7_misc_info = ::core::ffi::c_uint;
10298pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS:
10299 atom_set_pixel_clock_v1_7_deepcolor_ratio = 0;
10300pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4:
10301 atom_set_pixel_clock_v1_7_deepcolor_ratio = 1;
10302pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2:
10303 atom_set_pixel_clock_v1_7_deepcolor_ratio = 2;
10304pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1:
10305 atom_set_pixel_clock_v1_7_deepcolor_ratio = 3;
10306pub type atom_set_pixel_clock_v1_7_deepcolor_ratio = ::core::ffi::c_uint;
10307#[repr(C, packed)]
10308#[derive(Debug, Copy, Clone)]
10309pub struct set_dce_clock_parameters_v2_1 {
10310 pub dceclk_10khz: u32,
10311 pub dceclktype: u8,
10312 pub dceclksrc: u8,
10313 pub dceclkflag: u8,
10314 pub crtc_id: u8,
10315}
10316pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_DISPCLK: atom_set_dce_clock_clock_type = 0;
10317pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_DPREFCLK: atom_set_dce_clock_clock_type = 1;
10318pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_PIXELCLK: atom_set_dce_clock_clock_type = 2;
10319pub type atom_set_dce_clock_clock_type = ::core::ffi::c_uint;
10320pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK:
10321 atom_set_dce_clock_dprefclk_flag = 3;
10322pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA:
10323 atom_set_dce_clock_dprefclk_flag = 0;
10324pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK:
10325 atom_set_dce_clock_dprefclk_flag = 1;
10326pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE:
10327 atom_set_dce_clock_dprefclk_flag = 2;
10328pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN:
10329 atom_set_dce_clock_dprefclk_flag = 3;
10330pub type atom_set_dce_clock_dprefclk_flag = ::core::ffi::c_uint;
10331pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK:
10332 atom_set_dce_clock_pixclk_flag = 3;
10333pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS:
10334 atom_set_dce_clock_pixclk_flag = 0;
10335pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4:
10336 atom_set_dce_clock_pixclk_flag = 1;
10337pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2:
10338 atom_set_dce_clock_pixclk_flag = 2;
10339pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1:
10340 atom_set_dce_clock_pixclk_flag = 3;
10341pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE:
10342 atom_set_dce_clock_pixclk_flag = 4;
10343pub type atom_set_dce_clock_pixclk_flag = ::core::ffi::c_uint;
10344#[repr(C, packed)]
10345#[derive(Debug, Copy, Clone)]
10346pub struct set_dce_clock_ps_allocation_v2_1 {
10347 pub param: set_dce_clock_parameters_v2_1,
10348 pub ulReserved: [u32; 2usize],
10349}
10350#[repr(C, packed)]
10351#[derive(Debug, Copy, Clone)]
10352pub struct blank_crtc_parameters {
10353 pub crtc_id: u8,
10354 pub blanking: u8,
10355 pub reserved: u16,
10356 pub reserved1: u32,
10357}
10358pub const atom_blank_crtc_command_ATOM_BLANKING: atom_blank_crtc_command = 1;
10359pub const atom_blank_crtc_command_ATOM_BLANKING_OFF: atom_blank_crtc_command = 0;
10360pub type atom_blank_crtc_command = ::core::ffi::c_uint;
10361#[repr(C)]
10362#[derive(Debug, Copy, Clone)]
10363pub struct enable_crtc_parameters {
10364 pub crtc_id: u8,
10365 pub enable: u8,
10366 pub padding: [u8; 2usize],
10367}
10368#[repr(C)]
10369#[derive(Debug, Copy, Clone)]
10370pub struct enable_disp_power_gating_parameters_v2_1 {
10371 pub disp_pipe_id: u8,
10372 pub enable: u8,
10373 pub padding: [u8; 2usize],
10374}
10375#[repr(C, packed)]
10376#[derive(Debug, Copy, Clone)]
10377pub struct enable_disp_power_gating_ps_allocation {
10378 pub param: enable_disp_power_gating_parameters_v2_1,
10379 pub ulReserved: [u32; 4usize],
10380}
10381#[repr(C, packed)]
10382#[derive(Debug, Copy, Clone)]
10383pub struct set_crtc_using_dtd_timing_parameters {
10384 pub h_size: u16,
10385 pub h_blanking_time: u16,
10386 pub v_size: u16,
10387 pub v_blanking_time: u16,
10388 pub h_syncoffset: u16,
10389 pub h_syncwidth: u16,
10390 pub v_syncoffset: u16,
10391 pub v_syncwidth: u16,
10392 pub modemiscinfo: u16,
10393 pub h_border: u8,
10394 pub v_border: u8,
10395 pub crtc_id: u8,
10396 pub encoder_mode: u8,
10397 pub padding: [u8; 2usize],
10398}
10399#[repr(C, packed)]
10400#[derive(Copy, Clone)]
10401pub struct process_i2c_channel_transaction_parameters {
10402 pub i2cspeed_khz: u8,
10403 pub regind_status: process_i2c_channel_transaction_parameters__bindgen_ty_1,
10404 pub i2c_data_out: u16,
10405 pub flag: u8,
10406 pub trans_bytes: u8,
10407 pub slave_addr: u8,
10408 pub i2c_id: u8,
10409}
10410#[repr(C)]
10411#[derive(Copy, Clone)]
10412pub union process_i2c_channel_transaction_parameters__bindgen_ty_1 {
10413 pub regindex: u8,
10414 pub status: u8,
10415}
10416pub const atom_process_i2c_flag_HW_I2C_WRITE: atom_process_i2c_flag = 1;
10417pub const atom_process_i2c_flag_HW_I2C_READ: atom_process_i2c_flag = 0;
10418pub const atom_process_i2c_flag_I2C_2BYTE_ADDR: atom_process_i2c_flag = 2;
10419pub const atom_process_i2c_flag_HW_I2C_SMBUS_BYTE_WR: atom_process_i2c_flag = 4;
10420pub type atom_process_i2c_flag = ::core::ffi::c_uint;
10421pub const atom_process_i2c_status_HW_ASSISTED_I2C_STATUS_FAILURE: atom_process_i2c_status = 2;
10422pub const atom_process_i2c_status_HW_ASSISTED_I2C_STATUS_SUCCESS: atom_process_i2c_status = 1;
10423pub type atom_process_i2c_status = ::core::ffi::c_uint;
10424#[repr(C, packed)]
10425#[derive(Copy, Clone)]
10426pub struct process_aux_channel_transaction_parameters_v1_2 {
10427 pub aux_request: u16,
10428 pub dataout: u16,
10429 pub channelid: u8,
10430 pub aux_status_delay: process_aux_channel_transaction_parameters_v1_2__bindgen_ty_1,
10431 pub dataout_len: u8,
10432 pub hpd_id: u8,
10433}
10434#[repr(C)]
10435#[derive(Copy, Clone)]
10436pub union process_aux_channel_transaction_parameters_v1_2__bindgen_ty_1 {
10437 pub reply_status: u8,
10438 pub aux_delay: u8,
10439}
10440#[repr(C)]
10441#[derive(Debug, Copy, Clone)]
10442pub struct select_crtc_source_parameters_v2_3 {
10443 pub crtc_id: u8,
10444 pub encoder_id: u8,
10445 pub encode_mode: u8,
10446 pub dst_bpc: u8,
10447}
10448pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DISABLE_DIG:
10449 atom_dig_encoder_control_action = 0;
10450pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_ENABLE_DIG:
10451 atom_dig_encoder_control_action = 1;
10452pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_START:
10453 atom_dig_encoder_control_action = 8;
10454pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1:
10455 atom_dig_encoder_control_action = 9;
10456pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2:
10457 atom_dig_encoder_control_action = 10;
10458pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3:
10459 atom_dig_encoder_control_action = 19;
10460pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE:
10461 atom_dig_encoder_control_action = 11;
10462pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_VIDEO_OFF:
10463 atom_dig_encoder_control_action = 12;
10464pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_VIDEO_ON:
10465 atom_dig_encoder_control_action = 13;
10466pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_SETUP_PANEL_MODE:
10467 atom_dig_encoder_control_action = 16;
10468pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4:
10469 atom_dig_encoder_control_action = 20;
10470pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_STREAM_SETUP:
10471 atom_dig_encoder_control_action = 15;
10472pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_LINK_SETUP:
10473 atom_dig_encoder_control_action = 17;
10474pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_ENCODER_BLANK:
10475 atom_dig_encoder_control_action = 18;
10476pub type atom_dig_encoder_control_action = ::core::ffi::c_uint;
10477pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_DISABLE:
10478 atom_dig_encoder_control_panelmode = 0;
10479pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_ENABLE_eDP_MODE:
10480 atom_dig_encoder_control_panelmode = 1;
10481pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_ENABLE_LVLINK_MODE:
10482 atom_dig_encoder_control_panelmode = 17;
10483pub type atom_dig_encoder_control_panelmode = ::core::ffi::c_uint;
10484pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER:
10485 atom_dig_encoder_control_v5_digid = 0;
10486pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER:
10487 atom_dig_encoder_control_v5_digid = 1;
10488pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER:
10489 atom_dig_encoder_control_v5_digid = 2;
10490pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER:
10491 atom_dig_encoder_control_v5_digid = 3;
10492pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER:
10493 atom_dig_encoder_control_v5_digid = 4;
10494pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER:
10495 atom_dig_encoder_control_v5_digid = 5;
10496pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER:
10497 atom_dig_encoder_control_v5_digid = 6;
10498pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER:
10499 atom_dig_encoder_control_v5_digid = 7;
10500pub type atom_dig_encoder_control_v5_digid = ::core::ffi::c_uint;
10501#[repr(C, packed)]
10502#[derive(Debug, Copy, Clone)]
10503pub struct dig_encoder_stream_setup_parameters_v1_5 {
10504 pub digid: u8,
10505 pub action: u8,
10506 pub digmode: u8,
10507 pub lanenum: u8,
10508 pub pclk_10khz: u32,
10509 pub bitpercolor: u8,
10510 pub dplinkrate_270mhz: u8,
10511 pub reserved: [u8; 2usize],
10512}
10513#[repr(C)]
10514#[derive(Debug, Copy, Clone)]
10515pub struct dig_encoder_link_setup_parameters_v1_5 {
10516 pub digid: u8,
10517 pub action: u8,
10518 pub digmode: u8,
10519 pub lanenum: u8,
10520 pub symclk_10khz: u8,
10521 pub hpd_sel: u8,
10522 pub digfe_sel: u8,
10523 pub reserved: [u8; 2usize],
10524}
10525#[repr(C, packed)]
10526#[derive(Debug, Copy, Clone)]
10527pub struct dp_panel_mode_set_parameters_v1_5 {
10528 pub digid: u8,
10529 pub action: u8,
10530 pub panelmode: u8,
10531 pub reserved1: u8,
10532 pub reserved2: [u32; 2usize],
10533}
10534#[repr(C, packed)]
10535#[derive(Debug, Copy, Clone)]
10536pub struct dig_encoder_generic_cmd_parameters_v1_5 {
10537 pub digid: u8,
10538 pub action: u8,
10539 pub reserved1: [u8; 2usize],
10540 pub reserved2: [u32; 2usize],
10541}
10542#[repr(C)]
10543#[derive(Copy, Clone)]
10544pub union dig_encoder_control_parameters_v1_5 {
10545 pub cmd_param: dig_encoder_generic_cmd_parameters_v1_5,
10546 pub stream_param: dig_encoder_stream_setup_parameters_v1_5,
10547 pub link_param: dig_encoder_link_setup_parameters_v1_5,
10548 pub dppanel_param: dp_panel_mode_set_parameters_v1_5,
10549}
10550#[repr(C, packed)]
10551#[derive(Copy, Clone)]
10552pub struct dig_transmitter_control_parameters_v1_6 {
10553 pub phyid: u8,
10554 pub action: u8,
10555 pub mode_laneset: dig_transmitter_control_parameters_v1_6__bindgen_ty_1,
10556 pub lanenum: u8,
10557 pub symclk_10khz: u32,
10558 pub hpdsel: u8,
10559 pub digfe_sel: u8,
10560 pub connobj_id: u8,
10561 pub reserved: u8,
10562 pub reserved1: u32,
10563}
10564#[repr(C)]
10565#[derive(Copy, Clone)]
10566pub union dig_transmitter_control_parameters_v1_6__bindgen_ty_1 {
10567 pub digmode: u8,
10568 pub dplaneset: u8,
10569}
10570#[repr(C, packed)]
10571#[derive(Copy, Clone)]
10572pub struct dig_transmitter_control_ps_allocation_v1_6 {
10573 pub param: dig_transmitter_control_parameters_v1_6,
10574 pub reserved: [u32; 4usize],
10575}
10576pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_DISABLE:
10577 atom_dig_transmitter_control_action = 0;
10578pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_ENABLE:
10579 atom_dig_transmitter_control_action = 1;
10580pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_BLOFF:
10581 atom_dig_transmitter_control_action = 2;
10582pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_BLON:
10583 atom_dig_transmitter_control_action = 3;
10584pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL:
10585 atom_dig_transmitter_control_action = 4;
10586pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START:
10587 atom_dig_transmitter_control_action = 5;
10588pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP:
10589 atom_dig_transmitter_control_action = 6;
10590pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_INIT:
10591 atom_dig_transmitter_control_action = 7;
10592pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT:
10593 atom_dig_transmitter_control_action = 8;
10594pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT:
10595 atom_dig_transmitter_control_action = 9;
10596pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_SETUP:
10597 atom_dig_transmitter_control_action = 10;
10598pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH:
10599 atom_dig_transmitter_control_action = 11;
10600pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_POWER_ON:
10601 atom_dig_transmitter_control_action = 12;
10602pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_POWER_OFF:
10603 atom_dig_transmitter_control_action = 13;
10604pub type atom_dig_transmitter_control_action = ::core::ffi::c_uint;
10605pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGA_SEL:
10606 atom_dig_transmitter_control_digfe_sel = 1;
10607pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGB_SEL:
10608 atom_dig_transmitter_control_digfe_sel = 2;
10609pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGC_SEL:
10610 atom_dig_transmitter_control_digfe_sel = 4;
10611pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGD_SEL:
10612 atom_dig_transmitter_control_digfe_sel = 8;
10613pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGE_SEL:
10614 atom_dig_transmitter_control_digfe_sel = 16;
10615pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGF_SEL:
10616 atom_dig_transmitter_control_digfe_sel = 32;
10617pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGG_SEL:
10618 atom_dig_transmitter_control_digfe_sel = 64;
10619pub type atom_dig_transmitter_control_digfe_sel = ::core::ffi::c_uint;
10620pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_NO_HPD_SEL:
10621 atom_dig_transmitter_control_hpd_sel = 0;
10622pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD1_SEL:
10623 atom_dig_transmitter_control_hpd_sel = 1;
10624pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD2_SEL:
10625 atom_dig_transmitter_control_hpd_sel = 2;
10626pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD3_SEL:
10627 atom_dig_transmitter_control_hpd_sel = 3;
10628pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD4_SEL:
10629 atom_dig_transmitter_control_hpd_sel = 4;
10630pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD5_SEL:
10631 atom_dig_transmitter_control_hpd_sel = 5;
10632pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD6_SEL:
10633 atom_dig_transmitter_control_hpd_sel = 6;
10634pub type atom_dig_transmitter_control_hpd_sel = ::core::ffi::c_uint;
10635pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_4V:
10636 atom_dig_transmitter_control_dplaneset = 0;
10637pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_6V:
10638 atom_dig_transmitter_control_dplaneset = 1;
10639pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_8V:
10640 atom_dig_transmitter_control_dplaneset = 2;
10641pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_1_2V:
10642 atom_dig_transmitter_control_dplaneset = 3;
10643pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_4V:
10644 atom_dig_transmitter_control_dplaneset = 8;
10645pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_6V:
10646 atom_dig_transmitter_control_dplaneset = 9;
10647pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_8V:
10648 atom_dig_transmitter_control_dplaneset = 10;
10649pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__6DB_0_4V:
10650 atom_dig_transmitter_control_dplaneset = 16;
10651pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__6DB_0_6V:
10652 atom_dig_transmitter_control_dplaneset = 17;
10653pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__9_5DB_0_4V:
10654 atom_dig_transmitter_control_dplaneset = 24;
10655pub type atom_dig_transmitter_control_dplaneset = ::core::ffi::c_uint;
10656#[repr(C, packed)]
10657#[derive(Debug, Copy, Clone)]
10658pub struct external_encoder_control_parameters_v2_4 {
10659 pub pixelclock_10khz: u16,
10660 pub config: u8,
10661 pub action: u8,
10662 pub encodermode: u8,
10663 pub lanenum: u8,
10664 pub bitpercolor: u8,
10665 pub hpd_id: u8,
10666}
10667pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT:
10668 external_encoder_control_action_def = 0;
10669pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT:
10670 external_encoder_control_action_def = 1;
10671pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT:
10672 external_encoder_control_action_def = 7;
10673pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP:
10674 external_encoder_control_action_def = 15;
10675pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF:
10676 external_encoder_control_action_def = 16;
10677pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING:
10678 external_encoder_control_action_def = 17;
10679pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION:
10680 external_encoder_control_action_def = 18;
10681pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP:
10682 external_encoder_control_action_def = 20;
10683pub type external_encoder_control_action_def = ::core::ffi::c_uint;
10684pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK:
10685 external_encoder_control_v2_4_config_def = 3;
10686pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ:
10687 external_encoder_control_v2_4_config_def = 0;
10688pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ:
10689 external_encoder_control_v2_4_config_def = 1;
10690pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ:
10691 external_encoder_control_v2_4_config_def = 2;
10692pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ:
10693 external_encoder_control_v2_4_config_def = 3;
10694pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS:
10695 external_encoder_control_v2_4_config_def = 112;
10696pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER1:
10697 external_encoder_control_v2_4_config_def = 0;
10698pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER2:
10699 external_encoder_control_v2_4_config_def = 16;
10700pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER3:
10701 external_encoder_control_v2_4_config_def = 32;
10702pub type external_encoder_control_v2_4_config_def = ::core::ffi::c_uint;
10703#[repr(C, packed)]
10704#[derive(Debug, Copy, Clone)]
10705pub struct external_encoder_control_ps_allocation_v2_4 {
10706 pub sExtEncoder: external_encoder_control_parameters_v2_4,
10707 pub reserved: [u32; 2usize],
10708}
10709#[repr(C, packed)]
10710#[derive(Debug, Copy, Clone)]
10711pub struct amd_acpi_description_header {
10712 pub signature: u32,
10713 pub tableLength: u32,
10714 pub revision: u8,
10715 pub checksum: u8,
10716 pub oemId: [u8; 6usize],
10717 pub oemTableId: [u8; 8usize],
10718 pub oemRevision: u32,
10719 pub creatorId: u32,
10720 pub creatorRevision: u32,
10721}
10722#[repr(C, packed)]
10723#[derive(Debug, Copy, Clone)]
10724pub struct uefi_acpi_vfct {
10725 pub sheader: amd_acpi_description_header,
10726 pub tableUUID: [u8; 16usize],
10727 pub vbiosimageoffset: u32,
10728 pub lib1Imageoffset: u32,
10729 pub reserved: [u32; 4usize],
10730}
10731#[repr(C, packed)]
10732#[derive(Debug, Copy, Clone)]
10733pub struct vfct_image_header {
10734 pub pcibus: u32,
10735 pub pcidevice: u32,
10736 pub pcifunction: u32,
10737 pub vendorid: u16,
10738 pub deviceid: u16,
10739 pub ssvid: u16,
10740 pub ssid: u16,
10741 pub revision: u32,
10742 pub imagelength: u32,
10743}
10744#[repr(C)]
10745#[derive(Debug, Copy, Clone)]
10746pub struct gop_vbios_content {
10747 pub vbiosheader: vfct_image_header,
10748 pub vbioscontent: [u8; 1usize],
10749}
10750#[repr(C)]
10751#[derive(Debug, Copy, Clone)]
10752pub struct gop_lib1_content {
10753 pub lib1header: vfct_image_header,
10754 pub lib1content: [u8; 1usize],
10755}
10756pub const scratch_register_def_ATOM_DEVICE_CONNECT_INFO_DEF: scratch_register_def = 0;
10757pub const scratch_register_def_ATOM_BL_BRI_LEVEL_INFO_DEF: scratch_register_def = 2;
10758pub const scratch_register_def_ATOM_ACTIVE_INFO_DEF: scratch_register_def = 3;
10759pub const scratch_register_def_ATOM_LCD_INFO_DEF: scratch_register_def = 4;
10760pub const scratch_register_def_ATOM_DEVICE_REQ_INFO_DEF: scratch_register_def = 5;
10761pub const scratch_register_def_ATOM_ACC_CHANGE_INFO_DEF: scratch_register_def = 6;
10762pub const scratch_register_def_ATOM_PRE_OS_MODE_INFO_DEF: scratch_register_def = 7;
10763pub const scratch_register_def_ATOM_PRE_OS_ASSERTION_DEF: scratch_register_def = 8;
10764pub const scratch_register_def_ATOM_INTERNAL_TIMER_INFO_DEF: scratch_register_def = 10;
10765pub type scratch_register_def = ::core::ffi::c_uint;
10766pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_LCD1_CONNECT:
10767 scratch_device_connect_info_bit_def = 2;
10768pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP1_CONNECT:
10769 scratch_device_connect_info_bit_def = 8;
10770pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP2_CONNECT:
10771 scratch_device_connect_info_bit_def = 128;
10772pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP3_CONNECT:
10773 scratch_device_connect_info_bit_def = 512;
10774pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP4_CONNECT:
10775 scratch_device_connect_info_bit_def = 1024;
10776pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP5_CONNECT:
10777 scratch_device_connect_info_bit_def = 2048;
10778pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP6_CONNECT:
10779 scratch_device_connect_info_bit_def = 64;
10780pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFPx_CONNECT:
10781 scratch_device_connect_info_bit_def = 3784;
10782pub const scratch_device_connect_info_bit_def_ATOM_CONNECT_INFO_DEVICE_MASK:
10783 scratch_device_connect_info_bit_def = 4095;
10784pub type scratch_device_connect_info_bit_def = ::core::ffi::c_uint;
10785pub const scratch_bl_bri_level_info_bit_def_ATOM_CURRENT_BL_LEVEL_SHIFT:
10786 scratch_bl_bri_level_info_bit_def = 8;
10787pub const scratch_bl_bri_level_info_bit_def_ATOM_CURRENT_BL_LEVEL_MASK:
10788 scratch_bl_bri_level_info_bit_def = 65280;
10789pub const scratch_bl_bri_level_info_bit_def_ATOM_DEVICE_DPMS_STATE:
10790 scratch_bl_bri_level_info_bit_def = 65536;
10791pub type scratch_bl_bri_level_info_bit_def = ::core::ffi::c_uint;
10792pub const scratch_active_info_bits_def_ATOM_DISPLAY_LCD1_ACTIVE: scratch_active_info_bits_def = 2;
10793pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP1_ACTIVE: scratch_active_info_bits_def = 8;
10794pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP2_ACTIVE: scratch_active_info_bits_def = 128;
10795pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP3_ACTIVE: scratch_active_info_bits_def = 512;
10796pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP4_ACTIVE: scratch_active_info_bits_def =
10797 1024;
10798pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP5_ACTIVE: scratch_active_info_bits_def =
10799 2048;
10800pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP6_ACTIVE: scratch_active_info_bits_def = 64;
10801pub const scratch_active_info_bits_def_ATOM_ACTIVE_INFO_DEVICE_MASK: scratch_active_info_bits_def =
10802 4095;
10803pub type scratch_active_info_bits_def = ::core::ffi::c_uint;
10804pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_LCD1_REQ: scratch_device_req_info_bits_def =
10805 2;
10806pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP1_REQ: scratch_device_req_info_bits_def =
10807 8;
10808pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP2_REQ: scratch_device_req_info_bits_def =
10809 128;
10810pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP3_REQ: scratch_device_req_info_bits_def =
10811 512;
10812pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP4_REQ: scratch_device_req_info_bits_def =
10813 1024;
10814pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP5_REQ: scratch_device_req_info_bits_def =
10815 2048;
10816pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP6_REQ: scratch_device_req_info_bits_def =
10817 64;
10818pub const scratch_device_req_info_bits_def_ATOM_REQ_INFO_DEVICE_MASK:
10819 scratch_device_req_info_bits_def = 4095;
10820pub type scratch_device_req_info_bits_def = ::core::ffi::c_uint;
10821pub const scratch_acc_change_info_bitshift_def_ATOM_ACC_CHANGE_ACC_MODE_SHIFT:
10822 scratch_acc_change_info_bitshift_def = 4;
10823pub const scratch_acc_change_info_bitshift_def_ATOM_ACC_CHANGE_LID_STATUS_SHIFT:
10824 scratch_acc_change_info_bitshift_def = 6;
10825pub type scratch_acc_change_info_bitshift_def = ::core::ffi::c_uint;
10826pub const scratch_acc_change_info_bits_def_ATOM_ACC_CHANGE_ACC_MODE:
10827 scratch_acc_change_info_bits_def = 16;
10828pub const scratch_acc_change_info_bits_def_ATOM_ACC_CHANGE_LID_STATUS:
10829 scratch_acc_change_info_bits_def = 64;
10830pub type scratch_acc_change_info_bits_def = ::core::ffi::c_uint;
10831pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_MASK:
10832 scratch_pre_os_mode_info_bits_def = 3;
10833pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_VGA:
10834 scratch_pre_os_mode_info_bits_def = 0;
10835pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_VESA:
10836 scratch_pre_os_mode_info_bits_def = 1;
10837pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_GOP:
10838 scratch_pre_os_mode_info_bits_def = 2;
10839pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_PIXEL_DEPTH:
10840 scratch_pre_os_mode_info_bits_def = 12;
10841pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK:
10842 scratch_pre_os_mode_info_bits_def = 240;
10843pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_8BIT_PAL_EN:
10844 scratch_pre_os_mode_info_bits_def = 256;
10845pub const scratch_pre_os_mode_info_bits_def_ATOM_ASIC_INIT_COMPLETE:
10846 scratch_pre_os_mode_info_bits_def = 512;
10847pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_NUMBER_MASK:
10848 scratch_pre_os_mode_info_bits_def = 4294901760;
10849pub type scratch_pre_os_mode_info_bits_def = ::core::ffi::c_uint;
10850pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UTILITY_PIPELINE: atom_master_data_table_id =
10851 0;
10852pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__MULTIMEDIA_INF: atom_master_data_table_id =
10853 1;
10854pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__FIRMWARE_INF: atom_master_data_table_id = 2;
10855pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__LCD_INF: atom_master_data_table_id = 3;
10856pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__SMU_INF: atom_master_data_table_id = 4;
10857pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE:
10858 atom_master_data_table_id = 5;
10859pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__GPIO_PIN_LUT: atom_master_data_table_id = 6;
10860pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__GFX_INF: atom_master_data_table_id = 7;
10861pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__POWER_PLAY_INF: atom_master_data_table_id =
10862 8;
10863pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF:
10864 atom_master_data_table_id = 9;
10865pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS:
10866 atom_master_data_table_id = 10;
10867pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UMC_INF: atom_master_data_table_id = 11;
10868pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__DCE_INF: atom_master_data_table_id = 12;
10869pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VRAM_INF: atom_master_data_table_id = 13;
10870pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF:
10871 atom_master_data_table_id = 14;
10872pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF:
10873 atom_master_data_table_id = 15;
10874pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF: atom_master_data_table_id =
10875 16;
10876pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UNDEFINED: atom_master_data_table_id = 17;
10877pub type atom_master_data_table_id = ::core::ffi::c_uint;
10878pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ASIC_INIT: atom_master_command_table_id =
10879 0;
10880pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL:
10881 atom_master_command_table_id = 1;
10882pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK:
10883 atom_master_command_table_id = 2;
10884pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK:
10885 atom_master_command_table_id = 3;
10886pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK:
10887 atom_master_command_table_id = 4;
10888pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING:
10889 atom_master_command_table_id = 5;
10890pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__BLANK_CRTC: atom_master_command_table_id =
10891 6;
10892pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ENABLE_CRTC: atom_master_command_table_id =
10893 7;
10894pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO:
10895 atom_master_command_table_id = 8;
10896pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE:
10897 atom_master_command_table_id = 9;
10898pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_DCE_CLOCK:
10899 atom_master_command_table_id = 10;
10900pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK:
10901 atom_master_command_table_id = 11;
10902pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK:
10903 atom_master_command_table_id = 12;
10904pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING:
10905 atom_master_command_table_id = 13;
10906pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL:
10907 atom_master_command_table_id = 14;
10908pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION:
10909 atom_master_command_table_id = 15;
10910pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM:
10911 atom_master_command_table_id = 16;
10912pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS:
10913 atom_master_command_table_id = 17;
10914pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__MEMORY_TRAINING:
10915 atom_master_command_table_id = 18;
10916pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_VOLTAGE: atom_master_command_table_id =
10917 19;
10918pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL:
10919 atom_master_command_table_id = 20;
10920pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION:
10921 atom_master_command_table_id = 21;
10922pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF:
10923 atom_master_command_table_id = 22;
10924pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__UNDEFINED: atom_master_command_table_id =
10925 23;
10926pub type atom_master_command_table_id = ::core::ffi::c_uint;
10927#[repr(C)]
10928#[derive(Debug, Copy, Clone)]
10929pub struct metrics_table_header {
10930 pub structure_size: u16,
10931 pub format_revision: u8,
10932 pub content_revision: u8,
10933}
10934#[repr(C)]
10935#[derive(Debug, Copy, Clone)]
10936pub struct gpu_metrics_v1_0 {
10937 pub common_header: metrics_table_header,
10938 pub system_clock_counter: u64,
10939 pub temperature_edge: u16,
10940 pub temperature_hotspot: u16,
10941 pub temperature_mem: u16,
10942 pub temperature_vrgfx: u16,
10943 pub temperature_vrsoc: u16,
10944 pub temperature_vrmem: u16,
10945 pub average_gfx_activity: u16,
10946 pub average_umc_activity: u16,
10947 pub average_mm_activity: u16,
10948 pub average_socket_power: u16,
10949 pub energy_accumulator: u32,
10950 pub average_gfxclk_frequency: u16,
10951 pub average_socclk_frequency: u16,
10952 pub average_uclk_frequency: u16,
10953 pub average_vclk0_frequency: u16,
10954 pub average_dclk0_frequency: u16,
10955 pub average_vclk1_frequency: u16,
10956 pub average_dclk1_frequency: u16,
10957 pub current_gfxclk: u16,
10958 pub current_socclk: u16,
10959 pub current_uclk: u16,
10960 pub current_vclk0: u16,
10961 pub current_dclk0: u16,
10962 pub current_vclk1: u16,
10963 pub current_dclk1: u16,
10964 pub throttle_status: u32,
10965 pub current_fan_speed: u16,
10966 pub pcie_link_width: u8,
10967 pub pcie_link_speed: u8,
10968}
10969#[repr(C)]
10970#[derive(Debug, Copy, Clone)]
10971pub struct gpu_metrics_v1_1 {
10972 pub common_header: metrics_table_header,
10973 pub temperature_edge: u16,
10974 pub temperature_hotspot: u16,
10975 pub temperature_mem: u16,
10976 pub temperature_vrgfx: u16,
10977 pub temperature_vrsoc: u16,
10978 pub temperature_vrmem: u16,
10979 pub average_gfx_activity: u16,
10980 pub average_umc_activity: u16,
10981 pub average_mm_activity: u16,
10982 pub average_socket_power: u16,
10983 pub energy_accumulator: u64,
10984 pub system_clock_counter: u64,
10985 pub average_gfxclk_frequency: u16,
10986 pub average_socclk_frequency: u16,
10987 pub average_uclk_frequency: u16,
10988 pub average_vclk0_frequency: u16,
10989 pub average_dclk0_frequency: u16,
10990 pub average_vclk1_frequency: u16,
10991 pub average_dclk1_frequency: u16,
10992 pub current_gfxclk: u16,
10993 pub current_socclk: u16,
10994 pub current_uclk: u16,
10995 pub current_vclk0: u16,
10996 pub current_dclk0: u16,
10997 pub current_vclk1: u16,
10998 pub current_dclk1: u16,
10999 pub throttle_status: u32,
11000 pub current_fan_speed: u16,
11001 pub pcie_link_width: u16,
11002 pub pcie_link_speed: u16,
11003 pub padding: u16,
11004 pub gfx_activity_acc: u32,
11005 pub mem_activity_acc: u32,
11006 pub temperature_hbm: [u16; 4usize],
11007}
11008#[repr(C)]
11009#[derive(Debug, Copy, Clone)]
11010pub struct gpu_metrics_v1_2 {
11011 pub common_header: metrics_table_header,
11012 pub temperature_edge: u16,
11013 pub temperature_hotspot: u16,
11014 pub temperature_mem: u16,
11015 pub temperature_vrgfx: u16,
11016 pub temperature_vrsoc: u16,
11017 pub temperature_vrmem: u16,
11018 pub average_gfx_activity: u16,
11019 pub average_umc_activity: u16,
11020 pub average_mm_activity: u16,
11021 pub average_socket_power: u16,
11022 pub energy_accumulator: u64,
11023 pub system_clock_counter: u64,
11024 pub average_gfxclk_frequency: u16,
11025 pub average_socclk_frequency: u16,
11026 pub average_uclk_frequency: u16,
11027 pub average_vclk0_frequency: u16,
11028 pub average_dclk0_frequency: u16,
11029 pub average_vclk1_frequency: u16,
11030 pub average_dclk1_frequency: u16,
11031 pub current_gfxclk: u16,
11032 pub current_socclk: u16,
11033 pub current_uclk: u16,
11034 pub current_vclk0: u16,
11035 pub current_dclk0: u16,
11036 pub current_vclk1: u16,
11037 pub current_dclk1: u16,
11038 pub throttle_status: u32,
11039 pub current_fan_speed: u16,
11040 pub pcie_link_width: u16,
11041 pub pcie_link_speed: u16,
11042 pub padding: u16,
11043 pub gfx_activity_acc: u32,
11044 pub mem_activity_acc: u32,
11045 pub temperature_hbm: [u16; 4usize],
11046 pub firmware_timestamp: u64,
11047}
11048#[repr(C)]
11049#[derive(Debug, Copy, Clone)]
11050pub struct gpu_metrics_v1_3 {
11051 pub common_header: metrics_table_header,
11052 pub temperature_edge: u16,
11053 pub temperature_hotspot: u16,
11054 pub temperature_mem: u16,
11055 pub temperature_vrgfx: u16,
11056 pub temperature_vrsoc: u16,
11057 pub temperature_vrmem: u16,
11058 pub average_gfx_activity: u16,
11059 pub average_umc_activity: u16,
11060 pub average_mm_activity: u16,
11061 pub average_socket_power: u16,
11062 pub energy_accumulator: u64,
11063 pub system_clock_counter: u64,
11064 pub average_gfxclk_frequency: u16,
11065 pub average_socclk_frequency: u16,
11066 pub average_uclk_frequency: u16,
11067 pub average_vclk0_frequency: u16,
11068 pub average_dclk0_frequency: u16,
11069 pub average_vclk1_frequency: u16,
11070 pub average_dclk1_frequency: u16,
11071 pub current_gfxclk: u16,
11072 pub current_socclk: u16,
11073 pub current_uclk: u16,
11074 pub current_vclk0: u16,
11075 pub current_dclk0: u16,
11076 pub current_vclk1: u16,
11077 pub current_dclk1: u16,
11078 pub throttle_status: u32,
11079 pub current_fan_speed: u16,
11080 pub pcie_link_width: u16,
11081 pub pcie_link_speed: u16,
11082 pub padding: u16,
11083 pub gfx_activity_acc: u32,
11084 pub mem_activity_acc: u32,
11085 pub temperature_hbm: [u16; 4usize],
11086 pub firmware_timestamp: u64,
11087 pub voltage_soc: u16,
11088 pub voltage_gfx: u16,
11089 pub voltage_mem: u16,
11090 pub padding1: u16,
11091 pub indep_throttle_status: u64,
11092}
11093#[repr(C)]
11094#[derive(Debug, Copy, Clone)]
11095pub struct gpu_metrics_v1_4 {
11096 pub common_header: metrics_table_header,
11097 pub temperature_hotspot: u16,
11098 pub temperature_mem: u16,
11099 pub temperature_vrsoc: u16,
11100 pub curr_socket_power: u16,
11101 pub average_gfx_activity: u16,
11102 pub average_umc_activity: u16,
11103 pub vcn_activity: [u16; 4usize],
11104 pub energy_accumulator: u64,
11105 pub system_clock_counter: u64,
11106 pub throttle_status: u32,
11107 pub gfxclk_lock_status: u32,
11108 pub pcie_link_width: u16,
11109 pub pcie_link_speed: u16,
11110 pub xgmi_link_width: u16,
11111 pub xgmi_link_speed: u16,
11112 pub gfx_activity_acc: u32,
11113 pub mem_activity_acc: u32,
11114 pub pcie_bandwidth_acc: u64,
11115 pub pcie_bandwidth_inst: u64,
11116 pub pcie_l0_to_recov_count_acc: u64,
11117 pub pcie_replay_count_acc: u64,
11118 pub pcie_replay_rover_count_acc: u64,
11119 pub xgmi_read_data_acc: [u64; 8usize],
11120 pub xgmi_write_data_acc: [u64; 8usize],
11121 pub firmware_timestamp: u64,
11122 pub current_gfxclk: [u16; 8usize],
11123 pub current_socclk: [u16; 4usize],
11124 pub current_vclk0: [u16; 4usize],
11125 pub current_dclk0: [u16; 4usize],
11126 pub current_uclk: u16,
11127 pub padding: u16,
11128}
11129#[repr(C)]
11130#[derive(Debug, Copy, Clone)]
11131pub struct gpu_metrics_v1_5 {
11132 pub common_header: metrics_table_header,
11133 pub temperature_hotspot: u16,
11134 pub temperature_mem: u16,
11135 pub temperature_vrsoc: u16,
11136 pub curr_socket_power: u16,
11137 pub average_gfx_activity: u16,
11138 pub average_umc_activity: u16,
11139 pub vcn_activity: [u16; 4usize],
11140 pub jpeg_activity: [u16; 32usize],
11141 pub energy_accumulator: u64,
11142 pub system_clock_counter: u64,
11143 pub throttle_status: u32,
11144 pub gfxclk_lock_status: u32,
11145 pub pcie_link_width: u16,
11146 pub pcie_link_speed: u16,
11147 pub xgmi_link_width: u16,
11148 pub xgmi_link_speed: u16,
11149 pub gfx_activity_acc: u32,
11150 pub mem_activity_acc: u32,
11151 pub pcie_bandwidth_acc: u64,
11152 pub pcie_bandwidth_inst: u64,
11153 pub pcie_l0_to_recov_count_acc: u64,
11154 pub pcie_replay_count_acc: u64,
11155 pub pcie_replay_rover_count_acc: u64,
11156 pub pcie_nak_sent_count_acc: u32,
11157 pub pcie_nak_rcvd_count_acc: u32,
11158 pub xgmi_read_data_acc: [u64; 8usize],
11159 pub xgmi_write_data_acc: [u64; 8usize],
11160 pub firmware_timestamp: u64,
11161 pub current_gfxclk: [u16; 8usize],
11162 pub current_socclk: [u16; 4usize],
11163 pub current_vclk0: [u16; 4usize],
11164 pub current_dclk0: [u16; 4usize],
11165 pub current_uclk: u16,
11166 pub padding: u16,
11167}
11168#[repr(C)]
11169#[derive(Debug, Copy, Clone)]
11170pub struct gpu_metrics_v2_0 {
11171 pub common_header: metrics_table_header,
11172 pub system_clock_counter: u64,
11173 pub temperature_gfx: u16,
11174 pub temperature_soc: u16,
11175 pub temperature_core: [u16; 8usize],
11176 pub temperature_l3: [u16; 2usize],
11177 pub average_gfx_activity: u16,
11178 pub average_mm_activity: u16,
11179 pub average_socket_power: u16,
11180 pub average_cpu_power: u16,
11181 pub average_soc_power: u16,
11182 pub average_gfx_power: u16,
11183 pub average_core_power: [u16; 8usize],
11184 pub average_gfxclk_frequency: u16,
11185 pub average_socclk_frequency: u16,
11186 pub average_uclk_frequency: u16,
11187 pub average_fclk_frequency: u16,
11188 pub average_vclk_frequency: u16,
11189 pub average_dclk_frequency: u16,
11190 pub current_gfxclk: u16,
11191 pub current_socclk: u16,
11192 pub current_uclk: u16,
11193 pub current_fclk: u16,
11194 pub current_vclk: u16,
11195 pub current_dclk: u16,
11196 pub current_coreclk: [u16; 8usize],
11197 pub current_l3clk: [u16; 2usize],
11198 pub throttle_status: u32,
11199 pub fan_pwm: u16,
11200 pub padding: u16,
11201}
11202#[repr(C)]
11203#[derive(Debug, Copy, Clone)]
11204pub struct gpu_metrics_v2_1 {
11205 pub common_header: metrics_table_header,
11206 pub temperature_gfx: u16,
11207 pub temperature_soc: u16,
11208 pub temperature_core: [u16; 8usize],
11209 pub temperature_l3: [u16; 2usize],
11210 pub average_gfx_activity: u16,
11211 pub average_mm_activity: u16,
11212 pub system_clock_counter: u64,
11213 pub average_socket_power: u16,
11214 pub average_cpu_power: u16,
11215 pub average_soc_power: u16,
11216 pub average_gfx_power: u16,
11217 pub average_core_power: [u16; 8usize],
11218 pub average_gfxclk_frequency: u16,
11219 pub average_socclk_frequency: u16,
11220 pub average_uclk_frequency: u16,
11221 pub average_fclk_frequency: u16,
11222 pub average_vclk_frequency: u16,
11223 pub average_dclk_frequency: u16,
11224 pub current_gfxclk: u16,
11225 pub current_socclk: u16,
11226 pub current_uclk: u16,
11227 pub current_fclk: u16,
11228 pub current_vclk: u16,
11229 pub current_dclk: u16,
11230 pub current_coreclk: [u16; 8usize],
11231 pub current_l3clk: [u16; 2usize],
11232 pub throttle_status: u32,
11233 pub fan_pwm: u16,
11234 pub padding: [u16; 3usize],
11235}
11236#[repr(C)]
11237#[derive(Debug, Copy, Clone)]
11238pub struct gpu_metrics_v2_2 {
11239 pub common_header: metrics_table_header,
11240 pub temperature_gfx: u16,
11241 pub temperature_soc: u16,
11242 pub temperature_core: [u16; 8usize],
11243 pub temperature_l3: [u16; 2usize],
11244 pub average_gfx_activity: u16,
11245 pub average_mm_activity: u16,
11246 pub system_clock_counter: u64,
11247 pub average_socket_power: u16,
11248 pub average_cpu_power: u16,
11249 pub average_soc_power: u16,
11250 pub average_gfx_power: u16,
11251 pub average_core_power: [u16; 8usize],
11252 pub average_gfxclk_frequency: u16,
11253 pub average_socclk_frequency: u16,
11254 pub average_uclk_frequency: u16,
11255 pub average_fclk_frequency: u16,
11256 pub average_vclk_frequency: u16,
11257 pub average_dclk_frequency: u16,
11258 pub current_gfxclk: u16,
11259 pub current_socclk: u16,
11260 pub current_uclk: u16,
11261 pub current_fclk: u16,
11262 pub current_vclk: u16,
11263 pub current_dclk: u16,
11264 pub current_coreclk: [u16; 8usize],
11265 pub current_l3clk: [u16; 2usize],
11266 pub throttle_status: u32,
11267 pub fan_pwm: u16,
11268 pub padding: [u16; 3usize],
11269 pub indep_throttle_status: u64,
11270}
11271#[repr(C)]
11272#[derive(Debug, Copy, Clone)]
11273pub struct gpu_metrics_v2_3 {
11274 pub common_header: metrics_table_header,
11275 pub temperature_gfx: u16,
11276 pub temperature_soc: u16,
11277 pub temperature_core: [u16; 8usize],
11278 pub temperature_l3: [u16; 2usize],
11279 pub average_gfx_activity: u16,
11280 pub average_mm_activity: u16,
11281 pub system_clock_counter: u64,
11282 pub average_socket_power: u16,
11283 pub average_cpu_power: u16,
11284 pub average_soc_power: u16,
11285 pub average_gfx_power: u16,
11286 pub average_core_power: [u16; 8usize],
11287 pub average_gfxclk_frequency: u16,
11288 pub average_socclk_frequency: u16,
11289 pub average_uclk_frequency: u16,
11290 pub average_fclk_frequency: u16,
11291 pub average_vclk_frequency: u16,
11292 pub average_dclk_frequency: u16,
11293 pub current_gfxclk: u16,
11294 pub current_socclk: u16,
11295 pub current_uclk: u16,
11296 pub current_fclk: u16,
11297 pub current_vclk: u16,
11298 pub current_dclk: u16,
11299 pub current_coreclk: [u16; 8usize],
11300 pub current_l3clk: [u16; 2usize],
11301 pub throttle_status: u32,
11302 pub fan_pwm: u16,
11303 pub padding: [u16; 3usize],
11304 pub indep_throttle_status: u64,
11305 pub average_temperature_gfx: u16,
11306 pub average_temperature_soc: u16,
11307 pub average_temperature_core: [u16; 8usize],
11308 pub average_temperature_l3: [u16; 2usize],
11309}
11310#[repr(C)]
11311#[derive(Debug, Copy, Clone)]
11312pub struct gpu_metrics_v2_4 {
11313 pub common_header: metrics_table_header,
11314 pub temperature_gfx: u16,
11315 pub temperature_soc: u16,
11316 pub temperature_core: [u16; 8usize],
11317 pub temperature_l3: [u16; 2usize],
11318 pub average_gfx_activity: u16,
11319 pub average_mm_activity: u16,
11320 pub system_clock_counter: u64,
11321 pub average_socket_power: u16,
11322 pub average_cpu_power: u16,
11323 pub average_soc_power: u16,
11324 pub average_gfx_power: u16,
11325 pub average_core_power: [u16; 8usize],
11326 pub average_gfxclk_frequency: u16,
11327 pub average_socclk_frequency: u16,
11328 pub average_uclk_frequency: u16,
11329 pub average_fclk_frequency: u16,
11330 pub average_vclk_frequency: u16,
11331 pub average_dclk_frequency: u16,
11332 pub current_gfxclk: u16,
11333 pub current_socclk: u16,
11334 pub current_uclk: u16,
11335 pub current_fclk: u16,
11336 pub current_vclk: u16,
11337 pub current_dclk: u16,
11338 pub current_coreclk: [u16; 8usize],
11339 pub current_l3clk: [u16; 2usize],
11340 pub throttle_status: u32,
11341 pub fan_pwm: u16,
11342 pub padding: [u16; 3usize],
11343 pub indep_throttle_status: u64,
11344 pub average_temperature_gfx: u16,
11345 pub average_temperature_soc: u16,
11346 pub average_temperature_core: [u16; 8usize],
11347 pub average_temperature_l3: [u16; 2usize],
11348 pub average_cpu_voltage: u16,
11349 pub average_soc_voltage: u16,
11350 pub average_gfx_voltage: u16,
11351 pub average_cpu_current: u16,
11352 pub average_soc_current: u16,
11353 pub average_gfx_current: u16,
11354}
11355#[repr(C)]
11356#[derive(Debug, Copy, Clone)]
11357pub struct gpu_metrics_v3_0 {
11358 pub common_header: metrics_table_header,
11359 pub temperature_gfx: u16,
11360 pub temperature_soc: u16,
11361 pub temperature_core: [u16; 16usize],
11362 pub temperature_skin: u16,
11363 pub average_gfx_activity: u16,
11364 pub average_vcn_activity: u16,
11365 pub average_ipu_activity: [u16; 8usize],
11366 pub average_core_c0_activity: [u16; 16usize],
11367 pub average_dram_reads: u16,
11368 pub average_dram_writes: u16,
11369 pub average_ipu_reads: u16,
11370 pub average_ipu_writes: u16,
11371 pub system_clock_counter: u64,
11372 pub average_socket_power: u32,
11373 pub average_ipu_power: u16,
11374 pub average_apu_power: u32,
11375 pub average_gfx_power: u32,
11376 pub average_dgpu_power: u32,
11377 pub average_all_core_power: u32,
11378 pub average_core_power: [u16; 16usize],
11379 pub average_sys_power: u16,
11380 pub stapm_power_limit: u16,
11381 pub current_stapm_power_limit: u16,
11382 pub average_gfxclk_frequency: u16,
11383 pub average_socclk_frequency: u16,
11384 pub average_vpeclk_frequency: u16,
11385 pub average_ipuclk_frequency: u16,
11386 pub average_fclk_frequency: u16,
11387 pub average_vclk_frequency: u16,
11388 pub average_uclk_frequency: u16,
11389 pub average_mpipu_frequency: u16,
11390 pub current_coreclk: [u16; 16usize],
11391 pub current_core_maxfreq: u16,
11392 pub current_gfx_maxfreq: u16,
11393 pub throttle_residency_prochot: u32,
11394 pub throttle_residency_spl: u32,
11395 pub throttle_residency_fppt: u32,
11396 pub throttle_residency_sppt: u32,
11397 pub throttle_residency_thm_core: u32,
11398 pub throttle_residency_thm_gfx: u32,
11399 pub throttle_residency_thm_soc: u32,
11400 pub time_filter_alphavalue: u32,
11401}
11402pub type __builtin_va_list = [__va_list_tag; 1usize];
11403#[repr(C)]
11404#[derive(Debug, Copy, Clone)]
11405pub struct __va_list_tag {
11406 pub gp_offset: ::core::ffi::c_uint,
11407 pub fp_offset: ::core::ffi::c_uint,
11408 pub overflow_arg_area: *mut ::core::ffi::c_void,
11409 pub reg_save_area: *mut ::core::ffi::c_void,
11410}