1#[repr(C)]
4#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
5pub struct __BindgenBitfieldUnit<Storage> {
6 storage: Storage,
7}
8impl<Storage> __BindgenBitfieldUnit<Storage> {
9 #[inline]
10 pub const fn new(storage: Storage) -> Self {
11 Self { storage }
12 }
13}
14impl<Storage> __BindgenBitfieldUnit<Storage>
15where
16 Storage: AsRef<[u8]> + AsMut<[u8]>,
17{
18 #[inline]
19 fn extract_bit(byte: u8, index: usize) -> bool {
20 let bit_index = if cfg!(target_endian = "big") {
21 7 - (index % 8)
22 } else {
23 index % 8
24 };
25 let mask = 1 << bit_index;
26 byte & mask == mask
27 }
28 #[inline]
29 pub fn get_bit(&self, index: usize) -> bool {
30 debug_assert!(index / 8 < self.storage.as_ref().len());
31 let byte_index = index / 8;
32 let byte = self.storage.as_ref()[byte_index];
33 Self::extract_bit(byte, index)
34 }
35 #[inline]
36 pub unsafe fn raw_get_bit(this: *const Self, index: usize) -> bool {
37 debug_assert!(index / 8 < core::mem::size_of::<Storage>());
38 let byte_index = index / 8;
39 let byte = unsafe {
40 *(core::ptr::addr_of!((*this).storage) as *const u8).offset(byte_index as isize)
41 };
42 Self::extract_bit(byte, index)
43 }
44 #[inline]
45 fn change_bit(byte: u8, index: usize, val: bool) -> u8 {
46 let bit_index = if cfg!(target_endian = "big") {
47 7 - (index % 8)
48 } else {
49 index % 8
50 };
51 let mask = 1 << bit_index;
52 if val { byte | mask } else { byte & !mask }
53 }
54 #[inline]
55 pub fn set_bit(&mut self, index: usize, val: bool) {
56 debug_assert!(index / 8 < self.storage.as_ref().len());
57 let byte_index = index / 8;
58 let byte = &mut self.storage.as_mut()[byte_index];
59 *byte = Self::change_bit(*byte, index, val);
60 }
61 #[inline]
62 pub unsafe fn raw_set_bit(this: *mut Self, index: usize, val: bool) {
63 debug_assert!(index / 8 < core::mem::size_of::<Storage>());
64 let byte_index = index / 8;
65 let byte = unsafe {
66 (core::ptr::addr_of_mut!((*this).storage) as *mut u8).offset(byte_index as isize)
67 };
68 unsafe { *byte = Self::change_bit(*byte, index, val) };
69 }
70 #[inline]
71 pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
72 debug_assert!(bit_width <= 64);
73 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
74 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
75 let mut val = 0;
76 for i in 0..(bit_width as usize) {
77 if self.get_bit(i + bit_offset) {
78 let index = if cfg!(target_endian = "big") {
79 bit_width as usize - 1 - i
80 } else {
81 i
82 };
83 val |= 1 << index;
84 }
85 }
86 val
87 }
88 #[inline]
89 pub unsafe fn raw_get(this: *const Self, bit_offset: usize, bit_width: u8) -> u64 {
90 debug_assert!(bit_width <= 64);
91 debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
92 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
93 let mut val = 0;
94 for i in 0..(bit_width as usize) {
95 if unsafe { Self::raw_get_bit(this, i + bit_offset) } {
96 let index = if cfg!(target_endian = "big") {
97 bit_width as usize - 1 - i
98 } else {
99 i
100 };
101 val |= 1 << index;
102 }
103 }
104 val
105 }
106 #[inline]
107 pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
108 debug_assert!(bit_width <= 64);
109 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
110 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
111 for i in 0..(bit_width as usize) {
112 let mask = 1 << i;
113 let val_bit_is_set = val & mask == mask;
114 let index = if cfg!(target_endian = "big") {
115 bit_width as usize - 1 - i
116 } else {
117 i
118 };
119 self.set_bit(index + bit_offset, val_bit_is_set);
120 }
121 }
122 #[inline]
123 pub unsafe fn raw_set(this: *mut Self, bit_offset: usize, bit_width: u8, val: u64) {
124 debug_assert!(bit_width <= 64);
125 debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
126 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
127 for i in 0..(bit_width as usize) {
128 let mask = 1 << i;
129 let val_bit_is_set = val & mask == mask;
130 let index = if cfg!(target_endian = "big") {
131 bit_width as usize - 1 - i
132 } else {
133 i
134 };
135 unsafe { Self::raw_set_bit(this, index + bit_offset, val_bit_is_set) };
136 }
137 }
138}
139#[repr(C)]
140#[derive(Default)]
141pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]);
142impl<T> __IncompleteArrayField<T> {
143 #[inline]
144 pub const fn new() -> Self {
145 __IncompleteArrayField(::core::marker::PhantomData, [])
146 }
147 #[inline]
148 pub fn as_ptr(&self) -> *const T {
149 self as *const _ as *const T
150 }
151 #[inline]
152 pub fn as_mut_ptr(&mut self) -> *mut T {
153 self as *mut _ as *mut T
154 }
155 #[inline]
156 pub unsafe fn as_slice(&self, len: usize) -> &[T] {
157 unsafe { ::core::slice::from_raw_parts(self.as_ptr(), len) }
158 }
159 #[inline]
160 pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] {
161 unsafe { ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len) }
162 }
163}
164impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> {
165 fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
166 fmt.write_str("__IncompleteArrayField")
167 }
168}
169pub const _SYS_TYPES_H: u32 = 1;
170pub const _FEATURES_H: u32 = 1;
171pub const _DEFAULT_SOURCE: u32 = 1;
172pub const __GLIBC_USE_ISOC2Y: u32 = 0;
173pub const __GLIBC_USE_ISOC23: u32 = 0;
174pub const __USE_ISOC11: u32 = 1;
175pub const __USE_ISOC99: u32 = 1;
176pub const __USE_ISOC95: u32 = 1;
177pub const __USE_POSIX_IMPLICITLY: u32 = 1;
178pub const _POSIX_SOURCE: u32 = 1;
179pub const _POSIX_C_SOURCE: u32 = 200809;
180pub const __USE_POSIX: u32 = 1;
181pub const __USE_POSIX2: u32 = 1;
182pub const __USE_POSIX199309: u32 = 1;
183pub const __USE_POSIX199506: u32 = 1;
184pub const __USE_XOPEN2K: u32 = 1;
185pub const __USE_XOPEN2K8: u32 = 1;
186pub const _ATFILE_SOURCE: u32 = 1;
187pub const __WORDSIZE: u32 = 64;
188pub const __WORDSIZE_TIME64_COMPAT32: u32 = 1;
189pub const __SYSCALL_WORDSIZE: u32 = 64;
190pub const __TIMESIZE: u32 = 64;
191pub const __USE_TIME_BITS64: u32 = 1;
192pub const __USE_MISC: u32 = 1;
193pub const __USE_ATFILE: u32 = 1;
194pub const __USE_FORTIFY_LEVEL: u32 = 0;
195pub const __GLIBC_USE_DEPRECATED_GETS: u32 = 0;
196pub const __GLIBC_USE_DEPRECATED_SCANF: u32 = 0;
197pub const __GLIBC_USE_C23_STRTOL: u32 = 0;
198pub const _STDC_PREDEF_H: u32 = 1;
199pub const __STDC_IEC_559__: u32 = 1;
200pub const __STDC_IEC_60559_BFP__: u32 = 201404;
201pub const __STDC_IEC_559_COMPLEX__: u32 = 1;
202pub const __STDC_IEC_60559_COMPLEX__: u32 = 201404;
203pub const __STDC_ISO_10646__: u32 = 201706;
204pub const __GNU_LIBRARY__: u32 = 6;
205pub const __GLIBC__: u32 = 2;
206pub const __GLIBC_MINOR__: u32 = 41;
207pub const _SYS_CDEFS_H: u32 = 1;
208pub const __glibc_c99_flexarr_available: u32 = 1;
209pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI: u32 = 0;
210pub const __HAVE_GENERIC_SELECTION: u32 = 1;
211pub const _BITS_TYPES_H: u32 = 1;
212pub const _BITS_TYPESIZES_H: u32 = 1;
213pub const __OFF_T_MATCHES_OFF64_T: u32 = 1;
214pub const __INO_T_MATCHES_INO64_T: u32 = 1;
215pub const __RLIM_T_MATCHES_RLIM64_T: u32 = 1;
216pub const __STATFS_MATCHES_STATFS64: u32 = 1;
217pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64: u32 = 1;
218pub const __FD_SETSIZE: u32 = 1024;
219pub const _BITS_TIME64_H: u32 = 1;
220pub const __clock_t_defined: u32 = 1;
221pub const __clockid_t_defined: u32 = 1;
222pub const __time_t_defined: u32 = 1;
223pub const __timer_t_defined: u32 = 1;
224pub const _BITS_STDINT_INTN_H: u32 = 1;
225pub const __BIT_TYPES_DEFINED__: u32 = 1;
226pub const _ENDIAN_H: u32 = 1;
227pub const _BITS_ENDIAN_H: u32 = 1;
228pub const __LITTLE_ENDIAN: u32 = 1234;
229pub const __BIG_ENDIAN: u32 = 4321;
230pub const __PDP_ENDIAN: u32 = 3412;
231pub const _BITS_ENDIANNESS_H: u32 = 1;
232pub const __BYTE_ORDER: u32 = 1234;
233pub const __FLOAT_WORD_ORDER: u32 = 1234;
234pub const LITTLE_ENDIAN: u32 = 1234;
235pub const BIG_ENDIAN: u32 = 4321;
236pub const PDP_ENDIAN: u32 = 3412;
237pub const BYTE_ORDER: u32 = 1234;
238pub const _BITS_BYTESWAP_H: u32 = 1;
239pub const _BITS_UINTN_IDENTITY_H: u32 = 1;
240pub const _SYS_SELECT_H: u32 = 1;
241pub const __sigset_t_defined: u32 = 1;
242pub const __timeval_defined: u32 = 1;
243pub const _STRUCT_TIMESPEC: u32 = 1;
244pub const FD_SETSIZE: u32 = 1024;
245pub const _BITS_PTHREADTYPES_COMMON_H: u32 = 1;
246pub const _THREAD_SHARED_TYPES_H: u32 = 1;
247pub const _BITS_PTHREADTYPES_ARCH_H: u32 = 1;
248pub const __SIZEOF_PTHREAD_MUTEX_T: u32 = 40;
249pub const __SIZEOF_PTHREAD_ATTR_T: u32 = 56;
250pub const __SIZEOF_PTHREAD_RWLOCK_T: u32 = 56;
251pub const __SIZEOF_PTHREAD_BARRIER_T: u32 = 32;
252pub const __SIZEOF_PTHREAD_MUTEXATTR_T: u32 = 4;
253pub const __SIZEOF_PTHREAD_COND_T: u32 = 48;
254pub const __SIZEOF_PTHREAD_CONDATTR_T: u32 = 4;
255pub const __SIZEOF_PTHREAD_RWLOCKATTR_T: u32 = 8;
256pub const __SIZEOF_PTHREAD_BARRIERATTR_T: u32 = 4;
257pub const _THREAD_MUTEX_INTERNAL_H: u32 = 1;
258pub const __PTHREAD_MUTEX_HAVE_PREV: u32 = 1;
259pub const __have_pthread_attr_t: u32 = 1;
260pub const _STDINT_H: u32 = 1;
261pub const __GLIBC_USE_LIB_EXT2: u32 = 0;
262pub const __GLIBC_USE_IEC_60559_BFP_EXT: u32 = 0;
263pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23: u32 = 0;
264pub const __GLIBC_USE_IEC_60559_EXT: u32 = 0;
265pub const __GLIBC_USE_IEC_60559_FUNCS_EXT: u32 = 0;
266pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23: u32 = 0;
267pub const __GLIBC_USE_IEC_60559_TYPES_EXT: u32 = 0;
268pub const _BITS_WCHAR_H: u32 = 1;
269pub const _BITS_STDINT_UINTN_H: u32 = 1;
270pub const _BITS_STDINT_LEAST_H: u32 = 1;
271pub const INT8_MIN: i32 = -128;
272pub const INT16_MIN: i32 = -32768;
273pub const INT32_MIN: i32 = -2147483648;
274pub const INT8_MAX: u32 = 127;
275pub const INT16_MAX: u32 = 32767;
276pub const INT32_MAX: u32 = 2147483647;
277pub const UINT8_MAX: u32 = 255;
278pub const UINT16_MAX: u32 = 65535;
279pub const UINT32_MAX: u32 = 4294967295;
280pub const INT_LEAST8_MIN: i32 = -128;
281pub const INT_LEAST16_MIN: i32 = -32768;
282pub const INT_LEAST32_MIN: i32 = -2147483648;
283pub const INT_LEAST8_MAX: u32 = 127;
284pub const INT_LEAST16_MAX: u32 = 32767;
285pub const INT_LEAST32_MAX: u32 = 2147483647;
286pub const UINT_LEAST8_MAX: u32 = 255;
287pub const UINT_LEAST16_MAX: u32 = 65535;
288pub const UINT_LEAST32_MAX: u32 = 4294967295;
289pub const INT_FAST8_MIN: i32 = -128;
290pub const INT_FAST16_MIN: i64 = -9223372036854775808;
291pub const INT_FAST32_MIN: i64 = -9223372036854775808;
292pub const INT_FAST8_MAX: u32 = 127;
293pub const INT_FAST16_MAX: u64 = 9223372036854775807;
294pub const INT_FAST32_MAX: u64 = 9223372036854775807;
295pub const UINT_FAST8_MAX: u32 = 255;
296pub const UINT_FAST16_MAX: i32 = -1;
297pub const UINT_FAST32_MAX: i32 = -1;
298pub const INTPTR_MIN: i64 = -9223372036854775808;
299pub const INTPTR_MAX: u64 = 9223372036854775807;
300pub const UINTPTR_MAX: i32 = -1;
301pub const PTRDIFF_MIN: i64 = -9223372036854775808;
302pub const PTRDIFF_MAX: u64 = 9223372036854775807;
303pub const SIG_ATOMIC_MIN: i32 = -2147483648;
304pub const SIG_ATOMIC_MAX: u32 = 2147483647;
305pub const SIZE_MAX: i32 = -1;
306pub const WINT_MIN: u32 = 0;
307pub const WINT_MAX: u32 = 4294967295;
308pub const __BITS_PER_LONG: u32 = 64;
309pub const __BITS_PER_LONG_LONG: u32 = 64;
310pub const _IOC_NRBITS: u32 = 8;
311pub const _IOC_TYPEBITS: u32 = 8;
312pub const _IOC_SIZEBITS: u32 = 14;
313pub const _IOC_DIRBITS: u32 = 2;
314pub const _IOC_NRMASK: u32 = 255;
315pub const _IOC_TYPEMASK: u32 = 255;
316pub const _IOC_SIZEMASK: u32 = 16383;
317pub const _IOC_DIRMASK: u32 = 3;
318pub const _IOC_NRSHIFT: u32 = 0;
319pub const _IOC_TYPESHIFT: u32 = 8;
320pub const _IOC_SIZESHIFT: u32 = 16;
321pub const _IOC_DIRSHIFT: u32 = 30;
322pub const _IOC_NONE: u32 = 0;
323pub const _IOC_WRITE: u32 = 1;
324pub const _IOC_READ: u32 = 2;
325pub const IOC_IN: u32 = 1073741824;
326pub const IOC_OUT: u32 = 2147483648;
327pub const IOC_INOUT: u32 = 3221225472;
328pub const IOCSIZE_MASK: u32 = 1073676288;
329pub const IOCSIZE_SHIFT: u32 = 16;
330pub const DRM_NAME: &[u8; 4] = b"drm\0";
331pub const DRM_MIN_ORDER: u32 = 5;
332pub const DRM_MAX_ORDER: u32 = 22;
333pub const DRM_RAM_PERCENT: u32 = 10;
334pub const _DRM_LOCK_HELD: u32 = 2147483648;
335pub const _DRM_LOCK_CONT: u32 = 1073741824;
336pub const _DRM_VBLANK_HIGH_CRTC_SHIFT: u32 = 1;
337pub const _DRM_PRE_MODESET: u32 = 1;
338pub const _DRM_POST_MODESET: u32 = 2;
339pub const DRM_CAP_DUMB_BUFFER: u32 = 1;
340pub const DRM_CAP_VBLANK_HIGH_CRTC: u32 = 2;
341pub const DRM_CAP_DUMB_PREFERRED_DEPTH: u32 = 3;
342pub const DRM_CAP_DUMB_PREFER_SHADOW: u32 = 4;
343pub const DRM_CAP_PRIME: u32 = 5;
344pub const DRM_PRIME_CAP_IMPORT: u32 = 1;
345pub const DRM_PRIME_CAP_EXPORT: u32 = 2;
346pub const DRM_CAP_TIMESTAMP_MONOTONIC: u32 = 6;
347pub const DRM_CAP_ASYNC_PAGE_FLIP: u32 = 7;
348pub const DRM_CAP_CURSOR_WIDTH: u32 = 8;
349pub const DRM_CAP_CURSOR_HEIGHT: u32 = 9;
350pub const DRM_CAP_ADDFB2_MODIFIERS: u32 = 16;
351pub const DRM_CAP_PAGE_FLIP_TARGET: u32 = 17;
352pub const DRM_CAP_CRTC_IN_VBLANK_EVENT: u32 = 18;
353pub const DRM_CAP_SYNCOBJ: u32 = 19;
354pub const DRM_CAP_SYNCOBJ_TIMELINE: u32 = 20;
355pub const DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP: u32 = 21;
356pub const DRM_CLIENT_CAP_STEREO_3D: u32 = 1;
357pub const DRM_CLIENT_CAP_UNIVERSAL_PLANES: u32 = 2;
358pub const DRM_CLIENT_CAP_ATOMIC: u32 = 3;
359pub const DRM_CLIENT_CAP_ASPECT_RATIO: u32 = 4;
360pub const DRM_CLIENT_CAP_WRITEBACK_CONNECTORS: u32 = 5;
361pub const DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT: u32 = 6;
362pub const DRM_SYNCOBJ_CREATE_SIGNALED: u32 = 1;
363pub const DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE: u32 = 1;
364pub const DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE: u32 = 1;
365pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL: u32 = 1;
366pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT: u32 = 2;
367pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE: u32 = 4;
368pub const DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE: u32 = 8;
369pub const DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED: u32 = 1;
370pub const DRM_CRTC_SEQUENCE_RELATIVE: u32 = 1;
371pub const DRM_CRTC_SEQUENCE_NEXT_ON_MISS: u32 = 2;
372pub const DRM_CONNECTOR_NAME_LEN: u32 = 32;
373pub const DRM_DISPLAY_MODE_LEN: u32 = 32;
374pub const DRM_PROP_NAME_LEN: u32 = 32;
375pub const DRM_MODE_TYPE_BUILTIN: u32 = 1;
376pub const DRM_MODE_TYPE_CLOCK_C: u32 = 3;
377pub const DRM_MODE_TYPE_CRTC_C: u32 = 5;
378pub const DRM_MODE_TYPE_PREFERRED: u32 = 8;
379pub const DRM_MODE_TYPE_DEFAULT: u32 = 16;
380pub const DRM_MODE_TYPE_USERDEF: u32 = 32;
381pub const DRM_MODE_TYPE_DRIVER: u32 = 64;
382pub const DRM_MODE_TYPE_ALL: u32 = 104;
383pub const DRM_MODE_FLAG_PHSYNC: u32 = 1;
384pub const DRM_MODE_FLAG_NHSYNC: u32 = 2;
385pub const DRM_MODE_FLAG_PVSYNC: u32 = 4;
386pub const DRM_MODE_FLAG_NVSYNC: u32 = 8;
387pub const DRM_MODE_FLAG_INTERLACE: u32 = 16;
388pub const DRM_MODE_FLAG_DBLSCAN: u32 = 32;
389pub const DRM_MODE_FLAG_CSYNC: u32 = 64;
390pub const DRM_MODE_FLAG_PCSYNC: u32 = 128;
391pub const DRM_MODE_FLAG_NCSYNC: u32 = 256;
392pub const DRM_MODE_FLAG_HSKEW: u32 = 512;
393pub const DRM_MODE_FLAG_BCAST: u32 = 1024;
394pub const DRM_MODE_FLAG_PIXMUX: u32 = 2048;
395pub const DRM_MODE_FLAG_DBLCLK: u32 = 4096;
396pub const DRM_MODE_FLAG_CLKDIV2: u32 = 8192;
397pub const DRM_MODE_FLAG_3D_MASK: u32 = 507904;
398pub const DRM_MODE_FLAG_3D_NONE: u32 = 0;
399pub const DRM_MODE_FLAG_3D_FRAME_PACKING: u32 = 16384;
400pub const DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: u32 = 32768;
401pub const DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: u32 = 49152;
402pub const DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: u32 = 65536;
403pub const DRM_MODE_FLAG_3D_L_DEPTH: u32 = 81920;
404pub const DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: u32 = 98304;
405pub const DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: u32 = 114688;
406pub const DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: u32 = 131072;
407pub const DRM_MODE_PICTURE_ASPECT_NONE: u32 = 0;
408pub const DRM_MODE_PICTURE_ASPECT_4_3: u32 = 1;
409pub const DRM_MODE_PICTURE_ASPECT_16_9: u32 = 2;
410pub const DRM_MODE_PICTURE_ASPECT_64_27: u32 = 3;
411pub const DRM_MODE_PICTURE_ASPECT_256_135: u32 = 4;
412pub const DRM_MODE_CONTENT_TYPE_NO_DATA: u32 = 0;
413pub const DRM_MODE_CONTENT_TYPE_GRAPHICS: u32 = 1;
414pub const DRM_MODE_CONTENT_TYPE_PHOTO: u32 = 2;
415pub const DRM_MODE_CONTENT_TYPE_CINEMA: u32 = 3;
416pub const DRM_MODE_CONTENT_TYPE_GAME: u32 = 4;
417pub const DRM_MODE_FLAG_PIC_AR_MASK: u32 = 7864320;
418pub const DRM_MODE_FLAG_PIC_AR_NONE: u32 = 0;
419pub const DRM_MODE_FLAG_PIC_AR_4_3: u32 = 524288;
420pub const DRM_MODE_FLAG_PIC_AR_16_9: u32 = 1048576;
421pub const DRM_MODE_FLAG_PIC_AR_64_27: u32 = 1572864;
422pub const DRM_MODE_FLAG_PIC_AR_256_135: u32 = 2097152;
423pub const DRM_MODE_FLAG_ALL: u32 = 521215;
424pub const DRM_MODE_DPMS_ON: u32 = 0;
425pub const DRM_MODE_DPMS_STANDBY: u32 = 1;
426pub const DRM_MODE_DPMS_SUSPEND: u32 = 2;
427pub const DRM_MODE_DPMS_OFF: u32 = 3;
428pub const DRM_MODE_SCALE_NONE: u32 = 0;
429pub const DRM_MODE_SCALE_FULLSCREEN: u32 = 1;
430pub const DRM_MODE_SCALE_CENTER: u32 = 2;
431pub const DRM_MODE_SCALE_ASPECT: u32 = 3;
432pub const DRM_MODE_DITHERING_OFF: u32 = 0;
433pub const DRM_MODE_DITHERING_ON: u32 = 1;
434pub const DRM_MODE_DITHERING_AUTO: u32 = 2;
435pub const DRM_MODE_DIRTY_OFF: u32 = 0;
436pub const DRM_MODE_DIRTY_ON: u32 = 1;
437pub const DRM_MODE_DIRTY_ANNOTATE: u32 = 2;
438pub const DRM_MODE_LINK_STATUS_GOOD: u32 = 0;
439pub const DRM_MODE_LINK_STATUS_BAD: u32 = 1;
440pub const DRM_MODE_ROTATE_0: u32 = 1;
441pub const DRM_MODE_ROTATE_90: u32 = 2;
442pub const DRM_MODE_ROTATE_180: u32 = 4;
443pub const DRM_MODE_ROTATE_270: u32 = 8;
444pub const DRM_MODE_ROTATE_MASK: u32 = 15;
445pub const DRM_MODE_REFLECT_X: u32 = 16;
446pub const DRM_MODE_REFLECT_Y: u32 = 32;
447pub const DRM_MODE_REFLECT_MASK: u32 = 48;
448pub const DRM_MODE_CONTENT_PROTECTION_UNDESIRED: u32 = 0;
449pub const DRM_MODE_CONTENT_PROTECTION_DESIRED: u32 = 1;
450pub const DRM_MODE_CONTENT_PROTECTION_ENABLED: u32 = 2;
451pub const DRM_MODE_PRESENT_TOP_FIELD: u32 = 1;
452pub const DRM_MODE_PRESENT_BOTTOM_FIELD: u32 = 2;
453pub const DRM_MODE_ENCODER_NONE: u32 = 0;
454pub const DRM_MODE_ENCODER_DAC: u32 = 1;
455pub const DRM_MODE_ENCODER_TMDS: u32 = 2;
456pub const DRM_MODE_ENCODER_LVDS: u32 = 3;
457pub const DRM_MODE_ENCODER_TVDAC: u32 = 4;
458pub const DRM_MODE_ENCODER_VIRTUAL: u32 = 5;
459pub const DRM_MODE_ENCODER_DSI: u32 = 6;
460pub const DRM_MODE_ENCODER_DPMST: u32 = 7;
461pub const DRM_MODE_ENCODER_DPI: u32 = 8;
462pub const DRM_MODE_CONNECTOR_Unknown: u32 = 0;
463pub const DRM_MODE_CONNECTOR_VGA: u32 = 1;
464pub const DRM_MODE_CONNECTOR_DVII: u32 = 2;
465pub const DRM_MODE_CONNECTOR_DVID: u32 = 3;
466pub const DRM_MODE_CONNECTOR_DVIA: u32 = 4;
467pub const DRM_MODE_CONNECTOR_Composite: u32 = 5;
468pub const DRM_MODE_CONNECTOR_SVIDEO: u32 = 6;
469pub const DRM_MODE_CONNECTOR_LVDS: u32 = 7;
470pub const DRM_MODE_CONNECTOR_Component: u32 = 8;
471pub const DRM_MODE_CONNECTOR_9PinDIN: u32 = 9;
472pub const DRM_MODE_CONNECTOR_DisplayPort: u32 = 10;
473pub const DRM_MODE_CONNECTOR_HDMIA: u32 = 11;
474pub const DRM_MODE_CONNECTOR_HDMIB: u32 = 12;
475pub const DRM_MODE_CONNECTOR_TV: u32 = 13;
476pub const DRM_MODE_CONNECTOR_eDP: u32 = 14;
477pub const DRM_MODE_CONNECTOR_VIRTUAL: u32 = 15;
478pub const DRM_MODE_CONNECTOR_DSI: u32 = 16;
479pub const DRM_MODE_CONNECTOR_DPI: u32 = 17;
480pub const DRM_MODE_CONNECTOR_WRITEBACK: u32 = 18;
481pub const DRM_MODE_CONNECTOR_SPI: u32 = 19;
482pub const DRM_MODE_CONNECTOR_USB: u32 = 20;
483pub const DRM_MODE_PROP_PENDING: u32 = 1;
484pub const DRM_MODE_PROP_RANGE: u32 = 2;
485pub const DRM_MODE_PROP_IMMUTABLE: u32 = 4;
486pub const DRM_MODE_PROP_ENUM: u32 = 8;
487pub const DRM_MODE_PROP_BLOB: u32 = 16;
488pub const DRM_MODE_PROP_BITMASK: u32 = 32;
489pub const DRM_MODE_PROP_LEGACY_TYPE: u32 = 58;
490pub const DRM_MODE_PROP_EXTENDED_TYPE: u32 = 65472;
491pub const DRM_MODE_PROP_ATOMIC: u32 = 2147483648;
492pub const DRM_MODE_OBJECT_CRTC: u32 = 3435973836;
493pub const DRM_MODE_OBJECT_CONNECTOR: u32 = 3233857728;
494pub const DRM_MODE_OBJECT_ENCODER: u32 = 3772834016;
495pub const DRM_MODE_OBJECT_MODE: u32 = 3739147998;
496pub const DRM_MODE_OBJECT_PROPERTY: u32 = 2964369584;
497pub const DRM_MODE_OBJECT_FB: u32 = 4227595259;
498pub const DRM_MODE_OBJECT_BLOB: u32 = 3149642683;
499pub const DRM_MODE_OBJECT_PLANE: u32 = 4008636142;
500pub const DRM_MODE_OBJECT_ANY: u32 = 0;
501pub const DRM_MODE_FB_INTERLACED: u32 = 1;
502pub const DRM_MODE_FB_MODIFIERS: u32 = 2;
503pub const DRM_MODE_FB_DIRTY_ANNOTATE_COPY: u32 = 1;
504pub const DRM_MODE_FB_DIRTY_ANNOTATE_FILL: u32 = 2;
505pub const DRM_MODE_FB_DIRTY_FLAGS: u32 = 3;
506pub const DRM_MODE_FB_DIRTY_MAX_CLIPS: u32 = 256;
507pub const DRM_MODE_CURSOR_BO: u32 = 1;
508pub const DRM_MODE_CURSOR_MOVE: u32 = 2;
509pub const DRM_MODE_CURSOR_FLAGS: u32 = 3;
510pub const DRM_MODE_PAGE_FLIP_EVENT: u32 = 1;
511pub const DRM_MODE_PAGE_FLIP_ASYNC: u32 = 2;
512pub const DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE: u32 = 4;
513pub const DRM_MODE_PAGE_FLIP_TARGET_RELATIVE: u32 = 8;
514pub const DRM_MODE_PAGE_FLIP_TARGET: u32 = 12;
515pub const DRM_MODE_PAGE_FLIP_FLAGS: u32 = 15;
516pub const DRM_MODE_ATOMIC_TEST_ONLY: u32 = 256;
517pub const DRM_MODE_ATOMIC_NONBLOCK: u32 = 512;
518pub const DRM_MODE_ATOMIC_ALLOW_MODESET: u32 = 1024;
519pub const DRM_MODE_ATOMIC_FLAGS: u32 = 1795;
520pub const FORMAT_BLOB_CURRENT: u32 = 1;
521pub const DRM_IOCTL_BASE: u8 = 100u8;
522pub const DRM_COMMAND_BASE: u32 = 64;
523pub const DRM_COMMAND_END: u32 = 160;
524pub const DRM_EVENT_VBLANK: u32 = 1;
525pub const DRM_EVENT_FLIP_COMPLETE: u32 = 2;
526pub const DRM_EVENT_CRTC_SEQUENCE: u32 = 3;
527pub const DRM_MAX_MINOR: u32 = 64;
528pub const DRM_IOC_VOID: u32 = 0;
529pub const DRM_IOC_READ: u32 = 2;
530pub const DRM_IOC_WRITE: u32 = 1;
531pub const DRM_IOC_READWRITE: u32 = 3;
532pub const DRM_DEV_UID: u32 = 0;
533pub const DRM_DEV_GID: u32 = 0;
534pub const DRM_DIR_NAME: &[u8; 9] = b"/dev/dri\0";
535pub const DRM_PRIMARY_MINOR_NAME: &[u8; 5] = b"card\0";
536pub const DRM_CONTROL_MINOR_NAME: &[u8; 9] = b"controlD\0";
537pub const DRM_RENDER_MINOR_NAME: &[u8; 8] = b"renderD\0";
538pub const DRM_PROC_NAME: &[u8; 11] = b"/proc/dri/\0";
539pub const DRM_DEV_NAME: &[u8; 10] = b"%s/card%d\0";
540pub const DRM_CONTROL_DEV_NAME: &[u8; 14] = b"%s/controlD%d\0";
541pub const DRM_RENDER_DEV_NAME: &[u8; 13] = b"%s/renderD%d\0";
542pub const DRM_ERR_NO_DEVICE: i32 = -1001;
543pub const DRM_ERR_NO_ACCESS: i32 = -1002;
544pub const DRM_ERR_NOT_ROOT: i32 = -1003;
545pub const DRM_ERR_INVALID: i32 = -1004;
546pub const DRM_ERR_NO_FD: i32 = -1005;
547pub const DRM_AGP_NO_HANDLE: u32 = 0;
548pub const DRM_VBLANK_HIGH_CRTC_SHIFT: u32 = 1;
549pub const DRM_LOCK_HELD: u32 = 2147483648;
550pub const DRM_LOCK_CONT: u32 = 1073741824;
551pub const DRM_NODE_PRIMARY: u32 = 0;
552pub const DRM_NODE_CONTROL: u32 = 1;
553pub const DRM_NODE_RENDER: u32 = 2;
554pub const DRM_NODE_MAX: u32 = 3;
555pub const DRM_EVENT_CONTEXT_VERSION: u32 = 4;
556pub const DRM_BUS_PCI: u32 = 0;
557pub const DRM_BUS_USB: u32 = 1;
558pub const DRM_BUS_PLATFORM: u32 = 2;
559pub const DRM_BUS_HOST1X: u32 = 3;
560pub const DRM_PLATFORM_DEVICE_NAME_LEN: u32 = 512;
561pub const DRM_HOST1X_DEVICE_NAME_LEN: u32 = 512;
562pub const DRM_DEVICE_GET_PCI_REVISION: u32 = 1;
563pub const __bool_true_false_are_defined: u32 = 1;
564pub const true_: u32 = 1;
565pub const false_: u32 = 0;
566pub const DRM_MODE_FEATURE_KMS: u32 = 1;
567pub const DRM_MODE_FEATURE_DIRTYFB: u32 = 1;
568pub const DRM_PLANE_TYPE_OVERLAY: u32 = 0;
569pub const DRM_PLANE_TYPE_PRIMARY: u32 = 1;
570pub const DRM_PLANE_TYPE_CURSOR: u32 = 2;
571pub const AMDGPU_CS_MAX_IBS_PER_SUBMIT: u32 = 4;
572pub const AMDGPU_TIMEOUT_INFINITE: i32 = -1;
573pub const AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE: u32 = 1;
574pub const AMDGPU_VA_RANGE_32_BIT: u32 = 1;
575pub const AMDGPU_VA_RANGE_HIGH: u32 = 2;
576pub const AMDGPU_VA_RANGE_REPLAYABLE: u32 = 4;
577pub const DRM_AMDGPU_GEM_CREATE: u32 = 0;
578pub const DRM_AMDGPU_GEM_MMAP: u32 = 1;
579pub const DRM_AMDGPU_CTX: u32 = 2;
580pub const DRM_AMDGPU_BO_LIST: u32 = 3;
581pub const DRM_AMDGPU_CS: u32 = 4;
582pub const DRM_AMDGPU_INFO: u32 = 5;
583pub const DRM_AMDGPU_GEM_METADATA: u32 = 6;
584pub const DRM_AMDGPU_GEM_WAIT_IDLE: u32 = 7;
585pub const DRM_AMDGPU_GEM_VA: u32 = 8;
586pub const DRM_AMDGPU_WAIT_CS: u32 = 9;
587pub const DRM_AMDGPU_GEM_OP: u32 = 16;
588pub const DRM_AMDGPU_GEM_USERPTR: u32 = 17;
589pub const DRM_AMDGPU_WAIT_FENCES: u32 = 18;
590pub const DRM_AMDGPU_VM: u32 = 19;
591pub const DRM_AMDGPU_FENCE_TO_HANDLE: u32 = 20;
592pub const DRM_AMDGPU_SCHED: u32 = 21;
593pub const AMDGPU_GEM_DOMAIN_CPU: u32 = 1;
594pub const AMDGPU_GEM_DOMAIN_GTT: u32 = 2;
595pub const AMDGPU_GEM_DOMAIN_VRAM: u32 = 4;
596pub const AMDGPU_GEM_DOMAIN_GDS: u32 = 8;
597pub const AMDGPU_GEM_DOMAIN_GWS: u32 = 16;
598pub const AMDGPU_GEM_DOMAIN_OA: u32 = 32;
599pub const AMDGPU_GEM_DOMAIN_DOORBELL: u32 = 64;
600pub const AMDGPU_GEM_DOMAIN_MASK: u32 = 127;
601pub const AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED: u32 = 1;
602pub const AMDGPU_GEM_CREATE_NO_CPU_ACCESS: u32 = 2;
603pub const AMDGPU_GEM_CREATE_CPU_GTT_USWC: u32 = 4;
604pub const AMDGPU_GEM_CREATE_VRAM_CLEARED: u32 = 8;
605pub const AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS: u32 = 32;
606pub const AMDGPU_GEM_CREATE_VM_ALWAYS_VALID: u32 = 64;
607pub const AMDGPU_GEM_CREATE_EXPLICIT_SYNC: u32 = 128;
608pub const AMDGPU_GEM_CREATE_CP_MQD_GFX9: u32 = 256;
609pub const AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE: u32 = 512;
610pub const AMDGPU_GEM_CREATE_ENCRYPTED: u32 = 1024;
611pub const AMDGPU_GEM_CREATE_PREEMPTIBLE: u32 = 2048;
612pub const AMDGPU_GEM_CREATE_DISCARDABLE: u32 = 4096;
613pub const AMDGPU_GEM_CREATE_COHERENT: u32 = 8192;
614pub const AMDGPU_GEM_CREATE_UNCACHED: u32 = 16384;
615pub const AMDGPU_GEM_CREATE_EXT_COHERENT: u32 = 32768;
616pub const AMDGPU_BO_LIST_OP_CREATE: u32 = 0;
617pub const AMDGPU_BO_LIST_OP_DESTROY: u32 = 1;
618pub const AMDGPU_BO_LIST_OP_UPDATE: u32 = 2;
619pub const AMDGPU_CTX_OP_ALLOC_CTX: u32 = 1;
620pub const AMDGPU_CTX_OP_FREE_CTX: u32 = 2;
621pub const AMDGPU_CTX_OP_QUERY_STATE: u32 = 3;
622pub const AMDGPU_CTX_OP_QUERY_STATE2: u32 = 4;
623pub const AMDGPU_CTX_OP_GET_STABLE_PSTATE: u32 = 5;
624pub const AMDGPU_CTX_OP_SET_STABLE_PSTATE: u32 = 6;
625pub const AMDGPU_CTX_NO_RESET: u32 = 0;
626pub const AMDGPU_CTX_GUILTY_RESET: u32 = 1;
627pub const AMDGPU_CTX_INNOCENT_RESET: u32 = 2;
628pub const AMDGPU_CTX_UNKNOWN_RESET: u32 = 3;
629pub const AMDGPU_CTX_QUERY2_FLAGS_RESET: u32 = 1;
630pub const AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST: u32 = 2;
631pub const AMDGPU_CTX_QUERY2_FLAGS_GUILTY: u32 = 4;
632pub const AMDGPU_CTX_QUERY2_FLAGS_RAS_CE: u32 = 8;
633pub const AMDGPU_CTX_QUERY2_FLAGS_RAS_UE: u32 = 16;
634pub const AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS: u32 = 32;
635pub const AMDGPU_CTX_PRIORITY_UNSET: i32 = -2048;
636pub const AMDGPU_CTX_PRIORITY_VERY_LOW: i32 = -1023;
637pub const AMDGPU_CTX_PRIORITY_LOW: i32 = -512;
638pub const AMDGPU_CTX_PRIORITY_NORMAL: u32 = 0;
639pub const AMDGPU_CTX_PRIORITY_HIGH: u32 = 512;
640pub const AMDGPU_CTX_PRIORITY_VERY_HIGH: u32 = 1023;
641pub const AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK: u32 = 15;
642pub const AMDGPU_CTX_STABLE_PSTATE_NONE: u32 = 0;
643pub const AMDGPU_CTX_STABLE_PSTATE_STANDARD: u32 = 1;
644pub const AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: u32 = 2;
645pub const AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: u32 = 3;
646pub const AMDGPU_CTX_STABLE_PSTATE_PEAK: u32 = 4;
647pub const AMDGPU_VM_OP_RESERVE_VMID: u32 = 1;
648pub const AMDGPU_VM_OP_UNRESERVE_VMID: u32 = 2;
649pub const AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: u32 = 1;
650pub const AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE: u32 = 2;
651pub const AMDGPU_GEM_USERPTR_READONLY: u32 = 1;
652pub const AMDGPU_GEM_USERPTR_ANONONLY: u32 = 2;
653pub const AMDGPU_GEM_USERPTR_VALIDATE: u32 = 4;
654pub const AMDGPU_GEM_USERPTR_REGISTER: u32 = 8;
655pub const AMDGPU_TILING_ARRAY_MODE_SHIFT: u32 = 0;
656pub const AMDGPU_TILING_ARRAY_MODE_MASK: u32 = 15;
657pub const AMDGPU_TILING_PIPE_CONFIG_SHIFT: u32 = 4;
658pub const AMDGPU_TILING_PIPE_CONFIG_MASK: u32 = 31;
659pub const AMDGPU_TILING_TILE_SPLIT_SHIFT: u32 = 9;
660pub const AMDGPU_TILING_TILE_SPLIT_MASK: u32 = 7;
661pub const AMDGPU_TILING_MICRO_TILE_MODE_SHIFT: u32 = 12;
662pub const AMDGPU_TILING_MICRO_TILE_MODE_MASK: u32 = 7;
663pub const AMDGPU_TILING_BANK_WIDTH_SHIFT: u32 = 15;
664pub const AMDGPU_TILING_BANK_WIDTH_MASK: u32 = 3;
665pub const AMDGPU_TILING_BANK_HEIGHT_SHIFT: u32 = 17;
666pub const AMDGPU_TILING_BANK_HEIGHT_MASK: u32 = 3;
667pub const AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT: u32 = 19;
668pub const AMDGPU_TILING_MACRO_TILE_ASPECT_MASK: u32 = 3;
669pub const AMDGPU_TILING_NUM_BANKS_SHIFT: u32 = 21;
670pub const AMDGPU_TILING_NUM_BANKS_MASK: u32 = 3;
671pub const AMDGPU_TILING_SWIZZLE_MODE_SHIFT: u32 = 0;
672pub const AMDGPU_TILING_SWIZZLE_MODE_MASK: u32 = 31;
673pub const AMDGPU_TILING_DCC_OFFSET_256B_SHIFT: u32 = 5;
674pub const AMDGPU_TILING_DCC_OFFSET_256B_MASK: u32 = 16777215;
675pub const AMDGPU_TILING_DCC_PITCH_MAX_SHIFT: u32 = 29;
676pub const AMDGPU_TILING_DCC_PITCH_MAX_MASK: u32 = 16383;
677pub const AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT: u32 = 43;
678pub const AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK: u32 = 1;
679pub const AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT: u32 = 44;
680pub const AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK: u32 = 1;
681pub const AMDGPU_TILING_SCANOUT_SHIFT: u32 = 63;
682pub const AMDGPU_TILING_SCANOUT_MASK: u32 = 1;
683pub const AMDGPU_GEM_METADATA_OP_SET_METADATA: u32 = 1;
684pub const AMDGPU_GEM_METADATA_OP_GET_METADATA: u32 = 2;
685pub const AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: u32 = 0;
686pub const AMDGPU_GEM_OP_SET_PLACEMENT: u32 = 1;
687pub const AMDGPU_VA_OP_MAP: u32 = 1;
688pub const AMDGPU_VA_OP_UNMAP: u32 = 2;
689pub const AMDGPU_VA_OP_CLEAR: u32 = 3;
690pub const AMDGPU_VA_OP_REPLACE: u32 = 4;
691pub const AMDGPU_VM_DELAY_UPDATE: u32 = 1;
692pub const AMDGPU_VM_PAGE_READABLE: u32 = 2;
693pub const AMDGPU_VM_PAGE_WRITEABLE: u32 = 4;
694pub const AMDGPU_VM_PAGE_EXECUTABLE: u32 = 8;
695pub const AMDGPU_VM_PAGE_PRT: u32 = 16;
696pub const AMDGPU_VM_MTYPE_MASK: u32 = 480;
697pub const AMDGPU_VM_MTYPE_DEFAULT: u32 = 0;
698pub const AMDGPU_VM_MTYPE_NC: u32 = 32;
699pub const AMDGPU_VM_MTYPE_WC: u32 = 64;
700pub const AMDGPU_VM_MTYPE_CC: u32 = 96;
701pub const AMDGPU_VM_MTYPE_UC: u32 = 128;
702pub const AMDGPU_VM_MTYPE_RW: u32 = 160;
703pub const AMDGPU_VM_PAGE_NOALLOC: u32 = 512;
704pub const AMDGPU_HW_IP_GFX: u32 = 0;
705pub const AMDGPU_HW_IP_COMPUTE: u32 = 1;
706pub const AMDGPU_HW_IP_DMA: u32 = 2;
707pub const AMDGPU_HW_IP_UVD: u32 = 3;
708pub const AMDGPU_HW_IP_VCE: u32 = 4;
709pub const AMDGPU_HW_IP_UVD_ENC: u32 = 5;
710pub const AMDGPU_HW_IP_VCN_DEC: u32 = 6;
711pub const AMDGPU_HW_IP_VCN_ENC: u32 = 7;
712pub const AMDGPU_HW_IP_VCN_JPEG: u32 = 8;
713pub const AMDGPU_HW_IP_VPE: u32 = 9;
714pub const AMDGPU_HW_IP_NUM: u32 = 10;
715pub const AMDGPU_HW_IP_INSTANCE_MAX_COUNT: u32 = 1;
716pub const AMDGPU_CHUNK_ID_IB: u32 = 1;
717pub const AMDGPU_CHUNK_ID_FENCE: u32 = 2;
718pub const AMDGPU_CHUNK_ID_DEPENDENCIES: u32 = 3;
719pub const AMDGPU_CHUNK_ID_SYNCOBJ_IN: u32 = 4;
720pub const AMDGPU_CHUNK_ID_SYNCOBJ_OUT: u32 = 5;
721pub const AMDGPU_CHUNK_ID_BO_HANDLES: u32 = 6;
722pub const AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: u32 = 7;
723pub const AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: u32 = 8;
724pub const AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: u32 = 9;
725pub const AMDGPU_CHUNK_ID_CP_GFX_SHADOW: u32 = 10;
726pub const AMDGPU_IB_FLAG_CE: u32 = 1;
727pub const AMDGPU_IB_FLAG_PREAMBLE: u32 = 2;
728pub const AMDGPU_IB_FLAG_PREEMPT: u32 = 4;
729pub const AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE: u32 = 8;
730pub const AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID: u32 = 16;
731pub const AMDGPU_IB_FLAGS_SECURE: u32 = 32;
732pub const AMDGPU_IB_FLAG_EMIT_MEM_SYNC: u32 = 64;
733pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ: u32 = 0;
734pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD: u32 = 1;
735pub const AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD: u32 = 2;
736pub const AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW: u32 = 1;
737pub const AMDGPU_IDS_FLAGS_FUSION: u32 = 1;
738pub const AMDGPU_IDS_FLAGS_PREEMPTION: u32 = 2;
739pub const AMDGPU_IDS_FLAGS_TMZ: u32 = 4;
740pub const AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: u32 = 8;
741pub const AMDGPU_INFO_ACCEL_WORKING: u32 = 0;
742pub const AMDGPU_INFO_CRTC_FROM_ID: u32 = 1;
743pub const AMDGPU_INFO_HW_IP_INFO: u32 = 2;
744pub const AMDGPU_INFO_HW_IP_COUNT: u32 = 3;
745pub const AMDGPU_INFO_TIMESTAMP: u32 = 5;
746pub const AMDGPU_INFO_FW_VERSION: u32 = 14;
747pub const AMDGPU_INFO_FW_VCE: u32 = 1;
748pub const AMDGPU_INFO_FW_UVD: u32 = 2;
749pub const AMDGPU_INFO_FW_GMC: u32 = 3;
750pub const AMDGPU_INFO_FW_GFX_ME: u32 = 4;
751pub const AMDGPU_INFO_FW_GFX_PFP: u32 = 5;
752pub const AMDGPU_INFO_FW_GFX_CE: u32 = 6;
753pub const AMDGPU_INFO_FW_GFX_RLC: u32 = 7;
754pub const AMDGPU_INFO_FW_GFX_MEC: u32 = 8;
755pub const AMDGPU_INFO_FW_SMC: u32 = 10;
756pub const AMDGPU_INFO_FW_SDMA: u32 = 11;
757pub const AMDGPU_INFO_FW_SOS: u32 = 12;
758pub const AMDGPU_INFO_FW_ASD: u32 = 13;
759pub const AMDGPU_INFO_FW_VCN: u32 = 14;
760pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: u32 = 15;
761pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: u32 = 16;
762pub const AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: u32 = 17;
763pub const AMDGPU_INFO_FW_DMCU: u32 = 18;
764pub const AMDGPU_INFO_FW_TA: u32 = 19;
765pub const AMDGPU_INFO_FW_DMCUB: u32 = 20;
766pub const AMDGPU_INFO_FW_TOC: u32 = 21;
767pub const AMDGPU_INFO_FW_CAP: u32 = 22;
768pub const AMDGPU_INFO_FW_GFX_RLCP: u32 = 23;
769pub const AMDGPU_INFO_FW_GFX_RLCV: u32 = 24;
770pub const AMDGPU_INFO_FW_MES_KIQ: u32 = 25;
771pub const AMDGPU_INFO_FW_MES: u32 = 26;
772pub const AMDGPU_INFO_FW_IMU: u32 = 27;
773pub const AMDGPU_INFO_FW_VPE: u32 = 28;
774pub const AMDGPU_INFO_NUM_BYTES_MOVED: u32 = 15;
775pub const AMDGPU_INFO_VRAM_USAGE: u32 = 16;
776pub const AMDGPU_INFO_GTT_USAGE: u32 = 17;
777pub const AMDGPU_INFO_GDS_CONFIG: u32 = 19;
778pub const AMDGPU_INFO_VRAM_GTT: u32 = 20;
779pub const AMDGPU_INFO_READ_MMR_REG: u32 = 21;
780pub const AMDGPU_INFO_DEV_INFO: u32 = 22;
781pub const AMDGPU_INFO_VIS_VRAM_USAGE: u32 = 23;
782pub const AMDGPU_INFO_NUM_EVICTIONS: u32 = 24;
783pub const AMDGPU_INFO_MEMORY: u32 = 25;
784pub const AMDGPU_INFO_VCE_CLOCK_TABLE: u32 = 26;
785pub const AMDGPU_INFO_VBIOS: u32 = 27;
786pub const AMDGPU_INFO_VBIOS_SIZE: u32 = 1;
787pub const AMDGPU_INFO_VBIOS_IMAGE: u32 = 2;
788pub const AMDGPU_INFO_VBIOS_INFO: u32 = 3;
789pub const AMDGPU_INFO_NUM_HANDLES: u32 = 28;
790pub const AMDGPU_INFO_SENSOR: u32 = 29;
791pub const AMDGPU_INFO_SENSOR_GFX_SCLK: u32 = 1;
792pub const AMDGPU_INFO_SENSOR_GFX_MCLK: u32 = 2;
793pub const AMDGPU_INFO_SENSOR_GPU_TEMP: u32 = 3;
794pub const AMDGPU_INFO_SENSOR_GPU_LOAD: u32 = 4;
795pub const AMDGPU_INFO_SENSOR_GPU_AVG_POWER: u32 = 5;
796pub const AMDGPU_INFO_SENSOR_VDDNB: u32 = 6;
797pub const AMDGPU_INFO_SENSOR_VDDGFX: u32 = 7;
798pub const AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: u32 = 8;
799pub const AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: u32 = 9;
800pub const AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: u32 = 10;
801pub const AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: u32 = 11;
802pub const AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: u32 = 30;
803pub const AMDGPU_INFO_VRAM_LOST_COUNTER: u32 = 31;
804pub const AMDGPU_INFO_RAS_ENABLED_FEATURES: u32 = 32;
805pub const AMDGPU_INFO_RAS_ENABLED_UMC: u32 = 1;
806pub const AMDGPU_INFO_RAS_ENABLED_SDMA: u32 = 2;
807pub const AMDGPU_INFO_RAS_ENABLED_GFX: u32 = 4;
808pub const AMDGPU_INFO_RAS_ENABLED_MMHUB: u32 = 8;
809pub const AMDGPU_INFO_RAS_ENABLED_ATHUB: u32 = 16;
810pub const AMDGPU_INFO_RAS_ENABLED_PCIE: u32 = 32;
811pub const AMDGPU_INFO_RAS_ENABLED_HDP: u32 = 64;
812pub const AMDGPU_INFO_RAS_ENABLED_XGMI: u32 = 128;
813pub const AMDGPU_INFO_RAS_ENABLED_DF: u32 = 256;
814pub const AMDGPU_INFO_RAS_ENABLED_SMN: u32 = 512;
815pub const AMDGPU_INFO_RAS_ENABLED_SEM: u32 = 1024;
816pub const AMDGPU_INFO_RAS_ENABLED_MP0: u32 = 2048;
817pub const AMDGPU_INFO_RAS_ENABLED_MP1: u32 = 4096;
818pub const AMDGPU_INFO_RAS_ENABLED_FUSE: u32 = 8192;
819pub const AMDGPU_INFO_VIDEO_CAPS: u32 = 33;
820pub const AMDGPU_INFO_VIDEO_CAPS_DECODE: u32 = 0;
821pub const AMDGPU_INFO_VIDEO_CAPS_ENCODE: u32 = 1;
822pub const AMDGPU_INFO_MAX_IBS: u32 = 34;
823pub const AMDGPU_INFO_GPUVM_FAULT: u32 = 35;
824pub const AMDGPU_INFO_MMR_SE_INDEX_SHIFT: u32 = 0;
825pub const AMDGPU_INFO_MMR_SE_INDEX_MASK: u32 = 255;
826pub const AMDGPU_INFO_MMR_SH_INDEX_SHIFT: u32 = 8;
827pub const AMDGPU_INFO_MMR_SH_INDEX_MASK: u32 = 255;
828pub const AMDGPU_VRAM_TYPE_UNKNOWN: u32 = 0;
829pub const AMDGPU_VRAM_TYPE_GDDR1: u32 = 1;
830pub const AMDGPU_VRAM_TYPE_DDR2: u32 = 2;
831pub const AMDGPU_VRAM_TYPE_GDDR3: u32 = 3;
832pub const AMDGPU_VRAM_TYPE_GDDR4: u32 = 4;
833pub const AMDGPU_VRAM_TYPE_GDDR5: u32 = 5;
834pub const AMDGPU_VRAM_TYPE_HBM: u32 = 6;
835pub const AMDGPU_VRAM_TYPE_DDR3: u32 = 7;
836pub const AMDGPU_VRAM_TYPE_DDR4: u32 = 8;
837pub const AMDGPU_VRAM_TYPE_GDDR6: u32 = 9;
838pub const AMDGPU_VRAM_TYPE_DDR5: u32 = 10;
839pub const AMDGPU_VRAM_TYPE_LPDDR4: u32 = 11;
840pub const AMDGPU_VRAM_TYPE_LPDDR5: u32 = 12;
841pub const AMDGPU_VCE_CLOCK_TABLE_ENTRIES: u32 = 6;
842pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: u32 = 0;
843pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: u32 = 1;
844pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: u32 = 2;
845pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: u32 = 3;
846pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: u32 = 4;
847pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: u32 = 5;
848pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: u32 = 6;
849pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: u32 = 7;
850pub const AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT: u32 = 8;
851pub const AMDGPU_VMHUB_TYPE_MASK: u32 = 255;
852pub const AMDGPU_VMHUB_TYPE_SHIFT: u32 = 0;
853pub const AMDGPU_VMHUB_TYPE_GFX: u32 = 0;
854pub const AMDGPU_VMHUB_TYPE_MM0: u32 = 1;
855pub const AMDGPU_VMHUB_TYPE_MM1: u32 = 2;
856pub const AMDGPU_VMHUB_IDX_MASK: u32 = 65280;
857pub const AMDGPU_VMHUB_IDX_SHIFT: u32 = 8;
858pub const AMDGPU_FAMILY_UNKNOWN: u32 = 0;
859pub const AMDGPU_FAMILY_SI: u32 = 110;
860pub const AMDGPU_FAMILY_CI: u32 = 120;
861pub const AMDGPU_FAMILY_KV: u32 = 125;
862pub const AMDGPU_FAMILY_VI: u32 = 130;
863pub const AMDGPU_FAMILY_CZ: u32 = 135;
864pub const AMDGPU_FAMILY_AI: u32 = 141;
865pub const AMDGPU_FAMILY_RV: u32 = 142;
866pub const AMDGPU_FAMILY_NV: u32 = 143;
867pub const AMDGPU_FAMILY_VGH: u32 = 144;
868pub const AMDGPU_FAMILY_GC_11_0_0: u32 = 145;
869pub const AMDGPU_FAMILY_YC: u32 = 146;
870pub const AMDGPU_FAMILY_GC_11_0_1: u32 = 148;
871pub const AMDGPU_FAMILY_GC_10_3_6: u32 = 149;
872pub const AMDGPU_FAMILY_GC_10_3_7: u32 = 151;
873pub const AMDGPU_FAMILY_GC_11_5_0: u32 = 150;
874pub const BIOS_ATOM_PREFIX: &[u8; 9] = b"ATOMBIOS\0";
875pub const BIOS_VERSION_PREFIX: &[u8; 15] = b"ATOMBIOSBK-AMD\0";
876pub const BIOS_STRING_LENGTH: u32 = 43;
877pub const NUM_HBM_INSTANCES: u32 = 4;
878pub const NUM_XGMI_LINKS: u32 = 8;
879pub const MAX_GFX_CLKS: u32 = 8;
880pub const MAX_CLKS: u32 = 4;
881pub const NUM_VCN: u32 = 4;
882pub const NUM_JPEG_ENG: u32 = 32;
883pub type __gnuc_va_list = __builtin_va_list;
884pub type va_list = __builtin_va_list;
885pub type __u_char = ::core::ffi::c_uchar;
886pub type __u_short = ::core::ffi::c_ushort;
887pub type __u_int = ::core::ffi::c_uint;
888pub type __u_long = ::core::ffi::c_ulong;
889pub type __int8_t = ::core::ffi::c_schar;
890pub type __uint8_t = ::core::ffi::c_uchar;
891pub type __int16_t = ::core::ffi::c_short;
892pub type __uint16_t = ::core::ffi::c_ushort;
893pub type __int32_t = ::core::ffi::c_int;
894pub type __uint32_t = ::core::ffi::c_uint;
895pub type __int64_t = ::core::ffi::c_long;
896pub type __uint64_t = ::core::ffi::c_ulong;
897pub type __int_least8_t = __int8_t;
898pub type __uint_least8_t = __uint8_t;
899pub type __int_least16_t = __int16_t;
900pub type __uint_least16_t = __uint16_t;
901pub type __int_least32_t = __int32_t;
902pub type __uint_least32_t = __uint32_t;
903pub type __int_least64_t = __int64_t;
904pub type __uint_least64_t = __uint64_t;
905pub type __quad_t = ::core::ffi::c_long;
906pub type __u_quad_t = ::core::ffi::c_ulong;
907pub type __intmax_t = ::core::ffi::c_long;
908pub type __uintmax_t = ::core::ffi::c_ulong;
909pub type __dev_t = ::core::ffi::c_ulong;
910pub type __uid_t = ::core::ffi::c_uint;
911pub type __gid_t = ::core::ffi::c_uint;
912pub type __ino_t = ::core::ffi::c_ulong;
913pub type __ino64_t = ::core::ffi::c_ulong;
914pub type __mode_t = ::core::ffi::c_uint;
915pub type __nlink_t = ::core::ffi::c_ulong;
916pub type __off_t = ::core::ffi::c_long;
917pub type __off64_t = ::core::ffi::c_long;
918pub type __pid_t = ::core::ffi::c_int;
919#[repr(C)]
920#[derive(Debug, Copy, Clone)]
921pub struct __fsid_t {
922 pub __val: [::core::ffi::c_int; 2usize],
923}
924pub type __clock_t = ::core::ffi::c_long;
925pub type __rlim_t = ::core::ffi::c_ulong;
926pub type __rlim64_t = ::core::ffi::c_ulong;
927pub type __id_t = ::core::ffi::c_uint;
928pub type __time_t = ::core::ffi::c_long;
929pub type __useconds_t = ::core::ffi::c_uint;
930pub type __suseconds_t = ::core::ffi::c_long;
931pub type __suseconds64_t = ::core::ffi::c_long;
932pub type __daddr_t = ::core::ffi::c_int;
933pub type __key_t = ::core::ffi::c_int;
934pub type __clockid_t = ::core::ffi::c_int;
935pub type __timer_t = *mut ::core::ffi::c_void;
936pub type __blksize_t = ::core::ffi::c_long;
937pub type __blkcnt_t = ::core::ffi::c_long;
938pub type __blkcnt64_t = ::core::ffi::c_long;
939pub type __fsblkcnt_t = ::core::ffi::c_ulong;
940pub type __fsblkcnt64_t = ::core::ffi::c_ulong;
941pub type __fsfilcnt_t = ::core::ffi::c_ulong;
942pub type __fsfilcnt64_t = ::core::ffi::c_ulong;
943pub type __fsword_t = ::core::ffi::c_long;
944pub type __ssize_t = ::core::ffi::c_long;
945pub type __syscall_slong_t = ::core::ffi::c_long;
946pub type __syscall_ulong_t = ::core::ffi::c_ulong;
947pub type __loff_t = __off64_t;
948pub type __caddr_t = *mut ::core::ffi::c_char;
949pub type __intptr_t = ::core::ffi::c_long;
950pub type __socklen_t = ::core::ffi::c_uint;
951pub type __sig_atomic_t = ::core::ffi::c_int;
952pub type u_char = __u_char;
953pub type u_short = __u_short;
954pub type u_int = __u_int;
955pub type u_long = __u_long;
956pub type quad_t = __quad_t;
957pub type u_quad_t = __u_quad_t;
958pub type fsid_t = __fsid_t;
959pub type loff_t = __loff_t;
960pub type ino_t = __ino_t;
961pub type dev_t = __dev_t;
962pub type gid_t = __gid_t;
963pub type mode_t = __mode_t;
964pub type nlink_t = __nlink_t;
965pub type uid_t = __uid_t;
966pub type off_t = __off_t;
967pub type pid_t = __pid_t;
968pub type id_t = __id_t;
969pub type daddr_t = __daddr_t;
970pub type caddr_t = __caddr_t;
971pub type key_t = __key_t;
972pub type clock_t = __clock_t;
973pub type clockid_t = __clockid_t;
974pub type time_t = __time_t;
975pub type timer_t = __timer_t;
976pub type ulong = ::core::ffi::c_ulong;
977pub type ushort = ::core::ffi::c_ushort;
978pub type uint = ::core::ffi::c_uint;
979pub type u_int8_t = __uint8_t;
980pub type u_int16_t = __uint16_t;
981pub type u_int32_t = __uint32_t;
982pub type u_int64_t = __uint64_t;
983pub type register_t = ::core::ffi::c_long;
984#[repr(C)]
985#[derive(Debug, Copy, Clone)]
986pub struct __sigset_t {
987 pub __val: [::core::ffi::c_ulong; 16usize],
988}
989pub type sigset_t = __sigset_t;
990#[repr(C)]
991#[derive(Debug, Copy, Clone)]
992pub struct timeval {
993 pub tv_sec: __time_t,
994 pub tv_usec: __suseconds_t,
995}
996#[repr(C)]
997#[derive(Debug, Copy, Clone)]
998pub struct timespec {
999 pub tv_sec: __time_t,
1000 pub tv_nsec: __syscall_slong_t,
1001}
1002pub type suseconds_t = __suseconds_t;
1003pub type __fd_mask = ::core::ffi::c_long;
1004#[repr(C)]
1005#[derive(Debug, Copy, Clone)]
1006pub struct fd_set {
1007 pub __fds_bits: [__fd_mask; 16usize],
1008}
1009pub type fd_mask = __fd_mask;
1010unsafe extern "C" {
1011 pub fn select(
1012 __nfds: ::core::ffi::c_int,
1013 __readfds: *mut fd_set,
1014 __writefds: *mut fd_set,
1015 __exceptfds: *mut fd_set,
1016 __timeout: *mut timeval,
1017 ) -> ::core::ffi::c_int;
1018}
1019unsafe extern "C" {
1020 pub fn pselect(
1021 __nfds: ::core::ffi::c_int,
1022 __readfds: *mut fd_set,
1023 __writefds: *mut fd_set,
1024 __exceptfds: *mut fd_set,
1025 __timeout: *const timespec,
1026 __sigmask: *const __sigset_t,
1027 ) -> ::core::ffi::c_int;
1028}
1029pub type blksize_t = __blksize_t;
1030pub type blkcnt_t = __blkcnt_t;
1031pub type fsblkcnt_t = __fsblkcnt_t;
1032pub type fsfilcnt_t = __fsfilcnt_t;
1033#[repr(C)]
1034#[derive(Copy, Clone)]
1035pub union __atomic_wide_counter {
1036 pub __value64: ::core::ffi::c_ulonglong,
1037 pub __value32: __atomic_wide_counter__bindgen_ty_1,
1038}
1039#[repr(C)]
1040#[derive(Debug, Copy, Clone)]
1041pub struct __atomic_wide_counter__bindgen_ty_1 {
1042 pub __low: ::core::ffi::c_uint,
1043 pub __high: ::core::ffi::c_uint,
1044}
1045#[repr(C)]
1046#[derive(Debug, Copy, Clone)]
1047pub struct __pthread_internal_list {
1048 pub __prev: *mut __pthread_internal_list,
1049 pub __next: *mut __pthread_internal_list,
1050}
1051pub type __pthread_list_t = __pthread_internal_list;
1052#[repr(C)]
1053#[derive(Debug, Copy, Clone)]
1054pub struct __pthread_internal_slist {
1055 pub __next: *mut __pthread_internal_slist,
1056}
1057pub type __pthread_slist_t = __pthread_internal_slist;
1058#[repr(C)]
1059#[derive(Debug, Copy, Clone)]
1060pub struct __pthread_mutex_s {
1061 pub __lock: ::core::ffi::c_int,
1062 pub __count: ::core::ffi::c_uint,
1063 pub __owner: ::core::ffi::c_int,
1064 pub __nusers: ::core::ffi::c_uint,
1065 pub __kind: ::core::ffi::c_int,
1066 pub __spins: ::core::ffi::c_short,
1067 pub __elision: ::core::ffi::c_short,
1068 pub __list: __pthread_list_t,
1069}
1070#[repr(C)]
1071#[derive(Debug, Copy, Clone)]
1072pub struct __pthread_rwlock_arch_t {
1073 pub __readers: ::core::ffi::c_uint,
1074 pub __writers: ::core::ffi::c_uint,
1075 pub __wrphase_futex: ::core::ffi::c_uint,
1076 pub __writers_futex: ::core::ffi::c_uint,
1077 pub __pad3: ::core::ffi::c_uint,
1078 pub __pad4: ::core::ffi::c_uint,
1079 pub __cur_writer: ::core::ffi::c_int,
1080 pub __shared: ::core::ffi::c_int,
1081 pub __rwelision: ::core::ffi::c_schar,
1082 pub __pad1: [::core::ffi::c_uchar; 7usize],
1083 pub __pad2: ::core::ffi::c_ulong,
1084 pub __flags: ::core::ffi::c_uint,
1085}
1086#[repr(C)]
1087#[derive(Copy, Clone)]
1088pub struct __pthread_cond_s {
1089 pub __wseq: __atomic_wide_counter,
1090 pub __g1_start: __atomic_wide_counter,
1091 pub __g_size: [::core::ffi::c_uint; 2usize],
1092 pub __g1_orig_size: ::core::ffi::c_uint,
1093 pub __wrefs: ::core::ffi::c_uint,
1094 pub __g_signals: [::core::ffi::c_uint; 2usize],
1095 pub __unused_initialized_1: ::core::ffi::c_uint,
1096 pub __unused_initialized_2: ::core::ffi::c_uint,
1097}
1098pub type __tss_t = ::core::ffi::c_uint;
1099pub type __thrd_t = ::core::ffi::c_ulong;
1100#[repr(C)]
1101#[derive(Debug, Copy, Clone)]
1102pub struct __once_flag {
1103 pub __data: ::core::ffi::c_int,
1104}
1105pub type pthread_t = ::core::ffi::c_ulong;
1106#[repr(C)]
1107#[derive(Copy, Clone)]
1108pub union pthread_mutexattr_t {
1109 pub __size: [::core::ffi::c_char; 4usize],
1110 pub __align: ::core::ffi::c_int,
1111}
1112#[repr(C)]
1113#[derive(Copy, Clone)]
1114pub union pthread_condattr_t {
1115 pub __size: [::core::ffi::c_char; 4usize],
1116 pub __align: ::core::ffi::c_int,
1117}
1118pub type pthread_key_t = ::core::ffi::c_uint;
1119pub type pthread_once_t = ::core::ffi::c_int;
1120#[repr(C)]
1121#[derive(Copy, Clone)]
1122pub union pthread_attr_t {
1123 pub __size: [::core::ffi::c_char; 56usize],
1124 pub __align: ::core::ffi::c_long,
1125}
1126#[repr(C)]
1127#[derive(Copy, Clone)]
1128pub union pthread_mutex_t {
1129 pub __data: __pthread_mutex_s,
1130 pub __size: [::core::ffi::c_char; 40usize],
1131 pub __align: ::core::ffi::c_long,
1132}
1133#[repr(C)]
1134#[derive(Copy, Clone)]
1135pub union pthread_cond_t {
1136 pub __data: __pthread_cond_s,
1137 pub __size: [::core::ffi::c_char; 48usize],
1138 pub __align: ::core::ffi::c_longlong,
1139}
1140#[repr(C)]
1141#[derive(Copy, Clone)]
1142pub union pthread_rwlock_t {
1143 pub __data: __pthread_rwlock_arch_t,
1144 pub __size: [::core::ffi::c_char; 56usize],
1145 pub __align: ::core::ffi::c_long,
1146}
1147#[repr(C)]
1148#[derive(Copy, Clone)]
1149pub union pthread_rwlockattr_t {
1150 pub __size: [::core::ffi::c_char; 8usize],
1151 pub __align: ::core::ffi::c_long,
1152}
1153pub type pthread_spinlock_t = ::core::ffi::c_int;
1154#[repr(C)]
1155#[derive(Copy, Clone)]
1156pub union pthread_barrier_t {
1157 pub __size: [::core::ffi::c_char; 32usize],
1158 pub __align: ::core::ffi::c_long,
1159}
1160#[repr(C)]
1161#[derive(Copy, Clone)]
1162pub union pthread_barrierattr_t {
1163 pub __size: [::core::ffi::c_char; 4usize],
1164 pub __align: ::core::ffi::c_int,
1165}
1166pub type int_least8_t = __int_least8_t;
1167pub type int_least16_t = __int_least16_t;
1168pub type int_least32_t = __int_least32_t;
1169pub type int_least64_t = __int_least64_t;
1170pub type uint_least8_t = __uint_least8_t;
1171pub type uint_least16_t = __uint_least16_t;
1172pub type uint_least32_t = __uint_least32_t;
1173pub type uint_least64_t = __uint_least64_t;
1174pub type int_fast8_t = ::core::ffi::c_schar;
1175pub type int_fast16_t = ::core::ffi::c_long;
1176pub type int_fast32_t = ::core::ffi::c_long;
1177pub type int_fast64_t = ::core::ffi::c_long;
1178pub type uint_fast8_t = ::core::ffi::c_uchar;
1179pub type uint_fast16_t = ::core::ffi::c_ulong;
1180pub type uint_fast32_t = ::core::ffi::c_ulong;
1181pub type uint_fast64_t = ::core::ffi::c_ulong;
1182pub type intmax_t = __intmax_t;
1183pub type uintmax_t = __uintmax_t;
1184pub type __s8 = ::core::ffi::c_schar;
1185pub type __u8 = ::core::ffi::c_uchar;
1186pub type __s16 = ::core::ffi::c_short;
1187pub type __u16 = ::core::ffi::c_ushort;
1188pub type __s32 = ::core::ffi::c_int;
1189pub type __u32 = ::core::ffi::c_uint;
1190pub type __s64 = ::core::ffi::c_longlong;
1191pub type __u64 = ::core::ffi::c_ulonglong;
1192#[repr(C)]
1193#[derive(Debug, Copy, Clone)]
1194pub struct __kernel_fd_set {
1195 pub fds_bits: [::core::ffi::c_ulong; 16usize],
1196}
1197pub type __kernel_sighandler_t =
1198 ::core::option::Option<unsafe extern "C" fn(arg1: ::core::ffi::c_int)>;
1199pub type __kernel_key_t = ::core::ffi::c_int;
1200pub type __kernel_mqd_t = ::core::ffi::c_int;
1201pub type __kernel_old_uid_t = ::core::ffi::c_ushort;
1202pub type __kernel_old_gid_t = ::core::ffi::c_ushort;
1203pub type __kernel_old_dev_t = ::core::ffi::c_ulong;
1204pub type __kernel_long_t = ::core::ffi::c_long;
1205pub type __kernel_ulong_t = ::core::ffi::c_ulong;
1206pub type __kernel_ino_t = __kernel_ulong_t;
1207pub type __kernel_mode_t = ::core::ffi::c_uint;
1208pub type __kernel_pid_t = ::core::ffi::c_int;
1209pub type __kernel_ipc_pid_t = ::core::ffi::c_int;
1210pub type __kernel_uid_t = ::core::ffi::c_uint;
1211pub type __kernel_gid_t = ::core::ffi::c_uint;
1212pub type __kernel_suseconds_t = __kernel_long_t;
1213pub type __kernel_daddr_t = ::core::ffi::c_int;
1214pub type __kernel_uid32_t = ::core::ffi::c_uint;
1215pub type __kernel_gid32_t = ::core::ffi::c_uint;
1216pub type __kernel_size_t = __kernel_ulong_t;
1217pub type __kernel_ssize_t = __kernel_long_t;
1218pub type __kernel_ptrdiff_t = __kernel_long_t;
1219#[repr(C)]
1220#[derive(Debug, Copy, Clone)]
1221pub struct __kernel_fsid_t {
1222 pub val: [::core::ffi::c_int; 2usize],
1223}
1224pub type __kernel_off_t = __kernel_long_t;
1225pub type __kernel_loff_t = ::core::ffi::c_longlong;
1226pub type __kernel_old_time_t = __kernel_long_t;
1227pub type __kernel_time_t = __kernel_long_t;
1228pub type __kernel_time64_t = ::core::ffi::c_longlong;
1229pub type __kernel_clock_t = __kernel_long_t;
1230pub type __kernel_timer_t = ::core::ffi::c_int;
1231pub type __kernel_clockid_t = ::core::ffi::c_int;
1232pub type __kernel_caddr_t = *mut ::core::ffi::c_char;
1233pub type __kernel_uid16_t = ::core::ffi::c_ushort;
1234pub type __kernel_gid16_t = ::core::ffi::c_ushort;
1235pub type __s128 = i128;
1236pub type __u128 = u128;
1237pub type __le16 = __u16;
1238pub type __be16 = __u16;
1239pub type __le32 = __u32;
1240pub type __be32 = __u32;
1241pub type __le64 = __u64;
1242pub type __be64 = __u64;
1243pub type __sum16 = __u16;
1244pub type __wsum = __u32;
1245pub type __poll_t = ::core::ffi::c_uint;
1246pub type drm_handle_t = ::core::ffi::c_uint;
1247pub type drm_context_t = ::core::ffi::c_uint;
1248pub type drm_drawable_t = ::core::ffi::c_uint;
1249pub type drm_magic_t = ::core::ffi::c_uint;
1250#[repr(C)]
1251#[derive(Debug, Copy, Clone)]
1252pub struct drm_clip_rect {
1253 pub x1: ::core::ffi::c_ushort,
1254 pub y1: ::core::ffi::c_ushort,
1255 pub x2: ::core::ffi::c_ushort,
1256 pub y2: ::core::ffi::c_ushort,
1257}
1258#[repr(C)]
1259#[derive(Debug, Copy, Clone)]
1260pub struct drm_drawable_info {
1261 pub num_rects: ::core::ffi::c_uint,
1262 pub rects: *mut drm_clip_rect,
1263}
1264#[repr(C)]
1265#[derive(Debug, Copy, Clone)]
1266pub struct drm_tex_region {
1267 pub next: ::core::ffi::c_uchar,
1268 pub prev: ::core::ffi::c_uchar,
1269 pub in_use: ::core::ffi::c_uchar,
1270 pub padding: ::core::ffi::c_uchar,
1271 pub age: ::core::ffi::c_uint,
1272}
1273#[repr(C)]
1274#[derive(Debug, Copy, Clone)]
1275pub struct drm_hw_lock {
1276 pub lock: ::core::ffi::c_uint,
1277 pub padding: [::core::ffi::c_char; 60usize],
1278}
1279#[repr(C)]
1280#[derive(Debug, Copy, Clone)]
1281pub struct drm_version {
1282 pub version_major: ::core::ffi::c_int,
1283 pub version_minor: ::core::ffi::c_int,
1284 pub version_patchlevel: ::core::ffi::c_int,
1285 pub name_len: __kernel_size_t,
1286 pub name: *mut ::core::ffi::c_char,
1287 pub date_len: __kernel_size_t,
1288 pub date: *mut ::core::ffi::c_char,
1289 pub desc_len: __kernel_size_t,
1290 pub desc: *mut ::core::ffi::c_char,
1291}
1292#[repr(C)]
1293#[derive(Debug, Copy, Clone)]
1294pub struct drm_unique {
1295 pub unique_len: __kernel_size_t,
1296 pub unique: *mut ::core::ffi::c_char,
1297}
1298#[repr(C)]
1299#[derive(Debug, Copy, Clone)]
1300pub struct drm_list {
1301 pub count: ::core::ffi::c_int,
1302 pub version: *mut drm_version,
1303}
1304#[repr(C)]
1305#[derive(Debug, Copy, Clone)]
1306pub struct drm_block {
1307 pub unused: ::core::ffi::c_int,
1308}
1309#[repr(C)]
1310#[derive(Debug, Copy, Clone)]
1311pub struct drm_control {
1312 pub func: drm_control__bindgen_ty_1,
1313 pub irq: ::core::ffi::c_int,
1314}
1315pub const drm_control_DRM_ADD_COMMAND: drm_control__bindgen_ty_1 = 0;
1316pub const drm_control_DRM_RM_COMMAND: drm_control__bindgen_ty_1 = 1;
1317pub const drm_control_DRM_INST_HANDLER: drm_control__bindgen_ty_1 = 2;
1318pub const drm_control_DRM_UNINST_HANDLER: drm_control__bindgen_ty_1 = 3;
1319pub type drm_control__bindgen_ty_1 = ::core::ffi::c_uint;
1320pub const drm_map_type__DRM_FRAME_BUFFER: drm_map_type = 0;
1321pub const drm_map_type__DRM_REGISTERS: drm_map_type = 1;
1322pub const drm_map_type__DRM_SHM: drm_map_type = 2;
1323pub const drm_map_type__DRM_AGP: drm_map_type = 3;
1324pub const drm_map_type__DRM_SCATTER_GATHER: drm_map_type = 4;
1325pub const drm_map_type__DRM_CONSISTENT: drm_map_type = 5;
1326pub type drm_map_type = ::core::ffi::c_uint;
1327pub const drm_map_flags__DRM_RESTRICTED: drm_map_flags = 1;
1328pub const drm_map_flags__DRM_READ_ONLY: drm_map_flags = 2;
1329pub const drm_map_flags__DRM_LOCKED: drm_map_flags = 4;
1330pub const drm_map_flags__DRM_KERNEL: drm_map_flags = 8;
1331pub const drm_map_flags__DRM_WRITE_COMBINING: drm_map_flags = 16;
1332pub const drm_map_flags__DRM_CONTAINS_LOCK: drm_map_flags = 32;
1333pub const drm_map_flags__DRM_REMOVABLE: drm_map_flags = 64;
1334pub const drm_map_flags__DRM_DRIVER: drm_map_flags = 128;
1335pub type drm_map_flags = ::core::ffi::c_uint;
1336#[repr(C)]
1337#[derive(Debug, Copy, Clone)]
1338pub struct drm_ctx_priv_map {
1339 pub ctx_id: ::core::ffi::c_uint,
1340 pub handle: *mut ::core::ffi::c_void,
1341}
1342#[repr(C)]
1343#[derive(Debug, Copy, Clone)]
1344pub struct drm_map {
1345 pub offset: ::core::ffi::c_ulong,
1346 pub size: ::core::ffi::c_ulong,
1347 pub type_: drm_map_type,
1348 pub flags: drm_map_flags,
1349 pub handle: *mut ::core::ffi::c_void,
1350 pub mtrr: ::core::ffi::c_int,
1351}
1352#[repr(C)]
1353#[derive(Debug, Copy, Clone)]
1354pub struct drm_client {
1355 pub idx: ::core::ffi::c_int,
1356 pub auth: ::core::ffi::c_int,
1357 pub pid: ::core::ffi::c_ulong,
1358 pub uid: ::core::ffi::c_ulong,
1359 pub magic: ::core::ffi::c_ulong,
1360 pub iocs: ::core::ffi::c_ulong,
1361}
1362pub const drm_stat_type__DRM_STAT_LOCK: drm_stat_type = 0;
1363pub const drm_stat_type__DRM_STAT_OPENS: drm_stat_type = 1;
1364pub const drm_stat_type__DRM_STAT_CLOSES: drm_stat_type = 2;
1365pub const drm_stat_type__DRM_STAT_IOCTLS: drm_stat_type = 3;
1366pub const drm_stat_type__DRM_STAT_LOCKS: drm_stat_type = 4;
1367pub const drm_stat_type__DRM_STAT_UNLOCKS: drm_stat_type = 5;
1368pub const drm_stat_type__DRM_STAT_VALUE: drm_stat_type = 6;
1369pub const drm_stat_type__DRM_STAT_BYTE: drm_stat_type = 7;
1370pub const drm_stat_type__DRM_STAT_COUNT: drm_stat_type = 8;
1371pub const drm_stat_type__DRM_STAT_IRQ: drm_stat_type = 9;
1372pub const drm_stat_type__DRM_STAT_PRIMARY: drm_stat_type = 10;
1373pub const drm_stat_type__DRM_STAT_SECONDARY: drm_stat_type = 11;
1374pub const drm_stat_type__DRM_STAT_DMA: drm_stat_type = 12;
1375pub const drm_stat_type__DRM_STAT_SPECIAL: drm_stat_type = 13;
1376pub const drm_stat_type__DRM_STAT_MISSED: drm_stat_type = 14;
1377pub type drm_stat_type = ::core::ffi::c_uint;
1378#[repr(C)]
1379#[derive(Debug, Copy, Clone)]
1380pub struct drm_stats {
1381 pub count: ::core::ffi::c_ulong,
1382 pub data: [drm_stats__bindgen_ty_1; 15usize],
1383}
1384#[repr(C)]
1385#[derive(Debug, Copy, Clone)]
1386pub struct drm_stats__bindgen_ty_1 {
1387 pub value: ::core::ffi::c_ulong,
1388 pub type_: drm_stat_type,
1389}
1390pub const drm_lock_flags__DRM_LOCK_READY: drm_lock_flags = 1;
1391pub const drm_lock_flags__DRM_LOCK_QUIESCENT: drm_lock_flags = 2;
1392pub const drm_lock_flags__DRM_LOCK_FLUSH: drm_lock_flags = 4;
1393pub const drm_lock_flags__DRM_LOCK_FLUSH_ALL: drm_lock_flags = 8;
1394pub const drm_lock_flags__DRM_HALT_ALL_QUEUES: drm_lock_flags = 16;
1395pub const drm_lock_flags__DRM_HALT_CUR_QUEUES: drm_lock_flags = 32;
1396pub type drm_lock_flags = ::core::ffi::c_uint;
1397#[repr(C)]
1398#[derive(Debug, Copy, Clone)]
1399pub struct drm_lock {
1400 pub context: ::core::ffi::c_int,
1401 pub flags: drm_lock_flags,
1402}
1403pub const drm_dma_flags__DRM_DMA_BLOCK: drm_dma_flags = 1;
1404pub const drm_dma_flags__DRM_DMA_WHILE_LOCKED: drm_dma_flags = 2;
1405pub const drm_dma_flags__DRM_DMA_PRIORITY: drm_dma_flags = 4;
1406pub const drm_dma_flags__DRM_DMA_WAIT: drm_dma_flags = 16;
1407pub const drm_dma_flags__DRM_DMA_SMALLER_OK: drm_dma_flags = 32;
1408pub const drm_dma_flags__DRM_DMA_LARGER_OK: drm_dma_flags = 64;
1409pub type drm_dma_flags = ::core::ffi::c_uint;
1410#[repr(C)]
1411#[derive(Debug, Copy, Clone)]
1412pub struct drm_buf_desc {
1413 pub count: ::core::ffi::c_int,
1414 pub size: ::core::ffi::c_int,
1415 pub low_mark: ::core::ffi::c_int,
1416 pub high_mark: ::core::ffi::c_int,
1417 pub flags: drm_buf_desc__bindgen_ty_1,
1418 pub agp_start: ::core::ffi::c_ulong,
1419}
1420pub const drm_buf_desc__DRM_PAGE_ALIGN: drm_buf_desc__bindgen_ty_1 = 1;
1421pub const drm_buf_desc__DRM_AGP_BUFFER: drm_buf_desc__bindgen_ty_1 = 2;
1422pub const drm_buf_desc__DRM_SG_BUFFER: drm_buf_desc__bindgen_ty_1 = 4;
1423pub const drm_buf_desc__DRM_FB_BUFFER: drm_buf_desc__bindgen_ty_1 = 8;
1424pub const drm_buf_desc__DRM_PCI_BUFFER_RO: drm_buf_desc__bindgen_ty_1 = 16;
1425pub type drm_buf_desc__bindgen_ty_1 = ::core::ffi::c_uint;
1426#[repr(C)]
1427#[derive(Debug, Copy, Clone)]
1428pub struct drm_buf_info {
1429 pub count: ::core::ffi::c_int,
1430 pub list: *mut drm_buf_desc,
1431}
1432#[repr(C)]
1433#[derive(Debug, Copy, Clone)]
1434pub struct drm_buf_free {
1435 pub count: ::core::ffi::c_int,
1436 pub list: *mut ::core::ffi::c_int,
1437}
1438#[repr(C)]
1439#[derive(Debug, Copy, Clone)]
1440pub struct drm_buf_pub {
1441 pub idx: ::core::ffi::c_int,
1442 pub total: ::core::ffi::c_int,
1443 pub used: ::core::ffi::c_int,
1444 pub address: *mut ::core::ffi::c_void,
1445}
1446#[repr(C)]
1447#[derive(Debug, Copy, Clone)]
1448pub struct drm_buf_map {
1449 pub count: ::core::ffi::c_int,
1450 pub virtual_: *mut ::core::ffi::c_void,
1451 pub list: *mut drm_buf_pub,
1452}
1453#[repr(C)]
1454#[derive(Debug, Copy, Clone)]
1455pub struct drm_dma {
1456 pub context: ::core::ffi::c_int,
1457 pub send_count: ::core::ffi::c_int,
1458 pub send_indices: *mut ::core::ffi::c_int,
1459 pub send_sizes: *mut ::core::ffi::c_int,
1460 pub flags: drm_dma_flags,
1461 pub request_count: ::core::ffi::c_int,
1462 pub request_size: ::core::ffi::c_int,
1463 pub request_indices: *mut ::core::ffi::c_int,
1464 pub request_sizes: *mut ::core::ffi::c_int,
1465 pub granted_count: ::core::ffi::c_int,
1466}
1467pub const drm_ctx_flags__DRM_CONTEXT_PRESERVED: drm_ctx_flags = 1;
1468pub const drm_ctx_flags__DRM_CONTEXT_2DONLY: drm_ctx_flags = 2;
1469pub type drm_ctx_flags = ::core::ffi::c_uint;
1470#[repr(C)]
1471#[derive(Debug, Copy, Clone)]
1472pub struct drm_ctx {
1473 pub handle: drm_context_t,
1474 pub flags: drm_ctx_flags,
1475}
1476#[repr(C)]
1477#[derive(Debug, Copy, Clone)]
1478pub struct drm_ctx_res {
1479 pub count: ::core::ffi::c_int,
1480 pub contexts: *mut drm_ctx,
1481}
1482#[repr(C)]
1483#[derive(Debug, Copy, Clone)]
1484pub struct drm_draw {
1485 pub handle: drm_drawable_t,
1486}
1487pub const drm_drawable_info_type_t_DRM_DRAWABLE_CLIPRECTS: drm_drawable_info_type_t = 0;
1488pub type drm_drawable_info_type_t = ::core::ffi::c_uint;
1489#[repr(C)]
1490#[derive(Debug, Copy, Clone)]
1491pub struct drm_update_draw {
1492 pub handle: drm_drawable_t,
1493 pub type_: ::core::ffi::c_uint,
1494 pub num: ::core::ffi::c_uint,
1495 pub data: ::core::ffi::c_ulonglong,
1496}
1497#[repr(C)]
1498#[derive(Debug, Copy, Clone)]
1499pub struct drm_auth {
1500 pub magic: drm_magic_t,
1501}
1502#[repr(C)]
1503#[derive(Debug, Copy, Clone)]
1504pub struct drm_irq_busid {
1505 pub irq: ::core::ffi::c_int,
1506 pub busnum: ::core::ffi::c_int,
1507 pub devnum: ::core::ffi::c_int,
1508 pub funcnum: ::core::ffi::c_int,
1509}
1510pub const drm_vblank_seq_type__DRM_VBLANK_ABSOLUTE: drm_vblank_seq_type = 0;
1511pub const drm_vblank_seq_type__DRM_VBLANK_RELATIVE: drm_vblank_seq_type = 1;
1512pub const drm_vblank_seq_type__DRM_VBLANK_HIGH_CRTC_MASK: drm_vblank_seq_type = 62;
1513pub const drm_vblank_seq_type__DRM_VBLANK_EVENT: drm_vblank_seq_type = 67108864;
1514pub const drm_vblank_seq_type__DRM_VBLANK_FLIP: drm_vblank_seq_type = 134217728;
1515pub const drm_vblank_seq_type__DRM_VBLANK_NEXTONMISS: drm_vblank_seq_type = 268435456;
1516pub const drm_vblank_seq_type__DRM_VBLANK_SECONDARY: drm_vblank_seq_type = 536870912;
1517pub const drm_vblank_seq_type__DRM_VBLANK_SIGNAL: drm_vblank_seq_type = 1073741824;
1518pub type drm_vblank_seq_type = ::core::ffi::c_uint;
1519#[repr(C)]
1520#[derive(Debug, Copy, Clone)]
1521pub struct drm_wait_vblank_request {
1522 pub type_: drm_vblank_seq_type,
1523 pub sequence: ::core::ffi::c_uint,
1524 pub signal: ::core::ffi::c_ulong,
1525}
1526#[repr(C)]
1527#[derive(Debug, Copy, Clone)]
1528pub struct drm_wait_vblank_reply {
1529 pub type_: drm_vblank_seq_type,
1530 pub sequence: ::core::ffi::c_uint,
1531 pub tval_sec: ::core::ffi::c_long,
1532 pub tval_usec: ::core::ffi::c_long,
1533}
1534#[repr(C)]
1535#[derive(Copy, Clone)]
1536pub union drm_wait_vblank {
1537 pub request: drm_wait_vblank_request,
1538 pub reply: drm_wait_vblank_reply,
1539}
1540#[repr(C)]
1541#[derive(Debug, Copy, Clone)]
1542pub struct drm_modeset_ctl {
1543 pub crtc: __u32,
1544 pub cmd: __u32,
1545}
1546#[repr(C)]
1547#[derive(Debug, Copy, Clone)]
1548pub struct drm_agp_mode {
1549 pub mode: ::core::ffi::c_ulong,
1550}
1551#[repr(C)]
1552#[derive(Debug, Copy, Clone)]
1553pub struct drm_agp_buffer {
1554 pub size: ::core::ffi::c_ulong,
1555 pub handle: ::core::ffi::c_ulong,
1556 pub type_: ::core::ffi::c_ulong,
1557 pub physical: ::core::ffi::c_ulong,
1558}
1559#[repr(C)]
1560#[derive(Debug, Copy, Clone)]
1561pub struct drm_agp_binding {
1562 pub handle: ::core::ffi::c_ulong,
1563 pub offset: ::core::ffi::c_ulong,
1564}
1565#[repr(C)]
1566#[derive(Debug, Copy, Clone)]
1567pub struct drm_agp_info {
1568 pub agp_version_major: ::core::ffi::c_int,
1569 pub agp_version_minor: ::core::ffi::c_int,
1570 pub mode: ::core::ffi::c_ulong,
1571 pub aperture_base: ::core::ffi::c_ulong,
1572 pub aperture_size: ::core::ffi::c_ulong,
1573 pub memory_allowed: ::core::ffi::c_ulong,
1574 pub memory_used: ::core::ffi::c_ulong,
1575 pub id_vendor: ::core::ffi::c_ushort,
1576 pub id_device: ::core::ffi::c_ushort,
1577}
1578#[repr(C)]
1579#[derive(Debug, Copy, Clone)]
1580pub struct drm_scatter_gather {
1581 pub size: ::core::ffi::c_ulong,
1582 pub handle: ::core::ffi::c_ulong,
1583}
1584#[repr(C)]
1585#[derive(Debug, Copy, Clone)]
1586pub struct drm_set_version {
1587 pub drm_di_major: ::core::ffi::c_int,
1588 pub drm_di_minor: ::core::ffi::c_int,
1589 pub drm_dd_major: ::core::ffi::c_int,
1590 pub drm_dd_minor: ::core::ffi::c_int,
1591}
1592#[repr(C)]
1593#[derive(Debug, Copy, Clone)]
1594pub struct drm_gem_close {
1595 pub handle: __u32,
1596 pub pad: __u32,
1597}
1598#[repr(C)]
1599#[derive(Debug, Copy, Clone)]
1600pub struct drm_gem_flink {
1601 pub handle: __u32,
1602 pub name: __u32,
1603}
1604#[repr(C)]
1605#[derive(Debug, Copy, Clone)]
1606pub struct drm_gem_open {
1607 pub name: __u32,
1608 pub handle: __u32,
1609 pub size: __u64,
1610}
1611#[repr(C)]
1612#[derive(Debug, Copy, Clone)]
1613pub struct drm_get_cap {
1614 pub capability: __u64,
1615 pub value: __u64,
1616}
1617#[repr(C)]
1618#[derive(Debug, Copy, Clone)]
1619pub struct drm_set_client_cap {
1620 pub capability: __u64,
1621 pub value: __u64,
1622}
1623#[repr(C)]
1624#[derive(Debug, Copy, Clone)]
1625pub struct drm_prime_handle {
1626 pub handle: __u32,
1627 pub flags: __u32,
1628 pub fd: __s32,
1629}
1630#[repr(C)]
1631#[derive(Debug, Copy, Clone)]
1632pub struct drm_syncobj_create {
1633 pub handle: __u32,
1634 pub flags: __u32,
1635}
1636#[repr(C)]
1637#[derive(Debug, Copy, Clone)]
1638pub struct drm_syncobj_destroy {
1639 pub handle: __u32,
1640 pub pad: __u32,
1641}
1642#[repr(C)]
1643#[derive(Debug, Copy, Clone)]
1644pub struct drm_syncobj_handle {
1645 pub handle: __u32,
1646 pub flags: __u32,
1647 pub fd: __s32,
1648 pub pad: __u32,
1649}
1650#[repr(C)]
1651#[derive(Debug, Copy, Clone)]
1652pub struct drm_syncobj_transfer {
1653 pub src_handle: __u32,
1654 pub dst_handle: __u32,
1655 pub src_point: __u64,
1656 pub dst_point: __u64,
1657 pub flags: __u32,
1658 pub pad: __u32,
1659}
1660#[repr(C)]
1661#[derive(Debug, Copy, Clone)]
1662pub struct drm_syncobj_wait {
1663 pub handles: __u64,
1664 pub timeout_nsec: __s64,
1665 pub count_handles: __u32,
1666 pub flags: __u32,
1667 pub first_signaled: __u32,
1668 pub pad: __u32,
1669 pub deadline_nsec: __u64,
1670}
1671#[repr(C)]
1672#[derive(Debug, Copy, Clone)]
1673pub struct drm_syncobj_timeline_wait {
1674 pub handles: __u64,
1675 pub points: __u64,
1676 pub timeout_nsec: __s64,
1677 pub count_handles: __u32,
1678 pub flags: __u32,
1679 pub first_signaled: __u32,
1680 pub pad: __u32,
1681 pub deadline_nsec: __u64,
1682}
1683#[repr(C)]
1684#[derive(Debug, Copy, Clone)]
1685pub struct drm_syncobj_eventfd {
1686 pub handle: __u32,
1687 pub flags: __u32,
1688 pub point: __u64,
1689 pub fd: __s32,
1690 pub pad: __u32,
1691}
1692#[repr(C)]
1693#[derive(Debug, Copy, Clone)]
1694pub struct drm_syncobj_array {
1695 pub handles: __u64,
1696 pub count_handles: __u32,
1697 pub pad: __u32,
1698}
1699#[repr(C)]
1700#[derive(Debug, Copy, Clone)]
1701pub struct drm_syncobj_timeline_array {
1702 pub handles: __u64,
1703 pub points: __u64,
1704 pub count_handles: __u32,
1705 pub flags: __u32,
1706}
1707#[repr(C)]
1708#[derive(Debug, Copy, Clone)]
1709pub struct drm_crtc_get_sequence {
1710 pub crtc_id: __u32,
1711 pub active: __u32,
1712 pub sequence: __u64,
1713 pub sequence_ns: __s64,
1714}
1715#[repr(C)]
1716#[derive(Debug, Copy, Clone)]
1717pub struct drm_crtc_queue_sequence {
1718 pub crtc_id: __u32,
1719 pub flags: __u32,
1720 pub sequence: __u64,
1721 pub user_data: __u64,
1722}
1723#[repr(C)]
1724#[derive(Debug, Copy, Clone)]
1725pub struct drm_mode_modeinfo {
1726 pub clock: __u32,
1727 pub hdisplay: __u16,
1728 pub hsync_start: __u16,
1729 pub hsync_end: __u16,
1730 pub htotal: __u16,
1731 pub hskew: __u16,
1732 pub vdisplay: __u16,
1733 pub vsync_start: __u16,
1734 pub vsync_end: __u16,
1735 pub vtotal: __u16,
1736 pub vscan: __u16,
1737 pub vrefresh: __u32,
1738 pub flags: __u32,
1739 pub type_: __u32,
1740 pub name: [::core::ffi::c_char; 32usize],
1741}
1742#[repr(C)]
1743#[derive(Debug, Copy, Clone)]
1744pub struct drm_mode_card_res {
1745 pub fb_id_ptr: __u64,
1746 pub crtc_id_ptr: __u64,
1747 pub connector_id_ptr: __u64,
1748 pub encoder_id_ptr: __u64,
1749 pub count_fbs: __u32,
1750 pub count_crtcs: __u32,
1751 pub count_connectors: __u32,
1752 pub count_encoders: __u32,
1753 pub min_width: __u32,
1754 pub max_width: __u32,
1755 pub min_height: __u32,
1756 pub max_height: __u32,
1757}
1758#[repr(C)]
1759#[derive(Debug, Copy, Clone)]
1760pub struct drm_mode_crtc {
1761 pub set_connectors_ptr: __u64,
1762 pub count_connectors: __u32,
1763 pub crtc_id: __u32,
1764 pub fb_id: __u32,
1765 pub x: __u32,
1766 pub y: __u32,
1767 pub gamma_size: __u32,
1768 pub mode_valid: __u32,
1769 pub mode: drm_mode_modeinfo,
1770}
1771#[repr(C)]
1772#[derive(Debug, Copy, Clone)]
1773pub struct drm_mode_set_plane {
1774 pub plane_id: __u32,
1775 pub crtc_id: __u32,
1776 pub fb_id: __u32,
1777 pub flags: __u32,
1778 pub crtc_x: __s32,
1779 pub crtc_y: __s32,
1780 pub crtc_w: __u32,
1781 pub crtc_h: __u32,
1782 pub src_x: __u32,
1783 pub src_y: __u32,
1784 pub src_h: __u32,
1785 pub src_w: __u32,
1786}
1787#[repr(C)]
1788#[derive(Debug, Copy, Clone)]
1789pub struct drm_mode_get_plane {
1790 pub plane_id: __u32,
1791 pub crtc_id: __u32,
1792 pub fb_id: __u32,
1793 pub possible_crtcs: __u32,
1794 pub gamma_size: __u32,
1795 pub count_format_types: __u32,
1796 pub format_type_ptr: __u64,
1797}
1798#[repr(C)]
1799#[derive(Debug, Copy, Clone)]
1800pub struct drm_mode_get_plane_res {
1801 pub plane_id_ptr: __u64,
1802 pub count_planes: __u32,
1803}
1804#[repr(C)]
1805#[derive(Debug, Copy, Clone)]
1806pub struct drm_mode_get_encoder {
1807 pub encoder_id: __u32,
1808 pub encoder_type: __u32,
1809 pub crtc_id: __u32,
1810 pub possible_crtcs: __u32,
1811 pub possible_clones: __u32,
1812}
1813pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Automatic: drm_mode_subconnector = 0;
1814pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Unknown: drm_mode_subconnector = 0;
1815pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_VGA: drm_mode_subconnector = 1;
1816pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DVID: drm_mode_subconnector = 3;
1817pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DVIA: drm_mode_subconnector = 4;
1818pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Composite: drm_mode_subconnector = 5;
1819pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_SVIDEO: drm_mode_subconnector = 6;
1820pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Component: drm_mode_subconnector = 8;
1821pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_SCART: drm_mode_subconnector = 9;
1822pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_DisplayPort: drm_mode_subconnector = 10;
1823pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_HDMIA: drm_mode_subconnector = 11;
1824pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Native: drm_mode_subconnector = 15;
1825pub const drm_mode_subconnector_DRM_MODE_SUBCONNECTOR_Wireless: drm_mode_subconnector = 18;
1826pub type drm_mode_subconnector = ::core::ffi::c_uint;
1827#[repr(C)]
1828#[derive(Debug, Copy, Clone)]
1829pub struct drm_mode_get_connector {
1830 pub encoders_ptr: __u64,
1831 pub modes_ptr: __u64,
1832 pub props_ptr: __u64,
1833 pub prop_values_ptr: __u64,
1834 pub count_modes: __u32,
1835 pub count_props: __u32,
1836 pub count_encoders: __u32,
1837 pub encoder_id: __u32,
1838 pub connector_id: __u32,
1839 pub connector_type: __u32,
1840 pub connector_type_id: __u32,
1841 pub connection: __u32,
1842 pub mm_width: __u32,
1843 pub mm_height: __u32,
1844 pub subpixel: __u32,
1845 pub pad: __u32,
1846}
1847#[repr(C)]
1848#[derive(Debug, Copy, Clone)]
1849pub struct drm_mode_property_enum {
1850 pub value: __u64,
1851 pub name: [::core::ffi::c_char; 32usize],
1852}
1853#[repr(C)]
1854#[derive(Debug, Copy, Clone)]
1855pub struct drm_mode_get_property {
1856 pub values_ptr: __u64,
1857 pub enum_blob_ptr: __u64,
1858 pub prop_id: __u32,
1859 pub flags: __u32,
1860 pub name: [::core::ffi::c_char; 32usize],
1861 pub count_values: __u32,
1862 pub count_enum_blobs: __u32,
1863}
1864#[repr(C)]
1865#[derive(Debug, Copy, Clone)]
1866pub struct drm_mode_connector_set_property {
1867 pub value: __u64,
1868 pub prop_id: __u32,
1869 pub connector_id: __u32,
1870}
1871#[repr(C)]
1872#[derive(Debug, Copy, Clone)]
1873pub struct drm_mode_obj_get_properties {
1874 pub props_ptr: __u64,
1875 pub prop_values_ptr: __u64,
1876 pub count_props: __u32,
1877 pub obj_id: __u32,
1878 pub obj_type: __u32,
1879}
1880#[repr(C)]
1881#[derive(Debug, Copy, Clone)]
1882pub struct drm_mode_obj_set_property {
1883 pub value: __u64,
1884 pub prop_id: __u32,
1885 pub obj_id: __u32,
1886 pub obj_type: __u32,
1887}
1888#[repr(C)]
1889#[derive(Debug, Copy, Clone)]
1890pub struct drm_mode_get_blob {
1891 pub blob_id: __u32,
1892 pub length: __u32,
1893 pub data: __u64,
1894}
1895#[repr(C)]
1896#[derive(Debug, Copy, Clone)]
1897pub struct drm_mode_fb_cmd {
1898 pub fb_id: __u32,
1899 pub width: __u32,
1900 pub height: __u32,
1901 pub pitch: __u32,
1902 pub bpp: __u32,
1903 pub depth: __u32,
1904 pub handle: __u32,
1905}
1906#[repr(C)]
1907#[derive(Debug, Copy, Clone)]
1908pub struct drm_mode_fb_cmd2 {
1909 pub fb_id: __u32,
1910 pub width: __u32,
1911 pub height: __u32,
1912 pub pixel_format: __u32,
1913 pub flags: __u32,
1914 pub handles: [__u32; 4usize],
1915 pub pitches: [__u32; 4usize],
1916 pub offsets: [__u32; 4usize],
1917 pub modifier: [__u64; 4usize],
1918}
1919#[repr(C)]
1920#[derive(Debug, Copy, Clone)]
1921pub struct drm_mode_fb_dirty_cmd {
1922 pub fb_id: __u32,
1923 pub flags: __u32,
1924 pub color: __u32,
1925 pub num_clips: __u32,
1926 pub clips_ptr: __u64,
1927}
1928#[repr(C)]
1929#[derive(Debug, Copy, Clone)]
1930pub struct drm_mode_mode_cmd {
1931 pub connector_id: __u32,
1932 pub mode: drm_mode_modeinfo,
1933}
1934#[repr(C)]
1935#[derive(Debug, Copy, Clone)]
1936pub struct drm_mode_cursor {
1937 pub flags: __u32,
1938 pub crtc_id: __u32,
1939 pub x: __s32,
1940 pub y: __s32,
1941 pub width: __u32,
1942 pub height: __u32,
1943 pub handle: __u32,
1944}
1945#[repr(C)]
1946#[derive(Debug, Copy, Clone)]
1947pub struct drm_mode_cursor2 {
1948 pub flags: __u32,
1949 pub crtc_id: __u32,
1950 pub x: __s32,
1951 pub y: __s32,
1952 pub width: __u32,
1953 pub height: __u32,
1954 pub handle: __u32,
1955 pub hot_x: __s32,
1956 pub hot_y: __s32,
1957}
1958#[repr(C)]
1959#[derive(Debug, Copy, Clone)]
1960pub struct drm_mode_crtc_lut {
1961 pub crtc_id: __u32,
1962 pub gamma_size: __u32,
1963 pub red: __u64,
1964 pub green: __u64,
1965 pub blue: __u64,
1966}
1967#[repr(C)]
1968#[derive(Debug, Copy, Clone)]
1969pub struct drm_color_ctm {
1970 pub matrix: [__u64; 9usize],
1971}
1972#[repr(C)]
1973#[derive(Debug, Copy, Clone)]
1974pub struct drm_color_lut {
1975 pub red: __u16,
1976 pub green: __u16,
1977 pub blue: __u16,
1978 pub reserved: __u16,
1979}
1980#[repr(C)]
1981#[derive(Debug, Copy, Clone)]
1982pub struct drm_plane_size_hint {
1983 pub width: __u16,
1984 pub height: __u16,
1985}
1986#[repr(C)]
1987#[derive(Debug, Copy, Clone)]
1988pub struct hdr_metadata_infoframe {
1989 pub eotf: __u8,
1990 pub metadata_type: __u8,
1991 pub display_primaries: [hdr_metadata_infoframe__bindgen_ty_1; 3usize],
1992 pub white_point: hdr_metadata_infoframe__bindgen_ty_2,
1993 pub max_display_mastering_luminance: __u16,
1994 pub min_display_mastering_luminance: __u16,
1995 pub max_cll: __u16,
1996 pub max_fall: __u16,
1997}
1998#[repr(C)]
1999#[derive(Debug, Copy, Clone)]
2000pub struct hdr_metadata_infoframe__bindgen_ty_1 {
2001 pub x: __u16,
2002 pub y: __u16,
2003}
2004#[repr(C)]
2005#[derive(Debug, Copy, Clone)]
2006pub struct hdr_metadata_infoframe__bindgen_ty_2 {
2007 pub x: __u16,
2008 pub y: __u16,
2009}
2010#[repr(C)]
2011#[derive(Copy, Clone)]
2012pub struct hdr_output_metadata {
2013 pub metadata_type: __u32,
2014 pub __bindgen_anon_1: hdr_output_metadata__bindgen_ty_1,
2015}
2016#[repr(C)]
2017#[derive(Copy, Clone)]
2018pub union hdr_output_metadata__bindgen_ty_1 {
2019 pub hdmi_metadata_type1: hdr_metadata_infoframe,
2020}
2021#[repr(C)]
2022#[derive(Debug, Copy, Clone)]
2023pub struct drm_mode_crtc_page_flip {
2024 pub crtc_id: __u32,
2025 pub fb_id: __u32,
2026 pub flags: __u32,
2027 pub reserved: __u32,
2028 pub user_data: __u64,
2029}
2030#[repr(C)]
2031#[derive(Debug, Copy, Clone)]
2032pub struct drm_mode_crtc_page_flip_target {
2033 pub crtc_id: __u32,
2034 pub fb_id: __u32,
2035 pub flags: __u32,
2036 pub sequence: __u32,
2037 pub user_data: __u64,
2038}
2039#[repr(C)]
2040#[derive(Debug, Copy, Clone)]
2041pub struct drm_mode_create_dumb {
2042 pub height: __u32,
2043 pub width: __u32,
2044 pub bpp: __u32,
2045 pub flags: __u32,
2046 pub handle: __u32,
2047 pub pitch: __u32,
2048 pub size: __u64,
2049}
2050#[repr(C)]
2051#[derive(Debug, Copy, Clone)]
2052pub struct drm_mode_map_dumb {
2053 pub handle: __u32,
2054 pub pad: __u32,
2055 pub offset: __u64,
2056}
2057#[repr(C)]
2058#[derive(Debug, Copy, Clone)]
2059pub struct drm_mode_destroy_dumb {
2060 pub handle: __u32,
2061}
2062#[repr(C)]
2063#[derive(Debug, Copy, Clone)]
2064pub struct drm_mode_atomic {
2065 pub flags: __u32,
2066 pub count_objs: __u32,
2067 pub objs_ptr: __u64,
2068 pub count_props_ptr: __u64,
2069 pub props_ptr: __u64,
2070 pub prop_values_ptr: __u64,
2071 pub reserved: __u64,
2072 pub user_data: __u64,
2073}
2074#[repr(C)]
2075#[derive(Debug, Copy, Clone)]
2076pub struct drm_format_modifier_blob {
2077 pub version: __u32,
2078 pub flags: __u32,
2079 pub count_formats: __u32,
2080 pub formats_offset: __u32,
2081 pub count_modifiers: __u32,
2082 pub modifiers_offset: __u32,
2083}
2084#[repr(C)]
2085#[derive(Debug, Copy, Clone)]
2086pub struct drm_format_modifier {
2087 pub formats: __u64,
2088 pub offset: __u32,
2089 pub pad: __u32,
2090 pub modifier: __u64,
2091}
2092#[repr(C)]
2093#[derive(Debug, Copy, Clone)]
2094pub struct drm_mode_create_blob {
2095 pub data: __u64,
2096 pub length: __u32,
2097 pub blob_id: __u32,
2098}
2099#[repr(C)]
2100#[derive(Debug, Copy, Clone)]
2101pub struct drm_mode_destroy_blob {
2102 pub blob_id: __u32,
2103}
2104#[repr(C)]
2105#[derive(Debug, Copy, Clone)]
2106pub struct drm_mode_create_lease {
2107 pub object_ids: __u64,
2108 pub object_count: __u32,
2109 pub flags: __u32,
2110 pub lessee_id: __u32,
2111 pub fd: __u32,
2112}
2113#[repr(C)]
2114#[derive(Debug, Copy, Clone)]
2115pub struct drm_mode_list_lessees {
2116 pub count_lessees: __u32,
2117 pub pad: __u32,
2118 pub lessees_ptr: __u64,
2119}
2120#[repr(C)]
2121#[derive(Debug, Copy, Clone)]
2122pub struct drm_mode_get_lease {
2123 pub count_objects: __u32,
2124 pub pad: __u32,
2125 pub objects_ptr: __u64,
2126}
2127#[repr(C)]
2128#[derive(Debug, Copy, Clone)]
2129pub struct drm_mode_revoke_lease {
2130 pub lessee_id: __u32,
2131}
2132#[repr(C)]
2133#[derive(Debug, Copy, Clone)]
2134pub struct drm_mode_rect {
2135 pub x1: __s32,
2136 pub y1: __s32,
2137 pub x2: __s32,
2138 pub y2: __s32,
2139}
2140#[repr(C)]
2141#[derive(Debug, Copy, Clone)]
2142pub struct drm_mode_closefb {
2143 pub fb_id: __u32,
2144 pub pad: __u32,
2145}
2146#[repr(C)]
2147#[derive(Debug, Copy, Clone)]
2148pub struct drm_event {
2149 pub type_: __u32,
2150 pub length: __u32,
2151}
2152#[repr(C)]
2153#[derive(Debug, Copy, Clone)]
2154pub struct drm_event_vblank {
2155 pub base: drm_event,
2156 pub user_data: __u64,
2157 pub tv_sec: __u32,
2158 pub tv_usec: __u32,
2159 pub sequence: __u32,
2160 pub crtc_id: __u32,
2161}
2162#[repr(C)]
2163#[derive(Debug, Copy, Clone)]
2164pub struct drm_event_crtc_sequence {
2165 pub base: drm_event,
2166 pub user_data: __u64,
2167 pub time_ns: __s64,
2168 pub sequence: __u64,
2169}
2170pub type drm_clip_rect_t = drm_clip_rect;
2171pub type drm_drawable_info_t = drm_drawable_info;
2172pub type drm_tex_region_t = drm_tex_region;
2173pub type drm_hw_lock_t = drm_hw_lock;
2174pub type drm_version_t = drm_version;
2175pub type drm_unique_t = drm_unique;
2176pub type drm_list_t = drm_list;
2177pub type drm_block_t = drm_block;
2178pub type drm_control_t = drm_control;
2179pub use self::drm_map_flags as drm_map_flags_t;
2180pub use self::drm_map_type as drm_map_type_t;
2181pub type drm_ctx_priv_map_t = drm_ctx_priv_map;
2182pub type drm_map_t = drm_map;
2183pub type drm_client_t = drm_client;
2184pub use self::drm_stat_type as drm_stat_type_t;
2185pub type drm_stats_t = drm_stats;
2186pub use self::drm_lock_flags as drm_lock_flags_t;
2187pub type drm_lock_t = drm_lock;
2188pub use self::drm_dma_flags as drm_dma_flags_t;
2189pub type drm_buf_desc_t = drm_buf_desc;
2190pub type drm_buf_info_t = drm_buf_info;
2191pub type drm_buf_free_t = drm_buf_free;
2192pub type drm_buf_pub_t = drm_buf_pub;
2193pub type drm_buf_map_t = drm_buf_map;
2194pub type drm_dma_t = drm_dma;
2195pub type drm_wait_vblank_t = drm_wait_vblank;
2196pub type drm_agp_mode_t = drm_agp_mode;
2197pub use self::drm_ctx_flags as drm_ctx_flags_t;
2198pub type drm_ctx_t = drm_ctx;
2199pub type drm_ctx_res_t = drm_ctx_res;
2200pub type drm_draw_t = drm_draw;
2201pub type drm_update_draw_t = drm_update_draw;
2202pub type drm_auth_t = drm_auth;
2203pub type drm_irq_busid_t = drm_irq_busid;
2204pub use self::drm_vblank_seq_type as drm_vblank_seq_type_t;
2205pub type drm_agp_buffer_t = drm_agp_buffer;
2206pub type drm_agp_binding_t = drm_agp_binding;
2207pub type drm_agp_info_t = drm_agp_info;
2208pub type drm_scatter_gather_t = drm_scatter_gather;
2209pub type drm_set_version_t = drm_set_version;
2210pub type drmSize = ::core::ffi::c_uint;
2211pub type drmSizePtr = *mut ::core::ffi::c_uint;
2212pub type drmAddress = *mut ::core::ffi::c_void;
2213pub type drmAddressPtr = *mut *mut ::core::ffi::c_void;
2214#[repr(C)]
2215#[derive(Debug, Copy, Clone)]
2216pub struct _drmServerInfo {
2217 pub debug_print: ::core::option::Option<
2218 unsafe extern "C" fn(
2219 format: *const ::core::ffi::c_char,
2220 ap: *mut __va_list_tag,
2221 ) -> ::core::ffi::c_int,
2222 >,
2223 pub load_module: ::core::option::Option<
2224 unsafe extern "C" fn(name: *const ::core::ffi::c_char) -> ::core::ffi::c_int,
2225 >,
2226 pub get_perms:
2227 ::core::option::Option<unsafe extern "C" fn(arg1: *mut gid_t, arg2: *mut mode_t)>,
2228}
2229pub type drmServerInfo = _drmServerInfo;
2230pub type drmServerInfoPtr = *mut _drmServerInfo;
2231#[repr(C)]
2232#[derive(Debug, Copy, Clone)]
2233pub struct drmHashEntry {
2234 pub fd: ::core::ffi::c_int,
2235 pub f: ::core::option::Option<
2236 unsafe extern "C" fn(
2237 arg1: ::core::ffi::c_int,
2238 arg2: *mut ::core::ffi::c_void,
2239 arg3: *mut ::core::ffi::c_void,
2240 ),
2241 >,
2242 pub tagTable: *mut ::core::ffi::c_void,
2243}
2244unsafe extern "C" {
2245 pub fn drmIoctl(
2246 fd: ::core::ffi::c_int,
2247 request: ::core::ffi::c_ulong,
2248 arg: *mut ::core::ffi::c_void,
2249 ) -> ::core::ffi::c_int;
2250}
2251unsafe extern "C" {
2252 pub fn drmGetHashTable() -> *mut ::core::ffi::c_void;
2253}
2254unsafe extern "C" {
2255 pub fn drmGetEntry(fd: ::core::ffi::c_int) -> *mut drmHashEntry;
2256}
2257#[repr(C)]
2258#[derive(Debug, Copy, Clone)]
2259pub struct _drmVersion {
2260 pub version_major: ::core::ffi::c_int,
2261 pub version_minor: ::core::ffi::c_int,
2262 pub version_patchlevel: ::core::ffi::c_int,
2263 pub name_len: ::core::ffi::c_int,
2264 pub name: *mut ::core::ffi::c_char,
2265 pub date_len: ::core::ffi::c_int,
2266 pub date: *mut ::core::ffi::c_char,
2267 pub desc_len: ::core::ffi::c_int,
2268 pub desc: *mut ::core::ffi::c_char,
2269}
2270pub type drmVersion = _drmVersion;
2271pub type drmVersionPtr = *mut _drmVersion;
2272#[repr(C)]
2273#[derive(Debug, Copy, Clone)]
2274pub struct _drmStats {
2275 pub count: ::core::ffi::c_ulong,
2276 pub data: [_drmStats__bindgen_ty_1; 15usize],
2277}
2278#[repr(C)]
2279#[derive(Debug, Copy, Clone)]
2280pub struct _drmStats__bindgen_ty_1 {
2281 pub value: ::core::ffi::c_ulong,
2282 pub long_format: *const ::core::ffi::c_char,
2283 pub long_name: *const ::core::ffi::c_char,
2284 pub rate_format: *const ::core::ffi::c_char,
2285 pub rate_name: *const ::core::ffi::c_char,
2286 pub isvalue: ::core::ffi::c_int,
2287 pub mult_names: *const ::core::ffi::c_char,
2288 pub mult: ::core::ffi::c_int,
2289 pub verbose: ::core::ffi::c_int,
2290}
2291pub type drmStatsT = _drmStats;
2292pub const drmMapType_DRM_FRAME_BUFFER: drmMapType = 0;
2293pub const drmMapType_DRM_REGISTERS: drmMapType = 1;
2294pub const drmMapType_DRM_SHM: drmMapType = 2;
2295pub const drmMapType_DRM_AGP: drmMapType = 3;
2296pub const drmMapType_DRM_SCATTER_GATHER: drmMapType = 4;
2297pub const drmMapType_DRM_CONSISTENT: drmMapType = 5;
2298pub type drmMapType = ::core::ffi::c_uint;
2299pub const drmMapFlags_DRM_RESTRICTED: drmMapFlags = 1;
2300pub const drmMapFlags_DRM_READ_ONLY: drmMapFlags = 2;
2301pub const drmMapFlags_DRM_LOCKED: drmMapFlags = 4;
2302pub const drmMapFlags_DRM_KERNEL: drmMapFlags = 8;
2303pub const drmMapFlags_DRM_WRITE_COMBINING: drmMapFlags = 16;
2304pub const drmMapFlags_DRM_CONTAINS_LOCK: drmMapFlags = 32;
2305pub const drmMapFlags_DRM_REMOVABLE: drmMapFlags = 64;
2306pub type drmMapFlags = ::core::ffi::c_uint;
2307pub const drmDMAFlags_DRM_DMA_BLOCK: drmDMAFlags = 1;
2308pub const drmDMAFlags_DRM_DMA_WHILE_LOCKED: drmDMAFlags = 2;
2309pub const drmDMAFlags_DRM_DMA_PRIORITY: drmDMAFlags = 4;
2310pub const drmDMAFlags_DRM_DMA_WAIT: drmDMAFlags = 16;
2311pub const drmDMAFlags_DRM_DMA_SMALLER_OK: drmDMAFlags = 32;
2312pub const drmDMAFlags_DRM_DMA_LARGER_OK: drmDMAFlags = 64;
2313pub type drmDMAFlags = ::core::ffi::c_uint;
2314pub const drmBufDescFlags_DRM_PAGE_ALIGN: drmBufDescFlags = 1;
2315pub const drmBufDescFlags_DRM_AGP_BUFFER: drmBufDescFlags = 2;
2316pub const drmBufDescFlags_DRM_SG_BUFFER: drmBufDescFlags = 4;
2317pub const drmBufDescFlags_DRM_FB_BUFFER: drmBufDescFlags = 8;
2318pub const drmBufDescFlags_DRM_PCI_BUFFER_RO: drmBufDescFlags = 16;
2319pub type drmBufDescFlags = ::core::ffi::c_uint;
2320pub const drmLockFlags_DRM_LOCK_READY: drmLockFlags = 1;
2321pub const drmLockFlags_DRM_LOCK_QUIESCENT: drmLockFlags = 2;
2322pub const drmLockFlags_DRM_LOCK_FLUSH: drmLockFlags = 4;
2323pub const drmLockFlags_DRM_LOCK_FLUSH_ALL: drmLockFlags = 8;
2324pub const drmLockFlags_DRM_HALT_ALL_QUEUES: drmLockFlags = 16;
2325pub const drmLockFlags_DRM_HALT_CUR_QUEUES: drmLockFlags = 32;
2326pub type drmLockFlags = ::core::ffi::c_uint;
2327pub const drm_context_tFlags_DRM_CONTEXT_PRESERVED: drm_context_tFlags = 1;
2328pub const drm_context_tFlags_DRM_CONTEXT_2DONLY: drm_context_tFlags = 2;
2329pub type drm_context_tFlags = ::core::ffi::c_uint;
2330pub type drm_context_tFlagsPtr = *mut drm_context_tFlags;
2331#[repr(C)]
2332#[derive(Debug, Copy, Clone)]
2333pub struct _drmBufDesc {
2334 pub count: ::core::ffi::c_int,
2335 pub size: ::core::ffi::c_int,
2336 pub low_mark: ::core::ffi::c_int,
2337 pub high_mark: ::core::ffi::c_int,
2338}
2339pub type drmBufDesc = _drmBufDesc;
2340pub type drmBufDescPtr = *mut _drmBufDesc;
2341#[repr(C)]
2342#[derive(Debug, Copy, Clone)]
2343pub struct _drmBufInfo {
2344 pub count: ::core::ffi::c_int,
2345 pub list: drmBufDescPtr,
2346}
2347pub type drmBufInfo = _drmBufInfo;
2348pub type drmBufInfoPtr = *mut _drmBufInfo;
2349#[repr(C)]
2350#[derive(Debug, Copy, Clone)]
2351pub struct _drmBuf {
2352 pub idx: ::core::ffi::c_int,
2353 pub total: ::core::ffi::c_int,
2354 pub used: ::core::ffi::c_int,
2355 pub address: drmAddress,
2356}
2357pub type drmBuf = _drmBuf;
2358pub type drmBufPtr = *mut _drmBuf;
2359#[repr(C)]
2360#[derive(Debug, Copy, Clone)]
2361pub struct _drmBufMap {
2362 pub count: ::core::ffi::c_int,
2363 pub list: drmBufPtr,
2364}
2365pub type drmBufMap = _drmBufMap;
2366pub type drmBufMapPtr = *mut _drmBufMap;
2367#[repr(C)]
2368#[derive(Debug, Copy, Clone)]
2369pub struct _drmLock {
2370 pub lock: ::core::ffi::c_uint,
2371 pub padding: [::core::ffi::c_char; 60usize],
2372}
2373pub type drmLock = _drmLock;
2374pub type drmLockPtr = *mut _drmLock;
2375#[repr(C)]
2376#[derive(Debug, Copy, Clone)]
2377pub struct _drmDMAReq {
2378 pub context: drm_context_t,
2379 pub send_count: ::core::ffi::c_int,
2380 pub send_list: *mut ::core::ffi::c_int,
2381 pub send_sizes: *mut ::core::ffi::c_int,
2382 pub flags: drmDMAFlags,
2383 pub request_count: ::core::ffi::c_int,
2384 pub request_size: ::core::ffi::c_int,
2385 pub request_list: *mut ::core::ffi::c_int,
2386 pub request_sizes: *mut ::core::ffi::c_int,
2387 pub granted_count: ::core::ffi::c_int,
2388}
2389pub type drmDMAReq = _drmDMAReq;
2390pub type drmDMAReqPtr = *mut _drmDMAReq;
2391#[repr(C)]
2392#[derive(Debug, Copy, Clone)]
2393pub struct _drmRegion {
2394 pub handle: drm_handle_t,
2395 pub offset: ::core::ffi::c_uint,
2396 pub size: drmSize,
2397 pub map: drmAddress,
2398}
2399pub type drmRegion = _drmRegion;
2400pub type drmRegionPtr = *mut _drmRegion;
2401#[repr(C)]
2402#[derive(Debug, Copy, Clone)]
2403pub struct _drmTextureRegion {
2404 pub next: ::core::ffi::c_uchar,
2405 pub prev: ::core::ffi::c_uchar,
2406 pub in_use: ::core::ffi::c_uchar,
2407 pub padding: ::core::ffi::c_uchar,
2408 pub age: ::core::ffi::c_uint,
2409}
2410pub type drmTextureRegion = _drmTextureRegion;
2411pub type drmTextureRegionPtr = *mut _drmTextureRegion;
2412pub const drmVBlankSeqType_DRM_VBLANK_ABSOLUTE: drmVBlankSeqType = 0;
2413pub const drmVBlankSeqType_DRM_VBLANK_RELATIVE: drmVBlankSeqType = 1;
2414pub const drmVBlankSeqType_DRM_VBLANK_HIGH_CRTC_MASK: drmVBlankSeqType = 62;
2415pub const drmVBlankSeqType_DRM_VBLANK_EVENT: drmVBlankSeqType = 67108864;
2416pub const drmVBlankSeqType_DRM_VBLANK_FLIP: drmVBlankSeqType = 134217728;
2417pub const drmVBlankSeqType_DRM_VBLANK_NEXTONMISS: drmVBlankSeqType = 268435456;
2418pub const drmVBlankSeqType_DRM_VBLANK_SECONDARY: drmVBlankSeqType = 536870912;
2419pub const drmVBlankSeqType_DRM_VBLANK_SIGNAL: drmVBlankSeqType = 1073741824;
2420pub type drmVBlankSeqType = ::core::ffi::c_uint;
2421#[repr(C)]
2422#[derive(Debug, Copy, Clone)]
2423pub struct _drmVBlankReq {
2424 pub type_: drmVBlankSeqType,
2425 pub sequence: ::core::ffi::c_uint,
2426 pub signal: ::core::ffi::c_ulong,
2427}
2428pub type drmVBlankReq = _drmVBlankReq;
2429pub type drmVBlankReqPtr = *mut _drmVBlankReq;
2430#[repr(C)]
2431#[derive(Debug, Copy, Clone)]
2432pub struct _drmVBlankReply {
2433 pub type_: drmVBlankSeqType,
2434 pub sequence: ::core::ffi::c_uint,
2435 pub tval_sec: ::core::ffi::c_long,
2436 pub tval_usec: ::core::ffi::c_long,
2437}
2438pub type drmVBlankReply = _drmVBlankReply;
2439pub type drmVBlankReplyPtr = *mut _drmVBlankReply;
2440#[repr(C)]
2441#[derive(Copy, Clone)]
2442pub union _drmVBlank {
2443 pub request: drmVBlankReq,
2444 pub reply: drmVBlankReply,
2445}
2446pub type drmVBlank = _drmVBlank;
2447pub type drmVBlankPtr = *mut _drmVBlank;
2448#[repr(C)]
2449#[derive(Debug, Copy, Clone)]
2450pub struct _drmSetVersion {
2451 pub drm_di_major: ::core::ffi::c_int,
2452 pub drm_di_minor: ::core::ffi::c_int,
2453 pub drm_dd_major: ::core::ffi::c_int,
2454 pub drm_dd_minor: ::core::ffi::c_int,
2455}
2456pub type drmSetVersion = _drmSetVersion;
2457pub type drmSetVersionPtr = *mut _drmSetVersion;
2458unsafe extern "C" {
2459 pub fn drmAvailable() -> ::core::ffi::c_int;
2460}
2461unsafe extern "C" {
2462 pub fn drmOpen(
2463 name: *const ::core::ffi::c_char,
2464 busid: *const ::core::ffi::c_char,
2465 ) -> ::core::ffi::c_int;
2466}
2467unsafe extern "C" {
2468 pub fn drmOpenWithType(
2469 name: *const ::core::ffi::c_char,
2470 busid: *const ::core::ffi::c_char,
2471 type_: ::core::ffi::c_int,
2472 ) -> ::core::ffi::c_int;
2473}
2474unsafe extern "C" {
2475 pub fn drmOpenControl(minor: ::core::ffi::c_int) -> ::core::ffi::c_int;
2476}
2477unsafe extern "C" {
2478 pub fn drmOpenRender(minor: ::core::ffi::c_int) -> ::core::ffi::c_int;
2479}
2480unsafe extern "C" {
2481 pub fn drmClose(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2482}
2483unsafe extern "C" {
2484 pub fn drmGetVersion(fd: ::core::ffi::c_int) -> drmVersionPtr;
2485}
2486unsafe extern "C" {
2487 pub fn drmGetLibVersion(fd: ::core::ffi::c_int) -> drmVersionPtr;
2488}
2489unsafe extern "C" {
2490 pub fn drmGetCap(
2491 fd: ::core::ffi::c_int,
2492 capability: u64,
2493 value: *mut u64,
2494 ) -> ::core::ffi::c_int;
2495}
2496unsafe extern "C" {
2497 pub fn drmFreeVersion(arg1: drmVersionPtr);
2498}
2499unsafe extern "C" {
2500 pub fn drmGetMagic(fd: ::core::ffi::c_int, magic: *mut drm_magic_t) -> ::core::ffi::c_int;
2501}
2502unsafe extern "C" {
2503 pub fn drmGetBusid(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
2504}
2505unsafe extern "C" {
2506 pub fn drmGetInterruptFromBusID(
2507 fd: ::core::ffi::c_int,
2508 busnum: ::core::ffi::c_int,
2509 devnum: ::core::ffi::c_int,
2510 funcnum: ::core::ffi::c_int,
2511 ) -> ::core::ffi::c_int;
2512}
2513unsafe extern "C" {
2514 pub fn drmGetMap(
2515 fd: ::core::ffi::c_int,
2516 idx: ::core::ffi::c_int,
2517 offset: *mut drm_handle_t,
2518 size: *mut drmSize,
2519 type_: *mut drmMapType,
2520 flags: *mut drmMapFlags,
2521 handle: *mut drm_handle_t,
2522 mtrr: *mut ::core::ffi::c_int,
2523 ) -> ::core::ffi::c_int;
2524}
2525unsafe extern "C" {
2526 pub fn drmGetClient(
2527 fd: ::core::ffi::c_int,
2528 idx: ::core::ffi::c_int,
2529 auth: *mut ::core::ffi::c_int,
2530 pid: *mut ::core::ffi::c_int,
2531 uid: *mut ::core::ffi::c_int,
2532 magic: *mut ::core::ffi::c_ulong,
2533 iocs: *mut ::core::ffi::c_ulong,
2534 ) -> ::core::ffi::c_int;
2535}
2536unsafe extern "C" {
2537 pub fn drmGetStats(fd: ::core::ffi::c_int, stats: *mut drmStatsT) -> ::core::ffi::c_int;
2538}
2539unsafe extern "C" {
2540 pub fn drmSetInterfaceVersion(
2541 fd: ::core::ffi::c_int,
2542 version: *mut drmSetVersion,
2543 ) -> ::core::ffi::c_int;
2544}
2545unsafe extern "C" {
2546 pub fn drmCommandNone(
2547 fd: ::core::ffi::c_int,
2548 drmCommandIndex: ::core::ffi::c_ulong,
2549 ) -> ::core::ffi::c_int;
2550}
2551unsafe extern "C" {
2552 pub fn drmCommandRead(
2553 fd: ::core::ffi::c_int,
2554 drmCommandIndex: ::core::ffi::c_ulong,
2555 data: *mut ::core::ffi::c_void,
2556 size: ::core::ffi::c_ulong,
2557 ) -> ::core::ffi::c_int;
2558}
2559unsafe extern "C" {
2560 pub fn drmCommandWrite(
2561 fd: ::core::ffi::c_int,
2562 drmCommandIndex: ::core::ffi::c_ulong,
2563 data: *mut ::core::ffi::c_void,
2564 size: ::core::ffi::c_ulong,
2565 ) -> ::core::ffi::c_int;
2566}
2567unsafe extern "C" {
2568 pub fn drmCommandWriteRead(
2569 fd: ::core::ffi::c_int,
2570 drmCommandIndex: ::core::ffi::c_ulong,
2571 data: *mut ::core::ffi::c_void,
2572 size: ::core::ffi::c_ulong,
2573 ) -> ::core::ffi::c_int;
2574}
2575unsafe extern "C" {
2576 pub fn drmFreeBusid(busid: *const ::core::ffi::c_char);
2577}
2578unsafe extern "C" {
2579 pub fn drmSetBusid(
2580 fd: ::core::ffi::c_int,
2581 busid: *const ::core::ffi::c_char,
2582 ) -> ::core::ffi::c_int;
2583}
2584unsafe extern "C" {
2585 pub fn drmAuthMagic(fd: ::core::ffi::c_int, magic: drm_magic_t) -> ::core::ffi::c_int;
2586}
2587unsafe extern "C" {
2588 pub fn drmAddMap(
2589 fd: ::core::ffi::c_int,
2590 offset: drm_handle_t,
2591 size: drmSize,
2592 type_: drmMapType,
2593 flags: drmMapFlags,
2594 handle: *mut drm_handle_t,
2595 ) -> ::core::ffi::c_int;
2596}
2597unsafe extern "C" {
2598 pub fn drmRmMap(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
2599}
2600unsafe extern "C" {
2601 pub fn drmAddContextPrivateMapping(
2602 fd: ::core::ffi::c_int,
2603 ctx_id: drm_context_t,
2604 handle: drm_handle_t,
2605 ) -> ::core::ffi::c_int;
2606}
2607unsafe extern "C" {
2608 pub fn drmAddBufs(
2609 fd: ::core::ffi::c_int,
2610 count: ::core::ffi::c_int,
2611 size: ::core::ffi::c_int,
2612 flags: drmBufDescFlags,
2613 agp_offset: ::core::ffi::c_int,
2614 ) -> ::core::ffi::c_int;
2615}
2616unsafe extern "C" {
2617 pub fn drmMarkBufs(fd: ::core::ffi::c_int, low: f64, high: f64) -> ::core::ffi::c_int;
2618}
2619unsafe extern "C" {
2620 pub fn drmCreateContext(
2621 fd: ::core::ffi::c_int,
2622 handle: *mut drm_context_t,
2623 ) -> ::core::ffi::c_int;
2624}
2625unsafe extern "C" {
2626 pub fn drmSetContextFlags(
2627 fd: ::core::ffi::c_int,
2628 context: drm_context_t,
2629 flags: drm_context_tFlags,
2630 ) -> ::core::ffi::c_int;
2631}
2632unsafe extern "C" {
2633 pub fn drmGetContextFlags(
2634 fd: ::core::ffi::c_int,
2635 context: drm_context_t,
2636 flags: drm_context_tFlagsPtr,
2637 ) -> ::core::ffi::c_int;
2638}
2639unsafe extern "C" {
2640 pub fn drmAddContextTag(
2641 fd: ::core::ffi::c_int,
2642 context: drm_context_t,
2643 tag: *mut ::core::ffi::c_void,
2644 ) -> ::core::ffi::c_int;
2645}
2646unsafe extern "C" {
2647 pub fn drmDelContextTag(fd: ::core::ffi::c_int, context: drm_context_t) -> ::core::ffi::c_int;
2648}
2649unsafe extern "C" {
2650 pub fn drmGetContextTag(
2651 fd: ::core::ffi::c_int,
2652 context: drm_context_t,
2653 ) -> *mut ::core::ffi::c_void;
2654}
2655unsafe extern "C" {
2656 pub fn drmGetReservedContextList(
2657 fd: ::core::ffi::c_int,
2658 count: *mut ::core::ffi::c_int,
2659 ) -> *mut drm_context_t;
2660}
2661unsafe extern "C" {
2662 pub fn drmFreeReservedContextList(arg1: *mut drm_context_t);
2663}
2664unsafe extern "C" {
2665 pub fn drmSwitchToContext(fd: ::core::ffi::c_int, context: drm_context_t)
2666 -> ::core::ffi::c_int;
2667}
2668unsafe extern "C" {
2669 pub fn drmDestroyContext(fd: ::core::ffi::c_int, handle: drm_context_t) -> ::core::ffi::c_int;
2670}
2671unsafe extern "C" {
2672 pub fn drmCreateDrawable(
2673 fd: ::core::ffi::c_int,
2674 handle: *mut drm_drawable_t,
2675 ) -> ::core::ffi::c_int;
2676}
2677unsafe extern "C" {
2678 pub fn drmDestroyDrawable(fd: ::core::ffi::c_int, handle: drm_drawable_t)
2679 -> ::core::ffi::c_int;
2680}
2681unsafe extern "C" {
2682 pub fn drmUpdateDrawableInfo(
2683 fd: ::core::ffi::c_int,
2684 handle: drm_drawable_t,
2685 type_: drm_drawable_info_type_t,
2686 num: ::core::ffi::c_uint,
2687 data: *mut ::core::ffi::c_void,
2688 ) -> ::core::ffi::c_int;
2689}
2690unsafe extern "C" {
2691 pub fn drmCtlInstHandler(fd: ::core::ffi::c_int, irq: ::core::ffi::c_int)
2692 -> ::core::ffi::c_int;
2693}
2694unsafe extern "C" {
2695 pub fn drmCtlUninstHandler(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2696}
2697unsafe extern "C" {
2698 pub fn drmSetClientCap(
2699 fd: ::core::ffi::c_int,
2700 capability: u64,
2701 value: u64,
2702 ) -> ::core::ffi::c_int;
2703}
2704unsafe extern "C" {
2705 pub fn drmCrtcGetSequence(
2706 fd: ::core::ffi::c_int,
2707 crtcId: u32,
2708 sequence: *mut u64,
2709 ns: *mut u64,
2710 ) -> ::core::ffi::c_int;
2711}
2712unsafe extern "C" {
2713 pub fn drmCrtcQueueSequence(
2714 fd: ::core::ffi::c_int,
2715 crtcId: u32,
2716 flags: u32,
2717 sequence: u64,
2718 sequence_queued: *mut u64,
2719 user_data: u64,
2720 ) -> ::core::ffi::c_int;
2721}
2722unsafe extern "C" {
2723 pub fn drmMap(
2724 fd: ::core::ffi::c_int,
2725 handle: drm_handle_t,
2726 size: drmSize,
2727 address: drmAddressPtr,
2728 ) -> ::core::ffi::c_int;
2729}
2730unsafe extern "C" {
2731 pub fn drmUnmap(address: drmAddress, size: drmSize) -> ::core::ffi::c_int;
2732}
2733unsafe extern "C" {
2734 pub fn drmGetBufInfo(fd: ::core::ffi::c_int) -> drmBufInfoPtr;
2735}
2736unsafe extern "C" {
2737 pub fn drmMapBufs(fd: ::core::ffi::c_int) -> drmBufMapPtr;
2738}
2739unsafe extern "C" {
2740 pub fn drmUnmapBufs(bufs: drmBufMapPtr) -> ::core::ffi::c_int;
2741}
2742unsafe extern "C" {
2743 pub fn drmDMA(fd: ::core::ffi::c_int, request: drmDMAReqPtr) -> ::core::ffi::c_int;
2744}
2745unsafe extern "C" {
2746 pub fn drmFreeBufs(
2747 fd: ::core::ffi::c_int,
2748 count: ::core::ffi::c_int,
2749 list: *mut ::core::ffi::c_int,
2750 ) -> ::core::ffi::c_int;
2751}
2752unsafe extern "C" {
2753 pub fn drmGetLock(
2754 fd: ::core::ffi::c_int,
2755 context: drm_context_t,
2756 flags: drmLockFlags,
2757 ) -> ::core::ffi::c_int;
2758}
2759unsafe extern "C" {
2760 pub fn drmUnlock(fd: ::core::ffi::c_int, context: drm_context_t) -> ::core::ffi::c_int;
2761}
2762unsafe extern "C" {
2763 pub fn drmFinish(
2764 fd: ::core::ffi::c_int,
2765 context: ::core::ffi::c_int,
2766 flags: drmLockFlags,
2767 ) -> ::core::ffi::c_int;
2768}
2769unsafe extern "C" {
2770 pub fn drmGetContextPrivateMapping(
2771 fd: ::core::ffi::c_int,
2772 ctx_id: drm_context_t,
2773 handle: *mut drm_handle_t,
2774 ) -> ::core::ffi::c_int;
2775}
2776unsafe extern "C" {
2777 pub fn drmAgpAcquire(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2778}
2779unsafe extern "C" {
2780 pub fn drmAgpRelease(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2781}
2782unsafe extern "C" {
2783 pub fn drmAgpEnable(fd: ::core::ffi::c_int, mode: ::core::ffi::c_ulong) -> ::core::ffi::c_int;
2784}
2785unsafe extern "C" {
2786 pub fn drmAgpAlloc(
2787 fd: ::core::ffi::c_int,
2788 size: ::core::ffi::c_ulong,
2789 type_: ::core::ffi::c_ulong,
2790 address: *mut ::core::ffi::c_ulong,
2791 handle: *mut drm_handle_t,
2792 ) -> ::core::ffi::c_int;
2793}
2794unsafe extern "C" {
2795 pub fn drmAgpFree(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
2796}
2797unsafe extern "C" {
2798 pub fn drmAgpBind(
2799 fd: ::core::ffi::c_int,
2800 handle: drm_handle_t,
2801 offset: ::core::ffi::c_ulong,
2802 ) -> ::core::ffi::c_int;
2803}
2804unsafe extern "C" {
2805 pub fn drmAgpUnbind(fd: ::core::ffi::c_int, handle: drm_handle_t) -> ::core::ffi::c_int;
2806}
2807unsafe extern "C" {
2808 pub fn drmAgpVersionMajor(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2809}
2810unsafe extern "C" {
2811 pub fn drmAgpVersionMinor(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2812}
2813unsafe extern "C" {
2814 pub fn drmAgpGetMode(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
2815}
2816unsafe extern "C" {
2817 pub fn drmAgpBase(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
2818}
2819unsafe extern "C" {
2820 pub fn drmAgpSize(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
2821}
2822unsafe extern "C" {
2823 pub fn drmAgpMemoryUsed(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
2824}
2825unsafe extern "C" {
2826 pub fn drmAgpMemoryAvail(fd: ::core::ffi::c_int) -> ::core::ffi::c_ulong;
2827}
2828unsafe extern "C" {
2829 pub fn drmAgpVendorId(fd: ::core::ffi::c_int) -> ::core::ffi::c_uint;
2830}
2831unsafe extern "C" {
2832 pub fn drmAgpDeviceId(fd: ::core::ffi::c_int) -> ::core::ffi::c_uint;
2833}
2834unsafe extern "C" {
2835 pub fn drmScatterGatherAlloc(
2836 fd: ::core::ffi::c_int,
2837 size: ::core::ffi::c_ulong,
2838 handle: *mut drm_handle_t,
2839 ) -> ::core::ffi::c_int;
2840}
2841unsafe extern "C" {
2842 pub fn drmScatterGatherFree(fd: ::core::ffi::c_int, handle: drm_handle_t)
2843 -> ::core::ffi::c_int;
2844}
2845unsafe extern "C" {
2846 pub fn drmWaitVBlank(fd: ::core::ffi::c_int, vbl: drmVBlankPtr) -> ::core::ffi::c_int;
2847}
2848unsafe extern "C" {
2849 pub fn drmSetServerInfo(info: drmServerInfoPtr);
2850}
2851unsafe extern "C" {
2852 pub fn drmError(
2853 err: ::core::ffi::c_int,
2854 label: *const ::core::ffi::c_char,
2855 ) -> ::core::ffi::c_int;
2856}
2857unsafe extern "C" {
2858 pub fn drmMalloc(size: ::core::ffi::c_int) -> *mut ::core::ffi::c_void;
2859}
2860unsafe extern "C" {
2861 pub fn drmFree(pt: *mut ::core::ffi::c_void);
2862}
2863unsafe extern "C" {
2864 pub fn drmHashCreate() -> *mut ::core::ffi::c_void;
2865}
2866unsafe extern "C" {
2867 pub fn drmHashDestroy(t: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
2868}
2869unsafe extern "C" {
2870 pub fn drmHashLookup(
2871 t: *mut ::core::ffi::c_void,
2872 key: ::core::ffi::c_ulong,
2873 value: *mut *mut ::core::ffi::c_void,
2874 ) -> ::core::ffi::c_int;
2875}
2876unsafe extern "C" {
2877 pub fn drmHashInsert(
2878 t: *mut ::core::ffi::c_void,
2879 key: ::core::ffi::c_ulong,
2880 value: *mut ::core::ffi::c_void,
2881 ) -> ::core::ffi::c_int;
2882}
2883unsafe extern "C" {
2884 pub fn drmHashDelete(
2885 t: *mut ::core::ffi::c_void,
2886 key: ::core::ffi::c_ulong,
2887 ) -> ::core::ffi::c_int;
2888}
2889unsafe extern "C" {
2890 pub fn drmHashFirst(
2891 t: *mut ::core::ffi::c_void,
2892 key: *mut ::core::ffi::c_ulong,
2893 value: *mut *mut ::core::ffi::c_void,
2894 ) -> ::core::ffi::c_int;
2895}
2896unsafe extern "C" {
2897 pub fn drmHashNext(
2898 t: *mut ::core::ffi::c_void,
2899 key: *mut ::core::ffi::c_ulong,
2900 value: *mut *mut ::core::ffi::c_void,
2901 ) -> ::core::ffi::c_int;
2902}
2903unsafe extern "C" {
2904 pub fn drmRandomCreate(seed: ::core::ffi::c_ulong) -> *mut ::core::ffi::c_void;
2905}
2906unsafe extern "C" {
2907 pub fn drmRandomDestroy(state: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
2908}
2909unsafe extern "C" {
2910 pub fn drmRandom(state: *mut ::core::ffi::c_void) -> ::core::ffi::c_ulong;
2911}
2912unsafe extern "C" {
2913 pub fn drmRandomDouble(state: *mut ::core::ffi::c_void) -> f64;
2914}
2915unsafe extern "C" {
2916 pub fn drmSLCreate() -> *mut ::core::ffi::c_void;
2917}
2918unsafe extern "C" {
2919 pub fn drmSLDestroy(l: *mut ::core::ffi::c_void) -> ::core::ffi::c_int;
2920}
2921unsafe extern "C" {
2922 pub fn drmSLLookup(
2923 l: *mut ::core::ffi::c_void,
2924 key: ::core::ffi::c_ulong,
2925 value: *mut *mut ::core::ffi::c_void,
2926 ) -> ::core::ffi::c_int;
2927}
2928unsafe extern "C" {
2929 pub fn drmSLInsert(
2930 l: *mut ::core::ffi::c_void,
2931 key: ::core::ffi::c_ulong,
2932 value: *mut ::core::ffi::c_void,
2933 ) -> ::core::ffi::c_int;
2934}
2935unsafe extern "C" {
2936 pub fn drmSLDelete(
2937 l: *mut ::core::ffi::c_void,
2938 key: ::core::ffi::c_ulong,
2939 ) -> ::core::ffi::c_int;
2940}
2941unsafe extern "C" {
2942 pub fn drmSLNext(
2943 l: *mut ::core::ffi::c_void,
2944 key: *mut ::core::ffi::c_ulong,
2945 value: *mut *mut ::core::ffi::c_void,
2946 ) -> ::core::ffi::c_int;
2947}
2948unsafe extern "C" {
2949 pub fn drmSLFirst(
2950 l: *mut ::core::ffi::c_void,
2951 key: *mut ::core::ffi::c_ulong,
2952 value: *mut *mut ::core::ffi::c_void,
2953 ) -> ::core::ffi::c_int;
2954}
2955unsafe extern "C" {
2956 pub fn drmSLDump(l: *mut ::core::ffi::c_void);
2957}
2958unsafe extern "C" {
2959 pub fn drmSLLookupNeighbors(
2960 l: *mut ::core::ffi::c_void,
2961 key: ::core::ffi::c_ulong,
2962 prev_key: *mut ::core::ffi::c_ulong,
2963 prev_value: *mut *mut ::core::ffi::c_void,
2964 next_key: *mut ::core::ffi::c_ulong,
2965 next_value: *mut *mut ::core::ffi::c_void,
2966 ) -> ::core::ffi::c_int;
2967}
2968unsafe extern "C" {
2969 pub fn drmOpenOnce(
2970 unused: *mut ::core::ffi::c_void,
2971 BusID: *const ::core::ffi::c_char,
2972 newlyopened: *mut ::core::ffi::c_int,
2973 ) -> ::core::ffi::c_int;
2974}
2975unsafe extern "C" {
2976 pub fn drmOpenOnceWithType(
2977 BusID: *const ::core::ffi::c_char,
2978 newlyopened: *mut ::core::ffi::c_int,
2979 type_: ::core::ffi::c_int,
2980 ) -> ::core::ffi::c_int;
2981}
2982unsafe extern "C" {
2983 pub fn drmCloseOnce(fd: ::core::ffi::c_int);
2984}
2985unsafe extern "C" {
2986 pub fn drmMsg(format: *const ::core::ffi::c_char, ...);
2987}
2988unsafe extern "C" {
2989 pub fn drmSetMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2990}
2991unsafe extern "C" {
2992 pub fn drmDropMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2993}
2994unsafe extern "C" {
2995 pub fn drmIsMaster(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
2996}
2997#[repr(C)]
2998#[derive(Debug, Copy, Clone)]
2999pub struct _drmEventContext {
3000 pub version: ::core::ffi::c_int,
3001 pub vblank_handler: ::core::option::Option<
3002 unsafe extern "C" fn(
3003 fd: ::core::ffi::c_int,
3004 sequence: ::core::ffi::c_uint,
3005 tv_sec: ::core::ffi::c_uint,
3006 tv_usec: ::core::ffi::c_uint,
3007 user_data: *mut ::core::ffi::c_void,
3008 ),
3009 >,
3010 pub page_flip_handler: ::core::option::Option<
3011 unsafe extern "C" fn(
3012 fd: ::core::ffi::c_int,
3013 sequence: ::core::ffi::c_uint,
3014 tv_sec: ::core::ffi::c_uint,
3015 tv_usec: ::core::ffi::c_uint,
3016 user_data: *mut ::core::ffi::c_void,
3017 ),
3018 >,
3019 pub page_flip_handler2: ::core::option::Option<
3020 unsafe extern "C" fn(
3021 fd: ::core::ffi::c_int,
3022 sequence: ::core::ffi::c_uint,
3023 tv_sec: ::core::ffi::c_uint,
3024 tv_usec: ::core::ffi::c_uint,
3025 crtc_id: ::core::ffi::c_uint,
3026 user_data: *mut ::core::ffi::c_void,
3027 ),
3028 >,
3029 pub sequence_handler: ::core::option::Option<
3030 unsafe extern "C" fn(fd: ::core::ffi::c_int, sequence: u64, ns: u64, user_data: u64),
3031 >,
3032}
3033pub type drmEventContext = _drmEventContext;
3034pub type drmEventContextPtr = *mut _drmEventContext;
3035unsafe extern "C" {
3036 pub fn drmHandleEvent(fd: ::core::ffi::c_int, evctx: drmEventContextPtr) -> ::core::ffi::c_int;
3037}
3038unsafe extern "C" {
3039 pub fn drmGetDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3040}
3041unsafe extern "C" {
3042 pub fn drmGetDeviceNameFromFd2(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3043}
3044unsafe extern "C" {
3045 pub fn drmGetNodeTypeFromFd(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3046}
3047unsafe extern "C" {
3048 pub fn drmPrimeHandleToFD(
3049 fd: ::core::ffi::c_int,
3050 handle: u32,
3051 flags: u32,
3052 prime_fd: *mut ::core::ffi::c_int,
3053 ) -> ::core::ffi::c_int;
3054}
3055unsafe extern "C" {
3056 pub fn drmPrimeFDToHandle(
3057 fd: ::core::ffi::c_int,
3058 prime_fd: ::core::ffi::c_int,
3059 handle: *mut u32,
3060 ) -> ::core::ffi::c_int;
3061}
3062unsafe extern "C" {
3063 pub fn drmCloseBufferHandle(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
3064}
3065unsafe extern "C" {
3066 pub fn drmGetPrimaryDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3067}
3068unsafe extern "C" {
3069 pub fn drmGetRenderDeviceNameFromFd(fd: ::core::ffi::c_int) -> *mut ::core::ffi::c_char;
3070}
3071#[repr(C)]
3072#[derive(Debug, Copy, Clone)]
3073pub struct _drmPciBusInfo {
3074 pub domain: u16,
3075 pub bus: u8,
3076 pub dev: u8,
3077 pub func: u8,
3078}
3079pub type drmPciBusInfo = _drmPciBusInfo;
3080pub type drmPciBusInfoPtr = *mut _drmPciBusInfo;
3081#[repr(C)]
3082#[derive(Debug, Copy, Clone)]
3083pub struct _drmPciDeviceInfo {
3084 pub vendor_id: u16,
3085 pub device_id: u16,
3086 pub subvendor_id: u16,
3087 pub subdevice_id: u16,
3088 pub revision_id: u8,
3089}
3090pub type drmPciDeviceInfo = _drmPciDeviceInfo;
3091pub type drmPciDeviceInfoPtr = *mut _drmPciDeviceInfo;
3092#[repr(C)]
3093#[derive(Debug, Copy, Clone)]
3094pub struct _drmUsbBusInfo {
3095 pub bus: u8,
3096 pub dev: u8,
3097}
3098pub type drmUsbBusInfo = _drmUsbBusInfo;
3099pub type drmUsbBusInfoPtr = *mut _drmUsbBusInfo;
3100#[repr(C)]
3101#[derive(Debug, Copy, Clone)]
3102pub struct _drmUsbDeviceInfo {
3103 pub vendor: u16,
3104 pub product: u16,
3105}
3106pub type drmUsbDeviceInfo = _drmUsbDeviceInfo;
3107pub type drmUsbDeviceInfoPtr = *mut _drmUsbDeviceInfo;
3108#[repr(C)]
3109#[derive(Debug, Copy, Clone)]
3110pub struct _drmPlatformBusInfo {
3111 pub fullname: [::core::ffi::c_char; 512usize],
3112}
3113pub type drmPlatformBusInfo = _drmPlatformBusInfo;
3114pub type drmPlatformBusInfoPtr = *mut _drmPlatformBusInfo;
3115#[repr(C)]
3116#[derive(Debug, Copy, Clone)]
3117pub struct _drmPlatformDeviceInfo {
3118 pub compatible: *mut *mut ::core::ffi::c_char,
3119}
3120pub type drmPlatformDeviceInfo = _drmPlatformDeviceInfo;
3121pub type drmPlatformDeviceInfoPtr = *mut _drmPlatformDeviceInfo;
3122#[repr(C)]
3123#[derive(Debug, Copy, Clone)]
3124pub struct _drmHost1xBusInfo {
3125 pub fullname: [::core::ffi::c_char; 512usize],
3126}
3127pub type drmHost1xBusInfo = _drmHost1xBusInfo;
3128pub type drmHost1xBusInfoPtr = *mut _drmHost1xBusInfo;
3129#[repr(C)]
3130#[derive(Debug, Copy, Clone)]
3131pub struct _drmHost1xDeviceInfo {
3132 pub compatible: *mut *mut ::core::ffi::c_char,
3133}
3134pub type drmHost1xDeviceInfo = _drmHost1xDeviceInfo;
3135pub type drmHost1xDeviceInfoPtr = *mut _drmHost1xDeviceInfo;
3136#[repr(C)]
3137#[derive(Copy, Clone)]
3138pub struct _drmDevice {
3139 pub nodes: *mut *mut ::core::ffi::c_char,
3140 pub available_nodes: ::core::ffi::c_int,
3141 pub bustype: ::core::ffi::c_int,
3142 pub businfo: _drmDevice__bindgen_ty_1,
3143 pub deviceinfo: _drmDevice__bindgen_ty_2,
3144}
3145#[repr(C)]
3146#[derive(Copy, Clone)]
3147pub union _drmDevice__bindgen_ty_1 {
3148 pub pci: drmPciBusInfoPtr,
3149 pub usb: drmUsbBusInfoPtr,
3150 pub platform: drmPlatformBusInfoPtr,
3151 pub host1x: drmHost1xBusInfoPtr,
3152}
3153#[repr(C)]
3154#[derive(Copy, Clone)]
3155pub union _drmDevice__bindgen_ty_2 {
3156 pub pci: drmPciDeviceInfoPtr,
3157 pub usb: drmUsbDeviceInfoPtr,
3158 pub platform: drmPlatformDeviceInfoPtr,
3159 pub host1x: drmHost1xDeviceInfoPtr,
3160}
3161pub type drmDevice = _drmDevice;
3162pub type drmDevicePtr = *mut _drmDevice;
3163unsafe extern "C" {
3164 pub fn drmGetDevice(fd: ::core::ffi::c_int, device: *mut drmDevicePtr) -> ::core::ffi::c_int;
3165}
3166unsafe extern "C" {
3167 pub fn drmFreeDevice(device: *mut drmDevicePtr);
3168}
3169unsafe extern "C" {
3170 pub fn drmGetDevices(
3171 devices: *mut drmDevicePtr,
3172 max_devices: ::core::ffi::c_int,
3173 ) -> ::core::ffi::c_int;
3174}
3175unsafe extern "C" {
3176 pub fn drmFreeDevices(devices: *mut drmDevicePtr, count: ::core::ffi::c_int);
3177}
3178unsafe extern "C" {
3179 pub fn drmGetDevice2(
3180 fd: ::core::ffi::c_int,
3181 flags: u32,
3182 device: *mut drmDevicePtr,
3183 ) -> ::core::ffi::c_int;
3184}
3185unsafe extern "C" {
3186 pub fn drmGetDevices2(
3187 flags: u32,
3188 devices: *mut drmDevicePtr,
3189 max_devices: ::core::ffi::c_int,
3190 ) -> ::core::ffi::c_int;
3191}
3192unsafe extern "C" {
3193 pub fn drmGetDeviceFromDevId(
3194 dev_id: dev_t,
3195 flags: u32,
3196 device: *mut drmDevicePtr,
3197 ) -> ::core::ffi::c_int;
3198}
3199unsafe extern "C" {
3200 pub fn drmGetNodeTypeFromDevId(devid: dev_t) -> ::core::ffi::c_int;
3201}
3202unsafe extern "C" {
3203 pub fn drmDevicesEqual(a: drmDevicePtr, b: drmDevicePtr) -> ::core::ffi::c_int;
3204}
3205unsafe extern "C" {
3206 pub fn drmSyncobjCreate(
3207 fd: ::core::ffi::c_int,
3208 flags: u32,
3209 handle: *mut u32,
3210 ) -> ::core::ffi::c_int;
3211}
3212unsafe extern "C" {
3213 pub fn drmSyncobjDestroy(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
3214}
3215unsafe extern "C" {
3216 pub fn drmSyncobjHandleToFD(
3217 fd: ::core::ffi::c_int,
3218 handle: u32,
3219 obj_fd: *mut ::core::ffi::c_int,
3220 ) -> ::core::ffi::c_int;
3221}
3222unsafe extern "C" {
3223 pub fn drmSyncobjFDToHandle(
3224 fd: ::core::ffi::c_int,
3225 obj_fd: ::core::ffi::c_int,
3226 handle: *mut u32,
3227 ) -> ::core::ffi::c_int;
3228}
3229unsafe extern "C" {
3230 pub fn drmSyncobjImportSyncFile(
3231 fd: ::core::ffi::c_int,
3232 handle: u32,
3233 sync_file_fd: ::core::ffi::c_int,
3234 ) -> ::core::ffi::c_int;
3235}
3236unsafe extern "C" {
3237 pub fn drmSyncobjExportSyncFile(
3238 fd: ::core::ffi::c_int,
3239 handle: u32,
3240 sync_file_fd: *mut ::core::ffi::c_int,
3241 ) -> ::core::ffi::c_int;
3242}
3243unsafe extern "C" {
3244 pub fn drmSyncobjWait(
3245 fd: ::core::ffi::c_int,
3246 handles: *mut u32,
3247 num_handles: ::core::ffi::c_uint,
3248 timeout_nsec: i64,
3249 flags: ::core::ffi::c_uint,
3250 first_signaled: *mut u32,
3251 ) -> ::core::ffi::c_int;
3252}
3253unsafe extern "C" {
3254 pub fn drmSyncobjReset(
3255 fd: ::core::ffi::c_int,
3256 handles: *const u32,
3257 handle_count: u32,
3258 ) -> ::core::ffi::c_int;
3259}
3260unsafe extern "C" {
3261 pub fn drmSyncobjSignal(
3262 fd: ::core::ffi::c_int,
3263 handles: *const u32,
3264 handle_count: u32,
3265 ) -> ::core::ffi::c_int;
3266}
3267unsafe extern "C" {
3268 pub fn drmSyncobjTimelineSignal(
3269 fd: ::core::ffi::c_int,
3270 handles: *const u32,
3271 points: *mut u64,
3272 handle_count: u32,
3273 ) -> ::core::ffi::c_int;
3274}
3275unsafe extern "C" {
3276 pub fn drmSyncobjTimelineWait(
3277 fd: ::core::ffi::c_int,
3278 handles: *mut u32,
3279 points: *mut u64,
3280 num_handles: ::core::ffi::c_uint,
3281 timeout_nsec: i64,
3282 flags: ::core::ffi::c_uint,
3283 first_signaled: *mut u32,
3284 ) -> ::core::ffi::c_int;
3285}
3286unsafe extern "C" {
3287 pub fn drmSyncobjQuery(
3288 fd: ::core::ffi::c_int,
3289 handles: *mut u32,
3290 points: *mut u64,
3291 handle_count: u32,
3292 ) -> ::core::ffi::c_int;
3293}
3294unsafe extern "C" {
3295 pub fn drmSyncobjQuery2(
3296 fd: ::core::ffi::c_int,
3297 handles: *mut u32,
3298 points: *mut u64,
3299 handle_count: u32,
3300 flags: u32,
3301 ) -> ::core::ffi::c_int;
3302}
3303unsafe extern "C" {
3304 pub fn drmSyncobjTransfer(
3305 fd: ::core::ffi::c_int,
3306 dst_handle: u32,
3307 dst_point: u64,
3308 src_handle: u32,
3309 src_point: u64,
3310 flags: u32,
3311 ) -> ::core::ffi::c_int;
3312}
3313unsafe extern "C" {
3314 pub fn drmSyncobjEventfd(
3315 fd: ::core::ffi::c_int,
3316 handle: u32,
3317 point: u64,
3318 ev_fd: ::core::ffi::c_int,
3319 flags: u32,
3320 ) -> ::core::ffi::c_int;
3321}
3322unsafe extern "C" {
3323 pub fn drmGetFormatModifierVendor(modifier: u64) -> *mut ::core::ffi::c_char;
3324}
3325unsafe extern "C" {
3326 pub fn drmGetFormatModifierName(modifier: u64) -> *mut ::core::ffi::c_char;
3327}
3328unsafe extern "C" {
3329 pub fn drmGetFormatName(format: u32) -> *mut ::core::ffi::c_char;
3330}
3331pub type wchar_t = ::core::ffi::c_int;
3332#[repr(C)]
3333#[repr(align(16))]
3334#[derive(Debug, Copy, Clone)]
3335pub struct max_align_t {
3336 pub __clang_max_align_nonce1: ::core::ffi::c_longlong,
3337 pub __bindgen_padding_0: u64,
3338 pub __clang_max_align_nonce2: u128,
3339}
3340#[repr(C)]
3341#[derive(Debug, Copy, Clone)]
3342pub struct _drmModeRes {
3343 pub count_fbs: ::core::ffi::c_int,
3344 pub fbs: *mut u32,
3345 pub count_crtcs: ::core::ffi::c_int,
3346 pub crtcs: *mut u32,
3347 pub count_connectors: ::core::ffi::c_int,
3348 pub connectors: *mut u32,
3349 pub count_encoders: ::core::ffi::c_int,
3350 pub encoders: *mut u32,
3351 pub min_width: u32,
3352 pub max_width: u32,
3353 pub min_height: u32,
3354 pub max_height: u32,
3355}
3356pub type drmModeRes = _drmModeRes;
3357pub type drmModeResPtr = *mut _drmModeRes;
3358#[repr(C)]
3359#[derive(Debug, Copy, Clone)]
3360pub struct _drmModeModeInfo {
3361 pub clock: u32,
3362 pub hdisplay: u16,
3363 pub hsync_start: u16,
3364 pub hsync_end: u16,
3365 pub htotal: u16,
3366 pub hskew: u16,
3367 pub vdisplay: u16,
3368 pub vsync_start: u16,
3369 pub vsync_end: u16,
3370 pub vtotal: u16,
3371 pub vscan: u16,
3372 pub vrefresh: u32,
3373 pub flags: u32,
3374 pub type_: u32,
3375 pub name: [::core::ffi::c_char; 32usize],
3376}
3377pub type drmModeModeInfo = _drmModeModeInfo;
3378pub type drmModeModeInfoPtr = *mut _drmModeModeInfo;
3379#[repr(C)]
3380#[derive(Debug, Copy, Clone)]
3381pub struct _drmModeFB {
3382 pub fb_id: u32,
3383 pub width: u32,
3384 pub height: u32,
3385 pub pitch: u32,
3386 pub bpp: u32,
3387 pub depth: u32,
3388 pub handle: u32,
3389}
3390pub type drmModeFB = _drmModeFB;
3391pub type drmModeFBPtr = *mut _drmModeFB;
3392#[repr(C)]
3393#[derive(Debug, Copy, Clone)]
3394pub struct _drmModeFB2 {
3395 pub fb_id: u32,
3396 pub width: u32,
3397 pub height: u32,
3398 pub pixel_format: u32,
3399 pub modifier: u64,
3400 pub flags: u32,
3401 pub handles: [u32; 4usize],
3402 pub pitches: [u32; 4usize],
3403 pub offsets: [u32; 4usize],
3404}
3405pub type drmModeFB2 = _drmModeFB2;
3406pub type drmModeFB2Ptr = *mut _drmModeFB2;
3407pub type drmModeClip = drm_clip_rect;
3408pub type drmModeClipPtr = *mut drm_clip_rect;
3409#[repr(C)]
3410#[derive(Debug, Copy, Clone)]
3411pub struct _drmModePropertyBlob {
3412 pub id: u32,
3413 pub length: u32,
3414 pub data: *mut ::core::ffi::c_void,
3415}
3416pub type drmModePropertyBlobRes = _drmModePropertyBlob;
3417pub type drmModePropertyBlobPtr = *mut _drmModePropertyBlob;
3418#[repr(C)]
3419#[derive(Debug, Copy, Clone)]
3420pub struct _drmModeProperty {
3421 pub prop_id: u32,
3422 pub flags: u32,
3423 pub name: [::core::ffi::c_char; 32usize],
3424 pub count_values: ::core::ffi::c_int,
3425 pub values: *mut u64,
3426 pub count_enums: ::core::ffi::c_int,
3427 pub enums: *mut drm_mode_property_enum,
3428 pub count_blobs: ::core::ffi::c_int,
3429 pub blob_ids: *mut u32,
3430}
3431pub type drmModePropertyRes = _drmModeProperty;
3432pub type drmModePropertyPtr = *mut _drmModeProperty;
3433#[repr(C)]
3434#[derive(Debug, Copy, Clone)]
3435pub struct _drmModeCrtc {
3436 pub crtc_id: u32,
3437 pub buffer_id: u32,
3438 pub x: u32,
3439 pub y: u32,
3440 pub width: u32,
3441 pub height: u32,
3442 pub mode_valid: ::core::ffi::c_int,
3443 pub mode: drmModeModeInfo,
3444 pub gamma_size: ::core::ffi::c_int,
3445}
3446pub type drmModeCrtc = _drmModeCrtc;
3447pub type drmModeCrtcPtr = *mut _drmModeCrtc;
3448#[repr(C)]
3449#[derive(Debug, Copy, Clone)]
3450pub struct _drmModeEncoder {
3451 pub encoder_id: u32,
3452 pub encoder_type: u32,
3453 pub crtc_id: u32,
3454 pub possible_crtcs: u32,
3455 pub possible_clones: u32,
3456}
3457pub type drmModeEncoder = _drmModeEncoder;
3458pub type drmModeEncoderPtr = *mut _drmModeEncoder;
3459pub const drmModeConnection_DRM_MODE_CONNECTED: drmModeConnection = 1;
3460pub const drmModeConnection_DRM_MODE_DISCONNECTED: drmModeConnection = 2;
3461pub const drmModeConnection_DRM_MODE_UNKNOWNCONNECTION: drmModeConnection = 3;
3462pub type drmModeConnection = ::core::ffi::c_uint;
3463pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_UNKNOWN: drmModeSubPixel = 1;
3464pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_HORIZONTAL_RGB: drmModeSubPixel = 2;
3465pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_HORIZONTAL_BGR: drmModeSubPixel = 3;
3466pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_VERTICAL_RGB: drmModeSubPixel = 4;
3467pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_VERTICAL_BGR: drmModeSubPixel = 5;
3468pub const drmModeSubPixel_DRM_MODE_SUBPIXEL_NONE: drmModeSubPixel = 6;
3469pub type drmModeSubPixel = ::core::ffi::c_uint;
3470#[repr(C)]
3471#[derive(Debug, Copy, Clone)]
3472pub struct _drmModeConnector {
3473 pub connector_id: u32,
3474 pub encoder_id: u32,
3475 pub connector_type: u32,
3476 pub connector_type_id: u32,
3477 pub connection: drmModeConnection,
3478 pub mmWidth: u32,
3479 pub mmHeight: u32,
3480 pub subpixel: drmModeSubPixel,
3481 pub count_modes: ::core::ffi::c_int,
3482 pub modes: drmModeModeInfoPtr,
3483 pub count_props: ::core::ffi::c_int,
3484 pub props: *mut u32,
3485 pub prop_values: *mut u64,
3486 pub count_encoders: ::core::ffi::c_int,
3487 pub encoders: *mut u32,
3488}
3489pub type drmModeConnector = _drmModeConnector;
3490pub type drmModeConnectorPtr = *mut _drmModeConnector;
3491#[repr(C)]
3492#[derive(Debug, Copy, Clone)]
3493pub struct _drmModeObjectProperties {
3494 pub count_props: u32,
3495 pub props: *mut u32,
3496 pub prop_values: *mut u64,
3497}
3498pub type drmModeObjectProperties = _drmModeObjectProperties;
3499pub type drmModeObjectPropertiesPtr = *mut _drmModeObjectProperties;
3500#[repr(C)]
3501#[derive(Debug, Copy, Clone)]
3502pub struct _drmModeFormatModifierIterator {
3503 pub fmt_idx: u32,
3504 pub mod_idx: u32,
3505 pub fmt: u32,
3506 pub mod_: u64,
3507}
3508pub type drmModeFormatModifierIterator = _drmModeFormatModifierIterator;
3509#[repr(C)]
3510#[derive(Debug, Copy, Clone)]
3511pub struct _drmModePlane {
3512 pub count_formats: u32,
3513 pub formats: *mut u32,
3514 pub plane_id: u32,
3515 pub crtc_id: u32,
3516 pub fb_id: u32,
3517 pub crtc_x: u32,
3518 pub crtc_y: u32,
3519 pub x: u32,
3520 pub y: u32,
3521 pub possible_crtcs: u32,
3522 pub gamma_size: u32,
3523}
3524pub type drmModePlane = _drmModePlane;
3525pub type drmModePlanePtr = *mut _drmModePlane;
3526#[repr(C)]
3527#[derive(Debug, Copy, Clone)]
3528pub struct _drmModePlaneRes {
3529 pub count_planes: u32,
3530 pub planes: *mut u32,
3531}
3532pub type drmModePlaneRes = _drmModePlaneRes;
3533pub type drmModePlaneResPtr = *mut _drmModePlaneRes;
3534unsafe extern "C" {
3535 pub fn drmModeFreeModeInfo(ptr: drmModeModeInfoPtr);
3536}
3537unsafe extern "C" {
3538 pub fn drmModeFreeResources(ptr: drmModeResPtr);
3539}
3540unsafe extern "C" {
3541 pub fn drmModeFreeFB(ptr: drmModeFBPtr);
3542}
3543unsafe extern "C" {
3544 pub fn drmModeFreeFB2(ptr: drmModeFB2Ptr);
3545}
3546unsafe extern "C" {
3547 pub fn drmModeFreeCrtc(ptr: drmModeCrtcPtr);
3548}
3549unsafe extern "C" {
3550 pub fn drmModeFreeConnector(ptr: drmModeConnectorPtr);
3551}
3552unsafe extern "C" {
3553 pub fn drmModeFreeEncoder(ptr: drmModeEncoderPtr);
3554}
3555unsafe extern "C" {
3556 pub fn drmModeFreePlane(ptr: drmModePlanePtr);
3557}
3558unsafe extern "C" {
3559 pub fn drmModeFreePlaneResources(ptr: drmModePlaneResPtr);
3560}
3561unsafe extern "C" {
3562 pub fn drmIsKMS(fd: ::core::ffi::c_int) -> ::core::ffi::c_int;
3563}
3564unsafe extern "C" {
3565 pub fn drmModeGetResources(fd: ::core::ffi::c_int) -> drmModeResPtr;
3566}
3567unsafe extern "C" {
3568 pub fn drmModeGetFB(fd: ::core::ffi::c_int, bufferId: u32) -> drmModeFBPtr;
3569}
3570unsafe extern "C" {
3571 pub fn drmModeGetFB2(fd: ::core::ffi::c_int, bufferId: u32) -> drmModeFB2Ptr;
3572}
3573unsafe extern "C" {
3574 pub fn drmModeAddFB(
3575 fd: ::core::ffi::c_int,
3576 width: u32,
3577 height: u32,
3578 depth: u8,
3579 bpp: u8,
3580 pitch: u32,
3581 bo_handle: u32,
3582 buf_id: *mut u32,
3583 ) -> ::core::ffi::c_int;
3584}
3585unsafe extern "C" {
3586 pub fn drmModeAddFB2(
3587 fd: ::core::ffi::c_int,
3588 width: u32,
3589 height: u32,
3590 pixel_format: u32,
3591 bo_handles: *const u32,
3592 pitches: *const u32,
3593 offsets: *const u32,
3594 buf_id: *mut u32,
3595 flags: u32,
3596 ) -> ::core::ffi::c_int;
3597}
3598unsafe extern "C" {
3599 pub fn drmModeAddFB2WithModifiers(
3600 fd: ::core::ffi::c_int,
3601 width: u32,
3602 height: u32,
3603 pixel_format: u32,
3604 bo_handles: *const u32,
3605 pitches: *const u32,
3606 offsets: *const u32,
3607 modifier: *const u64,
3608 buf_id: *mut u32,
3609 flags: u32,
3610 ) -> ::core::ffi::c_int;
3611}
3612unsafe extern "C" {
3613 pub fn drmModeRmFB(fd: ::core::ffi::c_int, bufferId: u32) -> ::core::ffi::c_int;
3614}
3615unsafe extern "C" {
3616 pub fn drmModeCloseFB(fd: ::core::ffi::c_int, buffer_id: u32) -> ::core::ffi::c_int;
3617}
3618unsafe extern "C" {
3619 pub fn drmModeDirtyFB(
3620 fd: ::core::ffi::c_int,
3621 bufferId: u32,
3622 clips: drmModeClipPtr,
3623 num_clips: u32,
3624 ) -> ::core::ffi::c_int;
3625}
3626unsafe extern "C" {
3627 pub fn drmModeGetCrtc(fd: ::core::ffi::c_int, crtcId: u32) -> drmModeCrtcPtr;
3628}
3629unsafe extern "C" {
3630 pub fn drmModeSetCrtc(
3631 fd: ::core::ffi::c_int,
3632 crtcId: u32,
3633 bufferId: u32,
3634 x: u32,
3635 y: u32,
3636 connectors: *mut u32,
3637 count: ::core::ffi::c_int,
3638 mode: drmModeModeInfoPtr,
3639 ) -> ::core::ffi::c_int;
3640}
3641unsafe extern "C" {
3642 pub fn drmModeSetCursor(
3643 fd: ::core::ffi::c_int,
3644 crtcId: u32,
3645 bo_handle: u32,
3646 width: u32,
3647 height: u32,
3648 ) -> ::core::ffi::c_int;
3649}
3650unsafe extern "C" {
3651 pub fn drmModeSetCursor2(
3652 fd: ::core::ffi::c_int,
3653 crtcId: u32,
3654 bo_handle: u32,
3655 width: u32,
3656 height: u32,
3657 hot_x: i32,
3658 hot_y: i32,
3659 ) -> ::core::ffi::c_int;
3660}
3661unsafe extern "C" {
3662 pub fn drmModeMoveCursor(
3663 fd: ::core::ffi::c_int,
3664 crtcId: u32,
3665 x: ::core::ffi::c_int,
3666 y: ::core::ffi::c_int,
3667 ) -> ::core::ffi::c_int;
3668}
3669unsafe extern "C" {
3670 pub fn drmModeGetEncoder(fd: ::core::ffi::c_int, encoder_id: u32) -> drmModeEncoderPtr;
3671}
3672unsafe extern "C" {
3673 pub fn drmModeGetConnector(fd: ::core::ffi::c_int, connectorId: u32) -> drmModeConnectorPtr;
3674}
3675unsafe extern "C" {
3676 pub fn drmModeGetConnectorCurrent(
3677 fd: ::core::ffi::c_int,
3678 connector_id: u32,
3679 ) -> drmModeConnectorPtr;
3680}
3681unsafe extern "C" {
3682 pub fn drmModeConnectorGetPossibleCrtcs(
3683 fd: ::core::ffi::c_int,
3684 connector: *const drmModeConnector,
3685 ) -> u32;
3686}
3687unsafe extern "C" {
3688 pub fn drmModeAttachMode(
3689 fd: ::core::ffi::c_int,
3690 connectorId: u32,
3691 mode_info: drmModeModeInfoPtr,
3692 ) -> ::core::ffi::c_int;
3693}
3694unsafe extern "C" {
3695 pub fn drmModeDetachMode(
3696 fd: ::core::ffi::c_int,
3697 connectorId: u32,
3698 mode_info: drmModeModeInfoPtr,
3699 ) -> ::core::ffi::c_int;
3700}
3701unsafe extern "C" {
3702 pub fn drmModeGetProperty(fd: ::core::ffi::c_int, propertyId: u32) -> drmModePropertyPtr;
3703}
3704unsafe extern "C" {
3705 pub fn drmModeFreeProperty(ptr: drmModePropertyPtr);
3706}
3707unsafe extern "C" {
3708 pub fn drmModeGetPropertyBlob(fd: ::core::ffi::c_int, blob_id: u32) -> drmModePropertyBlobPtr;
3709}
3710unsafe extern "C" {
3711 pub fn drmModeFormatModifierBlobIterNext(
3712 blob: *const drmModePropertyBlobRes,
3713 iter: *mut drmModeFormatModifierIterator,
3714 ) -> bool;
3715}
3716unsafe extern "C" {
3717 pub fn drmModeFreePropertyBlob(ptr: drmModePropertyBlobPtr);
3718}
3719unsafe extern "C" {
3720 pub fn drmModeConnectorSetProperty(
3721 fd: ::core::ffi::c_int,
3722 connector_id: u32,
3723 property_id: u32,
3724 value: u64,
3725 ) -> ::core::ffi::c_int;
3726}
3727unsafe extern "C" {
3728 pub fn drmCheckModesettingSupported(busid: *const ::core::ffi::c_char) -> ::core::ffi::c_int;
3729}
3730unsafe extern "C" {
3731 pub fn drmModeCrtcSetGamma(
3732 fd: ::core::ffi::c_int,
3733 crtc_id: u32,
3734 size: u32,
3735 red: *const u16,
3736 green: *const u16,
3737 blue: *const u16,
3738 ) -> ::core::ffi::c_int;
3739}
3740unsafe extern "C" {
3741 pub fn drmModeCrtcGetGamma(
3742 fd: ::core::ffi::c_int,
3743 crtc_id: u32,
3744 size: u32,
3745 red: *mut u16,
3746 green: *mut u16,
3747 blue: *mut u16,
3748 ) -> ::core::ffi::c_int;
3749}
3750unsafe extern "C" {
3751 pub fn drmModePageFlip(
3752 fd: ::core::ffi::c_int,
3753 crtc_id: u32,
3754 fb_id: u32,
3755 flags: u32,
3756 user_data: *mut ::core::ffi::c_void,
3757 ) -> ::core::ffi::c_int;
3758}
3759unsafe extern "C" {
3760 pub fn drmModePageFlipTarget(
3761 fd: ::core::ffi::c_int,
3762 crtc_id: u32,
3763 fb_id: u32,
3764 flags: u32,
3765 user_data: *mut ::core::ffi::c_void,
3766 target_vblank: u32,
3767 ) -> ::core::ffi::c_int;
3768}
3769unsafe extern "C" {
3770 pub fn drmModeGetPlaneResources(fd: ::core::ffi::c_int) -> drmModePlaneResPtr;
3771}
3772unsafe extern "C" {
3773 pub fn drmModeGetPlane(fd: ::core::ffi::c_int, plane_id: u32) -> drmModePlanePtr;
3774}
3775unsafe extern "C" {
3776 pub fn drmModeSetPlane(
3777 fd: ::core::ffi::c_int,
3778 plane_id: u32,
3779 crtc_id: u32,
3780 fb_id: u32,
3781 flags: u32,
3782 crtc_x: i32,
3783 crtc_y: i32,
3784 crtc_w: u32,
3785 crtc_h: u32,
3786 src_x: u32,
3787 src_y: u32,
3788 src_w: u32,
3789 src_h: u32,
3790 ) -> ::core::ffi::c_int;
3791}
3792unsafe extern "C" {
3793 pub fn drmModeObjectGetProperties(
3794 fd: ::core::ffi::c_int,
3795 object_id: u32,
3796 object_type: u32,
3797 ) -> drmModeObjectPropertiesPtr;
3798}
3799unsafe extern "C" {
3800 pub fn drmModeFreeObjectProperties(ptr: drmModeObjectPropertiesPtr);
3801}
3802unsafe extern "C" {
3803 pub fn drmModeObjectSetProperty(
3804 fd: ::core::ffi::c_int,
3805 object_id: u32,
3806 object_type: u32,
3807 property_id: u32,
3808 value: u64,
3809 ) -> ::core::ffi::c_int;
3810}
3811#[repr(C)]
3812#[derive(Debug, Copy, Clone)]
3813pub struct _drmModeAtomicReq {
3814 _unused: [u8; 0],
3815}
3816pub type drmModeAtomicReq = _drmModeAtomicReq;
3817pub type drmModeAtomicReqPtr = *mut _drmModeAtomicReq;
3818unsafe extern "C" {
3819 pub fn drmModeAtomicAlloc() -> drmModeAtomicReqPtr;
3820}
3821unsafe extern "C" {
3822 pub fn drmModeAtomicDuplicate(req: drmModeAtomicReqPtr) -> drmModeAtomicReqPtr;
3823}
3824unsafe extern "C" {
3825 pub fn drmModeAtomicMerge(
3826 base: drmModeAtomicReqPtr,
3827 augment: drmModeAtomicReqPtr,
3828 ) -> ::core::ffi::c_int;
3829}
3830unsafe extern "C" {
3831 pub fn drmModeAtomicFree(req: drmModeAtomicReqPtr);
3832}
3833unsafe extern "C" {
3834 pub fn drmModeAtomicGetCursor(req: drmModeAtomicReqPtr) -> ::core::ffi::c_int;
3835}
3836unsafe extern "C" {
3837 pub fn drmModeAtomicSetCursor(req: drmModeAtomicReqPtr, cursor: ::core::ffi::c_int);
3838}
3839unsafe extern "C" {
3840 pub fn drmModeAtomicAddProperty(
3841 req: drmModeAtomicReqPtr,
3842 object_id: u32,
3843 property_id: u32,
3844 value: u64,
3845 ) -> ::core::ffi::c_int;
3846}
3847unsafe extern "C" {
3848 pub fn drmModeAtomicCommit(
3849 fd: ::core::ffi::c_int,
3850 req: drmModeAtomicReqPtr,
3851 flags: u32,
3852 user_data: *mut ::core::ffi::c_void,
3853 ) -> ::core::ffi::c_int;
3854}
3855unsafe extern "C" {
3856 pub fn drmModeCreatePropertyBlob(
3857 fd: ::core::ffi::c_int,
3858 data: *const ::core::ffi::c_void,
3859 size: usize,
3860 id: *mut u32,
3861 ) -> ::core::ffi::c_int;
3862}
3863unsafe extern "C" {
3864 pub fn drmModeDestroyPropertyBlob(fd: ::core::ffi::c_int, id: u32) -> ::core::ffi::c_int;
3865}
3866unsafe extern "C" {
3867 pub fn drmModeCreateLease(
3868 fd: ::core::ffi::c_int,
3869 objects: *const u32,
3870 num_objects: ::core::ffi::c_int,
3871 flags: ::core::ffi::c_int,
3872 lessee_id: *mut u32,
3873 ) -> ::core::ffi::c_int;
3874}
3875#[repr(C)]
3876#[derive(Debug)]
3877pub struct drmModeLesseeList {
3878 pub count: u32,
3879 pub lessees: __IncompleteArrayField<u32>,
3880}
3881pub type drmModeLesseeListRes = drmModeLesseeList;
3882pub type drmModeLesseeListPtr = *mut drmModeLesseeList;
3883unsafe extern "C" {
3884 pub fn drmModeListLessees(fd: ::core::ffi::c_int) -> drmModeLesseeListPtr;
3885}
3886#[repr(C)]
3887#[derive(Debug)]
3888pub struct drmModeObjectList {
3889 pub count: u32,
3890 pub objects: __IncompleteArrayField<u32>,
3891}
3892pub type drmModeObjectListRes = drmModeObjectList;
3893pub type drmModeObjectListPtr = *mut drmModeObjectList;
3894unsafe extern "C" {
3895 pub fn drmModeGetLease(fd: ::core::ffi::c_int) -> drmModeObjectListPtr;
3896}
3897unsafe extern "C" {
3898 pub fn drmModeRevokeLease(fd: ::core::ffi::c_int, lessee_id: u32) -> ::core::ffi::c_int;
3899}
3900unsafe extern "C" {
3901 pub fn drmModeGetConnectorTypeName(connector_type: u32) -> *const ::core::ffi::c_char;
3902}
3903unsafe extern "C" {
3904 pub fn drmModeCreateDumbBuffer(
3905 fd: ::core::ffi::c_int,
3906 width: u32,
3907 height: u32,
3908 bpp: u32,
3909 flags: u32,
3910 handle: *mut u32,
3911 pitch: *mut u32,
3912 size: *mut u64,
3913 ) -> ::core::ffi::c_int;
3914}
3915unsafe extern "C" {
3916 pub fn drmModeDestroyDumbBuffer(fd: ::core::ffi::c_int, handle: u32) -> ::core::ffi::c_int;
3917}
3918unsafe extern "C" {
3919 pub fn drmModeMapDumbBuffer(
3920 fd: ::core::ffi::c_int,
3921 handle: u32,
3922 offset: *mut u64,
3923 ) -> ::core::ffi::c_int;
3924}
3925pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_gem_flink_name: amdgpu_bo_handle_type = 0;
3926pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_kms: amdgpu_bo_handle_type = 1;
3927pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_dma_buf_fd: amdgpu_bo_handle_type = 2;
3928pub const amdgpu_bo_handle_type_amdgpu_bo_handle_type_kms_noimport: amdgpu_bo_handle_type = 3;
3929pub type amdgpu_bo_handle_type = ::core::ffi::c_uint;
3930pub const amdgpu_gpu_va_range_amdgpu_gpu_va_range_general: amdgpu_gpu_va_range = 0;
3931pub type amdgpu_gpu_va_range = ::core::ffi::c_uint;
3932pub const amdgpu_sw_info_amdgpu_sw_info_address32_hi: amdgpu_sw_info = 0;
3933pub type amdgpu_sw_info = ::core::ffi::c_uint;
3934#[repr(C)]
3935#[derive(Debug, Copy, Clone)]
3936pub struct amdgpu_device {
3937 _unused: [u8; 0],
3938}
3939pub type amdgpu_device_handle = *mut amdgpu_device;
3940#[repr(C)]
3941#[derive(Debug, Copy, Clone)]
3942pub struct amdgpu_context {
3943 _unused: [u8; 0],
3944}
3945pub type amdgpu_context_handle = *mut amdgpu_context;
3946#[repr(C)]
3947#[derive(Debug, Copy, Clone)]
3948pub struct amdgpu_bo {
3949 _unused: [u8; 0],
3950}
3951pub type amdgpu_bo_handle = *mut amdgpu_bo;
3952#[repr(C)]
3953#[derive(Debug, Copy, Clone)]
3954pub struct amdgpu_bo_list {
3955 _unused: [u8; 0],
3956}
3957pub type amdgpu_bo_list_handle = *mut amdgpu_bo_list;
3958#[repr(C)]
3959#[derive(Debug, Copy, Clone)]
3960pub struct amdgpu_va {
3961 _unused: [u8; 0],
3962}
3963pub type amdgpu_va_handle = *mut amdgpu_va;
3964#[repr(C)]
3965#[derive(Debug, Copy, Clone)]
3966pub struct amdgpu_va_manager {
3967 _unused: [u8; 0],
3968}
3969pub type amdgpu_va_manager_handle = *mut amdgpu_va_manager;
3970#[repr(C)]
3971#[derive(Debug, Copy, Clone)]
3972pub struct amdgpu_semaphore {
3973 _unused: [u8; 0],
3974}
3975pub type amdgpu_semaphore_handle = *mut amdgpu_semaphore;
3976#[repr(C)]
3977#[derive(Debug, Copy, Clone)]
3978pub struct amdgpu_bo_alloc_request {
3979 pub alloc_size: u64,
3980 pub phys_alignment: u64,
3981 pub preferred_heap: u32,
3982 pub flags: u64,
3983}
3984#[repr(C)]
3985#[derive(Debug, Copy, Clone)]
3986pub struct amdgpu_bo_metadata {
3987 pub flags: u64,
3988 pub tiling_info: u64,
3989 pub size_metadata: u32,
3990 pub umd_metadata: [u32; 64usize],
3991}
3992#[repr(C)]
3993#[derive(Debug, Copy, Clone)]
3994pub struct amdgpu_bo_info {
3995 pub alloc_size: u64,
3996 pub phys_alignment: u64,
3997 pub preferred_heap: u32,
3998 pub alloc_flags: u64,
3999 pub metadata: amdgpu_bo_metadata,
4000}
4001#[repr(C)]
4002#[derive(Debug, Copy, Clone)]
4003pub struct amdgpu_bo_import_result {
4004 pub buf_handle: amdgpu_bo_handle,
4005 pub alloc_size: u64,
4006}
4007#[repr(C)]
4008#[derive(Debug, Copy, Clone)]
4009pub struct amdgpu_gds_resource_info {
4010 pub gds_gfx_partition_size: u32,
4011 pub compute_partition_size: u32,
4012 pub gds_total_size: u32,
4013 pub gws_per_gfx_partition: u32,
4014 pub gws_per_compute_partition: u32,
4015 pub oa_per_gfx_partition: u32,
4016 pub oa_per_compute_partition: u32,
4017}
4018#[repr(C)]
4019#[derive(Debug, Copy, Clone)]
4020pub struct amdgpu_cs_fence {
4021 pub context: amdgpu_context_handle,
4022 pub ip_type: u32,
4023 pub ip_instance: u32,
4024 pub ring: u32,
4025 pub fence: u64,
4026}
4027#[repr(C)]
4028#[derive(Debug, Copy, Clone)]
4029pub struct amdgpu_cs_ib_info {
4030 pub flags: u64,
4031 pub ib_mc_address: u64,
4032 pub size: u32,
4033}
4034#[repr(C)]
4035#[derive(Debug, Copy, Clone)]
4036pub struct amdgpu_cs_fence_info {
4037 pub handle: amdgpu_bo_handle,
4038 pub offset: u64,
4039}
4040#[repr(C)]
4041#[derive(Debug, Copy, Clone)]
4042pub struct amdgpu_cs_request {
4043 pub flags: u64,
4044 pub ip_type: ::core::ffi::c_uint,
4045 pub ip_instance: ::core::ffi::c_uint,
4046 pub ring: u32,
4047 pub resources: amdgpu_bo_list_handle,
4048 pub number_of_dependencies: u32,
4049 pub dependencies: *mut amdgpu_cs_fence,
4050 pub number_of_ibs: u32,
4051 pub ibs: *mut amdgpu_cs_ib_info,
4052 pub seq_no: u64,
4053 pub fence_info: amdgpu_cs_fence_info,
4054}
4055#[repr(C)]
4056#[derive(Debug, Copy, Clone)]
4057pub struct amdgpu_buffer_size_alignments {
4058 pub size_local: u64,
4059 pub size_remote: u64,
4060}
4061#[repr(C)]
4062#[derive(Debug, Copy, Clone)]
4063pub struct amdgpu_heap_info {
4064 pub heap_size: u64,
4065 pub heap_usage: u64,
4066 pub max_allocation: u64,
4067}
4068#[repr(C)]
4069#[derive(Debug, Copy, Clone)]
4070pub struct amdgpu_gpu_info {
4071 pub asic_id: u32,
4072 pub chip_rev: u32,
4073 pub chip_external_rev: u32,
4074 pub family_id: u32,
4075 pub ids_flags: u64,
4076 pub max_engine_clk: u64,
4077 pub max_memory_clk: u64,
4078 pub num_shader_engines: u32,
4079 pub num_shader_arrays_per_engine: u32,
4080 pub avail_quad_shader_pipes: u32,
4081 pub max_quad_shader_pipes: u32,
4082 pub cache_entries_per_quad_pipe: u32,
4083 pub num_hw_gfx_contexts: u32,
4084 pub rb_pipes: u32,
4085 pub enabled_rb_pipes_mask: u32,
4086 pub gpu_counter_freq: u32,
4087 pub backend_disable: [u32; 4usize],
4088 pub mc_arb_ramcfg: u32,
4089 pub gb_addr_cfg: u32,
4090 pub gb_tile_mode: [u32; 32usize],
4091 pub gb_macro_tile_mode: [u32; 16usize],
4092 pub pa_sc_raster_cfg: [u32; 4usize],
4093 pub pa_sc_raster_cfg1: [u32; 4usize],
4094 pub cu_active_number: u32,
4095 pub cu_ao_mask: u32,
4096 pub cu_bitmap: [[u32; 4usize]; 4usize],
4097 pub vram_type: u32,
4098 pub vram_bit_width: u32,
4099 pub ce_ram_size: u32,
4100 pub vce_harvest_config: u32,
4101 pub pci_rev_id: u32,
4102}
4103unsafe extern "C" {
4104 pub fn amdgpu_device_initialize(
4105 fd: ::core::ffi::c_int,
4106 major_version: *mut u32,
4107 minor_version: *mut u32,
4108 device_handle: *mut amdgpu_device_handle,
4109 ) -> ::core::ffi::c_int;
4110}
4111unsafe extern "C" {
4112 pub fn amdgpu_device_initialize2(
4113 fd: ::core::ffi::c_int,
4114 deduplicate_device: bool,
4115 major_version: *mut u32,
4116 minor_version: *mut u32,
4117 device_handle: *mut amdgpu_device_handle,
4118 ) -> ::core::ffi::c_int;
4119}
4120unsafe extern "C" {
4121 pub fn amdgpu_device_deinitialize(device_handle: amdgpu_device_handle) -> ::core::ffi::c_int;
4122}
4123unsafe extern "C" {
4124 pub fn amdgpu_bo_alloc(
4125 dev: amdgpu_device_handle,
4126 alloc_buffer: *mut amdgpu_bo_alloc_request,
4127 buf_handle: *mut amdgpu_bo_handle,
4128 ) -> ::core::ffi::c_int;
4129}
4130unsafe extern "C" {
4131 pub fn amdgpu_bo_set_metadata(
4132 buf_handle: amdgpu_bo_handle,
4133 info: *mut amdgpu_bo_metadata,
4134 ) -> ::core::ffi::c_int;
4135}
4136unsafe extern "C" {
4137 pub fn amdgpu_bo_query_info(
4138 buf_handle: amdgpu_bo_handle,
4139 info: *mut amdgpu_bo_info,
4140 ) -> ::core::ffi::c_int;
4141}
4142unsafe extern "C" {
4143 pub fn amdgpu_bo_export(
4144 buf_handle: amdgpu_bo_handle,
4145 type_: amdgpu_bo_handle_type,
4146 shared_handle: *mut u32,
4147 ) -> ::core::ffi::c_int;
4148}
4149unsafe extern "C" {
4150 pub fn amdgpu_bo_import(
4151 dev: amdgpu_device_handle,
4152 type_: amdgpu_bo_handle_type,
4153 shared_handle: u32,
4154 output: *mut amdgpu_bo_import_result,
4155 ) -> ::core::ffi::c_int;
4156}
4157unsafe extern "C" {
4158 pub fn amdgpu_create_bo_from_user_mem(
4159 dev: amdgpu_device_handle,
4160 cpu: *mut ::core::ffi::c_void,
4161 size: u64,
4162 buf_handle: *mut amdgpu_bo_handle,
4163 ) -> ::core::ffi::c_int;
4164}
4165unsafe extern "C" {
4166 pub fn amdgpu_find_bo_by_cpu_mapping(
4167 dev: amdgpu_device_handle,
4168 cpu: *mut ::core::ffi::c_void,
4169 size: u64,
4170 buf_handle: *mut amdgpu_bo_handle,
4171 offset_in_bo: *mut u64,
4172 ) -> ::core::ffi::c_int;
4173}
4174unsafe extern "C" {
4175 pub fn amdgpu_bo_free(buf_handle: amdgpu_bo_handle) -> ::core::ffi::c_int;
4176}
4177unsafe extern "C" {
4178 pub fn amdgpu_bo_inc_ref(bo: amdgpu_bo_handle);
4179}
4180unsafe extern "C" {
4181 pub fn amdgpu_bo_cpu_map(
4182 buf_handle: amdgpu_bo_handle,
4183 cpu: *mut *mut ::core::ffi::c_void,
4184 ) -> ::core::ffi::c_int;
4185}
4186unsafe extern "C" {
4187 pub fn amdgpu_bo_cpu_unmap(buf_handle: amdgpu_bo_handle) -> ::core::ffi::c_int;
4188}
4189unsafe extern "C" {
4190 pub fn amdgpu_bo_wait_for_idle(
4191 buf_handle: amdgpu_bo_handle,
4192 timeout_ns: u64,
4193 buffer_busy: *mut bool,
4194 ) -> ::core::ffi::c_int;
4195}
4196unsafe extern "C" {
4197 pub fn amdgpu_bo_list_create_raw(
4198 dev: amdgpu_device_handle,
4199 number_of_buffers: u32,
4200 buffers: *mut drm_amdgpu_bo_list_entry,
4201 result: *mut u32,
4202 ) -> ::core::ffi::c_int;
4203}
4204unsafe extern "C" {
4205 pub fn amdgpu_bo_list_destroy_raw(
4206 dev: amdgpu_device_handle,
4207 bo_list: u32,
4208 ) -> ::core::ffi::c_int;
4209}
4210unsafe extern "C" {
4211 pub fn amdgpu_bo_list_create(
4212 dev: amdgpu_device_handle,
4213 number_of_resources: u32,
4214 resources: *mut amdgpu_bo_handle,
4215 resource_prios: *mut u8,
4216 result: *mut amdgpu_bo_list_handle,
4217 ) -> ::core::ffi::c_int;
4218}
4219unsafe extern "C" {
4220 pub fn amdgpu_bo_list_destroy(handle: amdgpu_bo_list_handle) -> ::core::ffi::c_int;
4221}
4222unsafe extern "C" {
4223 pub fn amdgpu_bo_list_update(
4224 handle: amdgpu_bo_list_handle,
4225 number_of_resources: u32,
4226 resources: *mut amdgpu_bo_handle,
4227 resource_prios: *mut u8,
4228 ) -> ::core::ffi::c_int;
4229}
4230unsafe extern "C" {
4231 pub fn amdgpu_cs_ctx_create2(
4232 dev: amdgpu_device_handle,
4233 priority: u32,
4234 context: *mut amdgpu_context_handle,
4235 ) -> ::core::ffi::c_int;
4236}
4237unsafe extern "C" {
4238 pub fn amdgpu_cs_ctx_create(
4239 dev: amdgpu_device_handle,
4240 context: *mut amdgpu_context_handle,
4241 ) -> ::core::ffi::c_int;
4242}
4243unsafe extern "C" {
4244 pub fn amdgpu_cs_ctx_free(context: amdgpu_context_handle) -> ::core::ffi::c_int;
4245}
4246unsafe extern "C" {
4247 pub fn amdgpu_cs_ctx_override_priority(
4248 dev: amdgpu_device_handle,
4249 context: amdgpu_context_handle,
4250 master_fd: ::core::ffi::c_int,
4251 priority: ::core::ffi::c_uint,
4252 ) -> ::core::ffi::c_int;
4253}
4254unsafe extern "C" {
4255 pub fn amdgpu_cs_ctx_stable_pstate(
4256 context: amdgpu_context_handle,
4257 op: u32,
4258 flags: u32,
4259 out_flags: *mut u32,
4260 ) -> ::core::ffi::c_int;
4261}
4262unsafe extern "C" {
4263 pub fn amdgpu_cs_query_reset_state(
4264 context: amdgpu_context_handle,
4265 state: *mut u32,
4266 hangs: *mut u32,
4267 ) -> ::core::ffi::c_int;
4268}
4269unsafe extern "C" {
4270 pub fn amdgpu_cs_query_reset_state2(
4271 context: amdgpu_context_handle,
4272 flags: *mut u64,
4273 ) -> ::core::ffi::c_int;
4274}
4275unsafe extern "C" {
4276 pub fn amdgpu_cs_submit(
4277 context: amdgpu_context_handle,
4278 flags: u64,
4279 ibs_request: *mut amdgpu_cs_request,
4280 number_of_requests: u32,
4281 ) -> ::core::ffi::c_int;
4282}
4283unsafe extern "C" {
4284 pub fn amdgpu_cs_query_fence_status(
4285 fence: *mut amdgpu_cs_fence,
4286 timeout_ns: u64,
4287 flags: u64,
4288 expired: *mut u32,
4289 ) -> ::core::ffi::c_int;
4290}
4291unsafe extern "C" {
4292 pub fn amdgpu_cs_wait_fences(
4293 fences: *mut amdgpu_cs_fence,
4294 fence_count: u32,
4295 wait_all: bool,
4296 timeout_ns: u64,
4297 status: *mut u32,
4298 first: *mut u32,
4299 ) -> ::core::ffi::c_int;
4300}
4301unsafe extern "C" {
4302 pub fn amdgpu_query_buffer_size_alignment(
4303 dev: amdgpu_device_handle,
4304 info: *mut amdgpu_buffer_size_alignments,
4305 ) -> ::core::ffi::c_int;
4306}
4307unsafe extern "C" {
4308 pub fn amdgpu_query_firmware_version(
4309 dev: amdgpu_device_handle,
4310 fw_type: ::core::ffi::c_uint,
4311 ip_instance: ::core::ffi::c_uint,
4312 index: ::core::ffi::c_uint,
4313 version: *mut u32,
4314 feature: *mut u32,
4315 ) -> ::core::ffi::c_int;
4316}
4317unsafe extern "C" {
4318 pub fn amdgpu_query_hw_ip_count(
4319 dev: amdgpu_device_handle,
4320 type_: ::core::ffi::c_uint,
4321 count: *mut u32,
4322 ) -> ::core::ffi::c_int;
4323}
4324unsafe extern "C" {
4325 pub fn amdgpu_query_hw_ip_info(
4326 dev: amdgpu_device_handle,
4327 type_: ::core::ffi::c_uint,
4328 ip_instance: ::core::ffi::c_uint,
4329 info: *mut drm_amdgpu_info_hw_ip,
4330 ) -> ::core::ffi::c_int;
4331}
4332unsafe extern "C" {
4333 pub fn amdgpu_query_heap_info(
4334 dev: amdgpu_device_handle,
4335 heap: u32,
4336 flags: u32,
4337 info: *mut amdgpu_heap_info,
4338 ) -> ::core::ffi::c_int;
4339}
4340unsafe extern "C" {
4341 pub fn amdgpu_query_crtc_from_id(
4342 dev: amdgpu_device_handle,
4343 id: ::core::ffi::c_uint,
4344 result: *mut i32,
4345 ) -> ::core::ffi::c_int;
4346}
4347unsafe extern "C" {
4348 pub fn amdgpu_query_gpu_info(
4349 dev: amdgpu_device_handle,
4350 info: *mut amdgpu_gpu_info,
4351 ) -> ::core::ffi::c_int;
4352}
4353unsafe extern "C" {
4354 pub fn amdgpu_query_info(
4355 dev: amdgpu_device_handle,
4356 info_id: ::core::ffi::c_uint,
4357 size: ::core::ffi::c_uint,
4358 value: *mut ::core::ffi::c_void,
4359 ) -> ::core::ffi::c_int;
4360}
4361unsafe extern "C" {
4362 pub fn amdgpu_query_sw_info(
4363 dev: amdgpu_device_handle,
4364 info: amdgpu_sw_info,
4365 value: *mut ::core::ffi::c_void,
4366 ) -> ::core::ffi::c_int;
4367}
4368unsafe extern "C" {
4369 pub fn amdgpu_query_gds_info(
4370 dev: amdgpu_device_handle,
4371 gds_info: *mut amdgpu_gds_resource_info,
4372 ) -> ::core::ffi::c_int;
4373}
4374unsafe extern "C" {
4375 pub fn amdgpu_query_sensor_info(
4376 dev: amdgpu_device_handle,
4377 sensor_type: ::core::ffi::c_uint,
4378 size: ::core::ffi::c_uint,
4379 value: *mut ::core::ffi::c_void,
4380 ) -> ::core::ffi::c_int;
4381}
4382unsafe extern "C" {
4383 pub fn amdgpu_query_video_caps_info(
4384 dev: amdgpu_device_handle,
4385 cap_type: ::core::ffi::c_uint,
4386 size: ::core::ffi::c_uint,
4387 value: *mut ::core::ffi::c_void,
4388 ) -> ::core::ffi::c_int;
4389}
4390unsafe extern "C" {
4391 pub fn amdgpu_query_gpuvm_fault_info(
4392 dev: amdgpu_device_handle,
4393 size: ::core::ffi::c_uint,
4394 value: *mut ::core::ffi::c_void,
4395 ) -> ::core::ffi::c_int;
4396}
4397unsafe extern "C" {
4398 pub fn amdgpu_read_mm_registers(
4399 dev: amdgpu_device_handle,
4400 dword_offset: ::core::ffi::c_uint,
4401 count: ::core::ffi::c_uint,
4402 instance: u32,
4403 flags: u32,
4404 values: *mut u32,
4405 ) -> ::core::ffi::c_int;
4406}
4407unsafe extern "C" {
4408 pub fn amdgpu_va_range_alloc(
4409 dev: amdgpu_device_handle,
4410 va_range_type: amdgpu_gpu_va_range,
4411 size: u64,
4412 va_base_alignment: u64,
4413 va_base_required: u64,
4414 va_base_allocated: *mut u64,
4415 va_range_handle: *mut amdgpu_va_handle,
4416 flags: u64,
4417 ) -> ::core::ffi::c_int;
4418}
4419unsafe extern "C" {
4420 pub fn amdgpu_va_range_free(va_range_handle: amdgpu_va_handle) -> ::core::ffi::c_int;
4421}
4422unsafe extern "C" {
4423 pub fn amdgpu_va_get_start_addr(va_handle: amdgpu_va_handle) -> u64;
4424}
4425unsafe extern "C" {
4426 pub fn amdgpu_va_range_query(
4427 dev: amdgpu_device_handle,
4428 type_: amdgpu_gpu_va_range,
4429 start: *mut u64,
4430 end: *mut u64,
4431 ) -> ::core::ffi::c_int;
4432}
4433unsafe extern "C" {
4434 pub fn amdgpu_va_manager_alloc() -> amdgpu_va_manager_handle;
4435}
4436unsafe extern "C" {
4437 pub fn amdgpu_va_manager_init(
4438 va_mgr: amdgpu_va_manager_handle,
4439 low_va_offset: u64,
4440 low_va_max: u64,
4441 high_va_offset: u64,
4442 high_va_max: u64,
4443 virtual_address_alignment: u32,
4444 );
4445}
4446unsafe extern "C" {
4447 pub fn amdgpu_va_manager_deinit(va_mgr: amdgpu_va_manager_handle);
4448}
4449unsafe extern "C" {
4450 pub fn amdgpu_va_range_alloc2(
4451 va_mgr: amdgpu_va_manager_handle,
4452 va_range_type: amdgpu_gpu_va_range,
4453 size: u64,
4454 va_base_alignment: u64,
4455 va_base_required: u64,
4456 va_base_allocated: *mut u64,
4457 va_range_handle: *mut amdgpu_va_handle,
4458 flags: u64,
4459 ) -> ::core::ffi::c_int;
4460}
4461unsafe extern "C" {
4462 pub fn amdgpu_bo_va_op(
4463 bo: amdgpu_bo_handle,
4464 offset: u64,
4465 size: u64,
4466 addr: u64,
4467 flags: u64,
4468 ops: u32,
4469 ) -> ::core::ffi::c_int;
4470}
4471unsafe extern "C" {
4472 pub fn amdgpu_bo_va_op_raw(
4473 dev: amdgpu_device_handle,
4474 bo: amdgpu_bo_handle,
4475 offset: u64,
4476 size: u64,
4477 addr: u64,
4478 flags: u64,
4479 ops: u32,
4480 ) -> ::core::ffi::c_int;
4481}
4482unsafe extern "C" {
4483 pub fn amdgpu_cs_create_semaphore(sem: *mut amdgpu_semaphore_handle) -> ::core::ffi::c_int;
4484}
4485unsafe extern "C" {
4486 pub fn amdgpu_cs_signal_semaphore(
4487 ctx: amdgpu_context_handle,
4488 ip_type: u32,
4489 ip_instance: u32,
4490 ring: u32,
4491 sem: amdgpu_semaphore_handle,
4492 ) -> ::core::ffi::c_int;
4493}
4494unsafe extern "C" {
4495 pub fn amdgpu_cs_wait_semaphore(
4496 ctx: amdgpu_context_handle,
4497 ip_type: u32,
4498 ip_instance: u32,
4499 ring: u32,
4500 sem: amdgpu_semaphore_handle,
4501 ) -> ::core::ffi::c_int;
4502}
4503unsafe extern "C" {
4504 pub fn amdgpu_cs_destroy_semaphore(sem: amdgpu_semaphore_handle) -> ::core::ffi::c_int;
4505}
4506unsafe extern "C" {
4507 pub fn amdgpu_get_marketing_name(dev: amdgpu_device_handle) -> *const ::core::ffi::c_char;
4508}
4509unsafe extern "C" {
4510 pub fn amdgpu_cs_create_syncobj2(
4511 dev: amdgpu_device_handle,
4512 flags: u32,
4513 syncobj: *mut u32,
4514 ) -> ::core::ffi::c_int;
4515}
4516unsafe extern "C" {
4517 pub fn amdgpu_cs_create_syncobj(
4518 dev: amdgpu_device_handle,
4519 syncobj: *mut u32,
4520 ) -> ::core::ffi::c_int;
4521}
4522unsafe extern "C" {
4523 pub fn amdgpu_cs_destroy_syncobj(dev: amdgpu_device_handle, syncobj: u32)
4524 -> ::core::ffi::c_int;
4525}
4526unsafe extern "C" {
4527 pub fn amdgpu_cs_syncobj_reset(
4528 dev: amdgpu_device_handle,
4529 syncobjs: *const u32,
4530 syncobj_count: u32,
4531 ) -> ::core::ffi::c_int;
4532}
4533unsafe extern "C" {
4534 pub fn amdgpu_cs_syncobj_signal(
4535 dev: amdgpu_device_handle,
4536 syncobjs: *const u32,
4537 syncobj_count: u32,
4538 ) -> ::core::ffi::c_int;
4539}
4540unsafe extern "C" {
4541 pub fn amdgpu_cs_syncobj_timeline_signal(
4542 dev: amdgpu_device_handle,
4543 syncobjs: *const u32,
4544 points: *mut u64,
4545 syncobj_count: u32,
4546 ) -> ::core::ffi::c_int;
4547}
4548unsafe extern "C" {
4549 pub fn amdgpu_cs_syncobj_wait(
4550 dev: amdgpu_device_handle,
4551 handles: *mut u32,
4552 num_handles: ::core::ffi::c_uint,
4553 timeout_nsec: i64,
4554 flags: ::core::ffi::c_uint,
4555 first_signaled: *mut u32,
4556 ) -> ::core::ffi::c_int;
4557}
4558unsafe extern "C" {
4559 pub fn amdgpu_cs_syncobj_timeline_wait(
4560 dev: amdgpu_device_handle,
4561 handles: *mut u32,
4562 points: *mut u64,
4563 num_handles: ::core::ffi::c_uint,
4564 timeout_nsec: i64,
4565 flags: ::core::ffi::c_uint,
4566 first_signaled: *mut u32,
4567 ) -> ::core::ffi::c_int;
4568}
4569unsafe extern "C" {
4570 pub fn amdgpu_cs_syncobj_query(
4571 dev: amdgpu_device_handle,
4572 handles: *mut u32,
4573 points: *mut u64,
4574 num_handles: ::core::ffi::c_uint,
4575 ) -> ::core::ffi::c_int;
4576}
4577unsafe extern "C" {
4578 pub fn amdgpu_cs_syncobj_query2(
4579 dev: amdgpu_device_handle,
4580 handles: *mut u32,
4581 points: *mut u64,
4582 num_handles: ::core::ffi::c_uint,
4583 flags: u32,
4584 ) -> ::core::ffi::c_int;
4585}
4586unsafe extern "C" {
4587 pub fn amdgpu_cs_export_syncobj(
4588 dev: amdgpu_device_handle,
4589 syncobj: u32,
4590 shared_fd: *mut ::core::ffi::c_int,
4591 ) -> ::core::ffi::c_int;
4592}
4593unsafe extern "C" {
4594 pub fn amdgpu_cs_import_syncobj(
4595 dev: amdgpu_device_handle,
4596 shared_fd: ::core::ffi::c_int,
4597 syncobj: *mut u32,
4598 ) -> ::core::ffi::c_int;
4599}
4600unsafe extern "C" {
4601 pub fn amdgpu_cs_syncobj_export_sync_file(
4602 dev: amdgpu_device_handle,
4603 syncobj: u32,
4604 sync_file_fd: *mut ::core::ffi::c_int,
4605 ) -> ::core::ffi::c_int;
4606}
4607unsafe extern "C" {
4608 pub fn amdgpu_cs_syncobj_import_sync_file(
4609 dev: amdgpu_device_handle,
4610 syncobj: u32,
4611 sync_file_fd: ::core::ffi::c_int,
4612 ) -> ::core::ffi::c_int;
4613}
4614unsafe extern "C" {
4615 pub fn amdgpu_cs_syncobj_export_sync_file2(
4616 dev: amdgpu_device_handle,
4617 syncobj: u32,
4618 point: u64,
4619 flags: u32,
4620 sync_file_fd: *mut ::core::ffi::c_int,
4621 ) -> ::core::ffi::c_int;
4622}
4623unsafe extern "C" {
4624 pub fn amdgpu_cs_syncobj_import_sync_file2(
4625 dev: amdgpu_device_handle,
4626 syncobj: u32,
4627 point: u64,
4628 sync_file_fd: ::core::ffi::c_int,
4629 ) -> ::core::ffi::c_int;
4630}
4631unsafe extern "C" {
4632 pub fn amdgpu_cs_syncobj_transfer(
4633 dev: amdgpu_device_handle,
4634 dst_handle: u32,
4635 dst_point: u64,
4636 src_handle: u32,
4637 src_point: u64,
4638 flags: u32,
4639 ) -> ::core::ffi::c_int;
4640}
4641unsafe extern "C" {
4642 pub fn amdgpu_cs_fence_to_handle(
4643 dev: amdgpu_device_handle,
4644 fence: *mut amdgpu_cs_fence,
4645 what: u32,
4646 out_handle: *mut u32,
4647 ) -> ::core::ffi::c_int;
4648}
4649unsafe extern "C" {
4650 pub fn amdgpu_cs_submit_raw(
4651 dev: amdgpu_device_handle,
4652 context: amdgpu_context_handle,
4653 bo_list_handle: amdgpu_bo_list_handle,
4654 num_chunks: ::core::ffi::c_int,
4655 chunks: *mut drm_amdgpu_cs_chunk,
4656 seq_no: *mut u64,
4657 ) -> ::core::ffi::c_int;
4658}
4659unsafe extern "C" {
4660 pub fn amdgpu_cs_submit_raw2(
4661 dev: amdgpu_device_handle,
4662 context: amdgpu_context_handle,
4663 bo_list_handle: u32,
4664 num_chunks: ::core::ffi::c_int,
4665 chunks: *mut drm_amdgpu_cs_chunk,
4666 seq_no: *mut u64,
4667 ) -> ::core::ffi::c_int;
4668}
4669unsafe extern "C" {
4670 pub fn amdgpu_cs_chunk_fence_to_dep(
4671 fence: *mut amdgpu_cs_fence,
4672 dep: *mut drm_amdgpu_cs_chunk_dep,
4673 );
4674}
4675unsafe extern "C" {
4676 pub fn amdgpu_cs_chunk_fence_info_to_data(
4677 fence_info: *mut amdgpu_cs_fence_info,
4678 data: *mut drm_amdgpu_cs_chunk_data,
4679 );
4680}
4681unsafe extern "C" {
4682 pub fn amdgpu_vm_reserve_vmid(dev: amdgpu_device_handle, flags: u32) -> ::core::ffi::c_int;
4683}
4684unsafe extern "C" {
4685 pub fn amdgpu_vm_unreserve_vmid(dev: amdgpu_device_handle, flags: u32) -> ::core::ffi::c_int;
4686}
4687#[repr(C)]
4688#[derive(Debug, Copy, Clone)]
4689pub struct drm_amdgpu_gem_create_in {
4690 #[doc = " the requested memory size"]
4691 pub bo_size: __u64,
4692 #[doc = " physical start_addr alignment in bytes for some HW requirements"]
4693 pub alignment: __u64,
4694 #[doc = " the requested memory domains"]
4695 pub domains: __u64,
4696 #[doc = " allocation flags"]
4697 pub domain_flags: __u64,
4698}
4699#[repr(C)]
4700#[derive(Debug, Copy, Clone)]
4701pub struct drm_amdgpu_gem_create_out {
4702 #[doc = " returned GEM object handle"]
4703 pub handle: __u32,
4704 pub _pad: __u32,
4705}
4706#[repr(C)]
4707#[derive(Copy, Clone)]
4708pub union drm_amdgpu_gem_create {
4709 pub in_: drm_amdgpu_gem_create_in,
4710 pub out: drm_amdgpu_gem_create_out,
4711}
4712#[repr(C)]
4713#[derive(Debug, Copy, Clone)]
4714pub struct drm_amdgpu_bo_list_in {
4715 #[doc = " Type of operation"]
4716 pub operation: __u32,
4717 #[doc = " Handle of list or 0 if we want to create one"]
4718 pub list_handle: __u32,
4719 #[doc = " Number of BOs in list"]
4720 pub bo_number: __u32,
4721 #[doc = " Size of each element describing BO"]
4722 pub bo_info_size: __u32,
4723 #[doc = " Pointer to array describing BOs"]
4724 pub bo_info_ptr: __u64,
4725}
4726#[repr(C)]
4727#[derive(Debug, Copy, Clone)]
4728pub struct drm_amdgpu_bo_list_entry {
4729 #[doc = " Handle of BO"]
4730 pub bo_handle: __u32,
4731 #[doc = " New (if specified) BO priority to be used during migration"]
4732 pub bo_priority: __u32,
4733}
4734#[repr(C)]
4735#[derive(Debug, Copy, Clone)]
4736pub struct drm_amdgpu_bo_list_out {
4737 #[doc = " Handle of resource list"]
4738 pub list_handle: __u32,
4739 pub _pad: __u32,
4740}
4741#[repr(C)]
4742#[derive(Copy, Clone)]
4743pub union drm_amdgpu_bo_list {
4744 pub in_: drm_amdgpu_bo_list_in,
4745 pub out: drm_amdgpu_bo_list_out,
4746}
4747#[repr(C)]
4748#[derive(Debug, Copy, Clone)]
4749pub struct drm_amdgpu_ctx_in {
4750 #[doc = " AMDGPU_CTX_OP_*"]
4751 pub op: __u32,
4752 #[doc = " Flags"]
4753 pub flags: __u32,
4754 pub ctx_id: __u32,
4755 #[doc = " AMDGPU_CTX_PRIORITY_*"]
4756 pub priority: __s32,
4757}
4758#[repr(C)]
4759#[derive(Copy, Clone)]
4760pub union drm_amdgpu_ctx_out {
4761 pub alloc: drm_amdgpu_ctx_out__bindgen_ty_1,
4762 pub state: drm_amdgpu_ctx_out__bindgen_ty_2,
4763 pub pstate: drm_amdgpu_ctx_out__bindgen_ty_3,
4764}
4765#[repr(C)]
4766#[derive(Debug, Copy, Clone)]
4767pub struct drm_amdgpu_ctx_out__bindgen_ty_1 {
4768 pub ctx_id: __u32,
4769 pub _pad: __u32,
4770}
4771#[repr(C)]
4772#[derive(Debug, Copy, Clone)]
4773pub struct drm_amdgpu_ctx_out__bindgen_ty_2 {
4774 #[doc = " For future use, no flags defined so far"]
4775 pub flags: __u64,
4776 #[doc = " Number of resets caused by this context so far."]
4777 pub hangs: __u32,
4778 #[doc = " Reset status since the last call of the ioctl."]
4779 pub reset_status: __u32,
4780}
4781#[repr(C)]
4782#[derive(Debug, Copy, Clone)]
4783pub struct drm_amdgpu_ctx_out__bindgen_ty_3 {
4784 pub flags: __u32,
4785 pub _pad: __u32,
4786}
4787#[repr(C)]
4788#[derive(Copy, Clone)]
4789pub union drm_amdgpu_ctx {
4790 pub in_: drm_amdgpu_ctx_in,
4791 pub out: drm_amdgpu_ctx_out,
4792}
4793#[repr(C)]
4794#[derive(Debug, Copy, Clone)]
4795pub struct drm_amdgpu_vm_in {
4796 #[doc = " AMDGPU_VM_OP_*"]
4797 pub op: __u32,
4798 pub flags: __u32,
4799}
4800#[repr(C)]
4801#[derive(Debug, Copy, Clone)]
4802pub struct drm_amdgpu_vm_out {
4803 #[doc = " For future use, no flags defined so far"]
4804 pub flags: __u64,
4805}
4806#[repr(C)]
4807#[derive(Copy, Clone)]
4808pub union drm_amdgpu_vm {
4809 pub in_: drm_amdgpu_vm_in,
4810 pub out: drm_amdgpu_vm_out,
4811}
4812#[repr(C)]
4813#[derive(Debug, Copy, Clone)]
4814pub struct drm_amdgpu_sched_in {
4815 pub op: __u32,
4816 pub fd: __u32,
4817 #[doc = " AMDGPU_CTX_PRIORITY_*"]
4818 pub priority: __s32,
4819 pub ctx_id: __u32,
4820}
4821#[repr(C)]
4822#[derive(Copy, Clone)]
4823pub union drm_amdgpu_sched {
4824 pub in_: drm_amdgpu_sched_in,
4825}
4826#[repr(C)]
4827#[derive(Debug, Copy, Clone)]
4828pub struct drm_amdgpu_gem_userptr {
4829 pub addr: __u64,
4830 pub size: __u64,
4831 pub flags: __u32,
4832 pub handle: __u32,
4833}
4834#[doc = " The same structure is shared for input/output"]
4835#[repr(C)]
4836#[derive(Debug, Copy, Clone)]
4837pub struct drm_amdgpu_gem_metadata {
4838 #[doc = " GEM Object handle"]
4839 pub handle: __u32,
4840 #[doc = " Do we want get or set metadata"]
4841 pub op: __u32,
4842 pub data: drm_amdgpu_gem_metadata__bindgen_ty_1,
4843}
4844#[repr(C)]
4845#[derive(Debug, Copy, Clone)]
4846pub struct drm_amdgpu_gem_metadata__bindgen_ty_1 {
4847 #[doc = " For future use, no flags defined so far"]
4848 pub flags: __u64,
4849 #[doc = " family specific tiling info"]
4850 pub tiling_info: __u64,
4851 pub data_size_bytes: __u32,
4852 pub data: [__u32; 64usize],
4853}
4854#[repr(C)]
4855#[derive(Debug, Copy, Clone)]
4856pub struct drm_amdgpu_gem_mmap_in {
4857 #[doc = " the GEM object handle"]
4858 pub handle: __u32,
4859 pub _pad: __u32,
4860}
4861#[repr(C)]
4862#[derive(Debug, Copy, Clone)]
4863pub struct drm_amdgpu_gem_mmap_out {
4864 #[doc = " mmap offset from the vma offset manager"]
4865 pub addr_ptr: __u64,
4866}
4867#[repr(C)]
4868#[derive(Copy, Clone)]
4869pub union drm_amdgpu_gem_mmap {
4870 pub in_: drm_amdgpu_gem_mmap_in,
4871 pub out: drm_amdgpu_gem_mmap_out,
4872}
4873#[repr(C)]
4874#[derive(Debug, Copy, Clone)]
4875pub struct drm_amdgpu_gem_wait_idle_in {
4876 #[doc = " GEM object handle"]
4877 pub handle: __u32,
4878 #[doc = " For future use, no flags defined so far"]
4879 pub flags: __u32,
4880 #[doc = " Absolute timeout to wait"]
4881 pub timeout: __u64,
4882}
4883#[repr(C)]
4884#[derive(Debug, Copy, Clone)]
4885pub struct drm_amdgpu_gem_wait_idle_out {
4886 #[doc = " BO status: 0 - BO is idle, 1 - BO is busy"]
4887 pub status: __u32,
4888 #[doc = " Returned current memory domain"]
4889 pub domain: __u32,
4890}
4891#[repr(C)]
4892#[derive(Copy, Clone)]
4893pub union drm_amdgpu_gem_wait_idle {
4894 pub in_: drm_amdgpu_gem_wait_idle_in,
4895 pub out: drm_amdgpu_gem_wait_idle_out,
4896}
4897#[repr(C)]
4898#[derive(Debug, Copy, Clone)]
4899pub struct drm_amdgpu_wait_cs_in {
4900 pub handle: __u64,
4901 #[doc = " Absolute timeout to wait"]
4902 pub timeout: __u64,
4903 pub ip_type: __u32,
4904 pub ip_instance: __u32,
4905 pub ring: __u32,
4906 pub ctx_id: __u32,
4907}
4908#[repr(C)]
4909#[derive(Debug, Copy, Clone)]
4910pub struct drm_amdgpu_wait_cs_out {
4911 #[doc = " CS status: 0 - CS completed, 1 - CS still busy"]
4912 pub status: __u64,
4913}
4914#[repr(C)]
4915#[derive(Copy, Clone)]
4916pub union drm_amdgpu_wait_cs {
4917 pub in_: drm_amdgpu_wait_cs_in,
4918 pub out: drm_amdgpu_wait_cs_out,
4919}
4920#[repr(C)]
4921#[derive(Debug, Copy, Clone)]
4922pub struct drm_amdgpu_fence {
4923 pub ctx_id: __u32,
4924 pub ip_type: __u32,
4925 pub ip_instance: __u32,
4926 pub ring: __u32,
4927 pub seq_no: __u64,
4928}
4929#[repr(C)]
4930#[derive(Debug, Copy, Clone)]
4931pub struct drm_amdgpu_wait_fences_in {
4932 #[doc = " This points to uint64_t * which points to fences"]
4933 pub fences: __u64,
4934 pub fence_count: __u32,
4935 pub wait_all: __u32,
4936 pub timeout_ns: __u64,
4937}
4938#[repr(C)]
4939#[derive(Debug, Copy, Clone)]
4940pub struct drm_amdgpu_wait_fences_out {
4941 pub status: __u32,
4942 pub first_signaled: __u32,
4943}
4944#[repr(C)]
4945#[derive(Copy, Clone)]
4946pub union drm_amdgpu_wait_fences {
4947 pub in_: drm_amdgpu_wait_fences_in,
4948 pub out: drm_amdgpu_wait_fences_out,
4949}
4950#[repr(C)]
4951#[derive(Debug, Copy, Clone)]
4952pub struct drm_amdgpu_gem_op {
4953 #[doc = " GEM object handle"]
4954 pub handle: __u32,
4955 #[doc = " AMDGPU_GEM_OP_*"]
4956 pub op: __u32,
4957 #[doc = " Input or return value"]
4958 pub value: __u64,
4959}
4960#[repr(C)]
4961#[derive(Debug, Copy, Clone)]
4962pub struct drm_amdgpu_gem_va {
4963 #[doc = " GEM object handle"]
4964 pub handle: __u32,
4965 pub _pad: __u32,
4966 #[doc = " AMDGPU_VA_OP_*"]
4967 pub operation: __u32,
4968 #[doc = " AMDGPU_VM_PAGE_*"]
4969 pub flags: __u32,
4970 #[doc = " va address to assign . Must be correctly aligned."]
4971 pub va_address: __u64,
4972 #[doc = " Specify offset inside of BO to assign. Must be correctly aligned."]
4973 pub offset_in_bo: __u64,
4974 #[doc = " Specify mapping size. Must be correctly aligned."]
4975 pub map_size: __u64,
4976}
4977#[repr(C)]
4978#[derive(Debug, Copy, Clone)]
4979pub struct drm_amdgpu_cs_chunk {
4980 pub chunk_id: __u32,
4981 pub length_dw: __u32,
4982 pub chunk_data: __u64,
4983}
4984#[repr(C)]
4985#[derive(Debug, Copy, Clone)]
4986pub struct drm_amdgpu_cs_in {
4987 #[doc = " Rendering context id"]
4988 pub ctx_id: __u32,
4989 #[doc = " Handle of resource list associated with CS"]
4990 pub bo_list_handle: __u32,
4991 pub num_chunks: __u32,
4992 pub flags: __u32,
4993 #[doc = " this points to __u64 * which point to cs chunks"]
4994 pub chunks: __u64,
4995}
4996#[repr(C)]
4997#[derive(Debug, Copy, Clone)]
4998pub struct drm_amdgpu_cs_out {
4999 pub handle: __u64,
5000}
5001#[repr(C)]
5002#[derive(Copy, Clone)]
5003pub union drm_amdgpu_cs {
5004 pub in_: drm_amdgpu_cs_in,
5005 pub out: drm_amdgpu_cs_out,
5006}
5007#[repr(C)]
5008#[derive(Debug, Copy, Clone)]
5009pub struct drm_amdgpu_cs_chunk_ib {
5010 pub _pad: __u32,
5011 #[doc = " AMDGPU_IB_FLAG_*"]
5012 pub flags: __u32,
5013 #[doc = " Virtual address to begin IB execution"]
5014 pub va_start: __u64,
5015 #[doc = " Size of submission"]
5016 pub ib_bytes: __u32,
5017 #[doc = " HW IP to submit to"]
5018 pub ip_type: __u32,
5019 #[doc = " HW IP index of the same type to submit to"]
5020 pub ip_instance: __u32,
5021 #[doc = " Ring index to submit to"]
5022 pub ring: __u32,
5023}
5024#[repr(C)]
5025#[derive(Debug, Copy, Clone)]
5026pub struct drm_amdgpu_cs_chunk_dep {
5027 pub ip_type: __u32,
5028 pub ip_instance: __u32,
5029 pub ring: __u32,
5030 pub ctx_id: __u32,
5031 pub handle: __u64,
5032}
5033#[repr(C)]
5034#[derive(Debug, Copy, Clone)]
5035pub struct drm_amdgpu_cs_chunk_fence {
5036 pub handle: __u32,
5037 pub offset: __u32,
5038}
5039#[repr(C)]
5040#[derive(Debug, Copy, Clone)]
5041pub struct drm_amdgpu_cs_chunk_sem {
5042 pub handle: __u32,
5043}
5044#[repr(C)]
5045#[derive(Debug, Copy, Clone)]
5046pub struct drm_amdgpu_cs_chunk_syncobj {
5047 pub handle: __u32,
5048 pub flags: __u32,
5049 pub point: __u64,
5050}
5051#[repr(C)]
5052#[derive(Copy, Clone)]
5053pub union drm_amdgpu_fence_to_handle {
5054 pub in_: drm_amdgpu_fence_to_handle__bindgen_ty_1,
5055 pub out: drm_amdgpu_fence_to_handle__bindgen_ty_2,
5056}
5057#[repr(C)]
5058#[derive(Debug, Copy, Clone)]
5059pub struct drm_amdgpu_fence_to_handle__bindgen_ty_1 {
5060 pub fence: drm_amdgpu_fence,
5061 pub what: __u32,
5062 pub pad: __u32,
5063}
5064#[repr(C)]
5065#[derive(Debug, Copy, Clone)]
5066pub struct drm_amdgpu_fence_to_handle__bindgen_ty_2 {
5067 pub handle: __u32,
5068}
5069#[repr(C)]
5070#[derive(Copy, Clone)]
5071pub struct drm_amdgpu_cs_chunk_data {
5072 pub __bindgen_anon_1: drm_amdgpu_cs_chunk_data__bindgen_ty_1,
5073}
5074#[repr(C)]
5075#[derive(Copy, Clone)]
5076pub union drm_amdgpu_cs_chunk_data__bindgen_ty_1 {
5077 pub ib_data: drm_amdgpu_cs_chunk_ib,
5078 pub fence_data: drm_amdgpu_cs_chunk_fence,
5079}
5080#[repr(C)]
5081#[derive(Debug, Copy, Clone)]
5082pub struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
5083 pub shadow_va: __u64,
5084 pub csa_va: __u64,
5085 pub gds_va: __u64,
5086 pub flags: __u64,
5087}
5088#[repr(C)]
5089#[derive(Debug, Copy, Clone)]
5090pub struct drm_amdgpu_query_fw {
5091 #[doc = " AMDGPU_INFO_FW_*"]
5092 pub fw_type: __u32,
5093 #[doc = " Index of the IP if there are more IPs of\n the same type."]
5094 pub ip_instance: __u32,
5095 #[doc = " Index of the engine. Whether this is used depends\n on the firmware type. (e.g. MEC, SDMA)"]
5096 pub index: __u32,
5097 pub _pad: __u32,
5098}
5099#[repr(C)]
5100#[derive(Copy, Clone)]
5101pub struct drm_amdgpu_info {
5102 pub return_pointer: __u64,
5103 pub return_size: __u32,
5104 pub query: __u32,
5105 pub __bindgen_anon_1: drm_amdgpu_info__bindgen_ty_1,
5106}
5107#[repr(C)]
5108#[derive(Copy, Clone)]
5109pub union drm_amdgpu_info__bindgen_ty_1 {
5110 pub mode_crtc: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_1,
5111 pub query_hw_ip: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_2,
5112 pub read_mmr_reg: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_3,
5113 pub query_fw: drm_amdgpu_query_fw,
5114 pub vbios_info: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_4,
5115 pub sensor_info: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_5,
5116 pub video_cap: drm_amdgpu_info__bindgen_ty_1__bindgen_ty_6,
5117}
5118#[repr(C)]
5119#[derive(Debug, Copy, Clone)]
5120pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_1 {
5121 pub id: __u32,
5122 pub _pad: __u32,
5123}
5124#[repr(C)]
5125#[derive(Debug, Copy, Clone)]
5126pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_2 {
5127 #[doc = " AMDGPU_HW_IP_*"]
5128 pub type_: __u32,
5129 #[doc = " Index of the IP if there are more IPs of the same\n type. Ignored by AMDGPU_INFO_HW_IP_COUNT."]
5130 pub ip_instance: __u32,
5131}
5132#[repr(C)]
5133#[derive(Debug, Copy, Clone)]
5134pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_3 {
5135 pub dword_offset: __u32,
5136 #[doc = " number of registers to read"]
5137 pub count: __u32,
5138 pub instance: __u32,
5139 #[doc = " For future use, no flags defined so far"]
5140 pub flags: __u32,
5141}
5142#[repr(C)]
5143#[derive(Debug, Copy, Clone)]
5144pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_4 {
5145 pub type_: __u32,
5146 pub offset: __u32,
5147}
5148#[repr(C)]
5149#[derive(Debug, Copy, Clone)]
5150pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_5 {
5151 pub type_: __u32,
5152}
5153#[repr(C)]
5154#[derive(Debug, Copy, Clone)]
5155pub struct drm_amdgpu_info__bindgen_ty_1__bindgen_ty_6 {
5156 pub type_: __u32,
5157}
5158#[repr(C)]
5159#[derive(Debug, Copy, Clone)]
5160pub struct drm_amdgpu_info_gds {
5161 #[doc = " GDS GFX partition size"]
5162 pub gds_gfx_partition_size: __u32,
5163 #[doc = " GDS compute partition size"]
5164 pub compute_partition_size: __u32,
5165 #[doc = " total GDS memory size"]
5166 pub gds_total_size: __u32,
5167 #[doc = " GWS size per GFX partition"]
5168 pub gws_per_gfx_partition: __u32,
5169 #[doc = " GSW size per compute partition"]
5170 pub gws_per_compute_partition: __u32,
5171 #[doc = " OA size per GFX partition"]
5172 pub oa_per_gfx_partition: __u32,
5173 #[doc = " OA size per compute partition"]
5174 pub oa_per_compute_partition: __u32,
5175 pub _pad: __u32,
5176}
5177#[repr(C)]
5178#[derive(Debug, Copy, Clone)]
5179pub struct drm_amdgpu_info_vram_gtt {
5180 pub vram_size: __u64,
5181 pub vram_cpu_accessible_size: __u64,
5182 pub gtt_size: __u64,
5183}
5184#[repr(C)]
5185#[derive(Debug, Copy, Clone)]
5186pub struct drm_amdgpu_heap_info {
5187 #[doc = " max. physical memory"]
5188 pub total_heap_size: __u64,
5189 #[doc = " Theoretical max. available memory in the given heap"]
5190 pub usable_heap_size: __u64,
5191 #[doc = " Number of bytes allocated in the heap. This includes all processes\n and private allocations in the kernel. It changes when new buffers\n are allocated, freed, and moved. It cannot be larger than\n heap_size."]
5192 pub heap_usage: __u64,
5193 #[doc = " Theoretical possible max. size of buffer which\n could be allocated in the given heap"]
5194 pub max_allocation: __u64,
5195}
5196#[repr(C)]
5197#[derive(Debug, Copy, Clone)]
5198pub struct drm_amdgpu_memory_info {
5199 pub vram: drm_amdgpu_heap_info,
5200 pub cpu_accessible_vram: drm_amdgpu_heap_info,
5201 pub gtt: drm_amdgpu_heap_info,
5202}
5203#[repr(C)]
5204#[derive(Debug, Copy, Clone)]
5205pub struct drm_amdgpu_info_firmware {
5206 pub ver: __u32,
5207 pub feature: __u32,
5208}
5209#[repr(C)]
5210#[derive(Debug, Copy, Clone)]
5211pub struct drm_amdgpu_info_vbios {
5212 pub name: [__u8; 64usize],
5213 pub vbios_pn: [__u8; 64usize],
5214 pub version: __u32,
5215 pub pad: __u32,
5216 pub vbios_ver_str: [__u8; 32usize],
5217 pub date: [__u8; 32usize],
5218}
5219#[repr(C)]
5220#[derive(Debug, Copy, Clone)]
5221pub struct drm_amdgpu_info_device {
5222 #[doc = " PCI Device ID"]
5223 pub device_id: __u32,
5224 #[doc = " Internal chip revision: A0, A1, etc.)"]
5225 pub chip_rev: __u32,
5226 pub external_rev: __u32,
5227 #[doc = " Revision id in PCI Config space"]
5228 pub pci_rev: __u32,
5229 pub family: __u32,
5230 pub num_shader_engines: __u32,
5231 pub num_shader_arrays_per_engine: __u32,
5232 pub gpu_counter_freq: __u32,
5233 pub max_engine_clock: __u64,
5234 pub max_memory_clock: __u64,
5235 pub cu_active_number: __u32,
5236 pub cu_ao_mask: __u32,
5237 pub cu_bitmap: [[__u32; 4usize]; 4usize],
5238 #[doc = " Render backend pipe mask. One render backend is CB+DB."]
5239 pub enabled_rb_pipes_mask: __u32,
5240 pub num_rb_pipes: __u32,
5241 pub num_hw_gfx_contexts: __u32,
5242 pub pcie_gen: __u32,
5243 pub ids_flags: __u64,
5244 #[doc = " Starting virtual address for UMDs."]
5245 pub virtual_address_offset: __u64,
5246 #[doc = " The maximum virtual address"]
5247 pub virtual_address_max: __u64,
5248 #[doc = " Required alignment of virtual addresses."]
5249 pub virtual_address_alignment: __u32,
5250 #[doc = " Page table entry - fragment size"]
5251 pub pte_fragment_size: __u32,
5252 pub gart_page_size: __u32,
5253 #[doc = " constant engine ram size"]
5254 pub ce_ram_size: __u32,
5255 #[doc = " video memory type info"]
5256 pub vram_type: __u32,
5257 #[doc = " video memory bit width"]
5258 pub vram_bit_width: __u32,
5259 pub vce_harvest_config: __u32,
5260 pub gc_double_offchip_lds_buf: __u32,
5261 pub prim_buf_gpu_addr: __u64,
5262 pub pos_buf_gpu_addr: __u64,
5263 pub cntl_sb_buf_gpu_addr: __u64,
5264 pub param_buf_gpu_addr: __u64,
5265 pub prim_buf_size: __u32,
5266 pub pos_buf_size: __u32,
5267 pub cntl_sb_buf_size: __u32,
5268 pub param_buf_size: __u32,
5269 pub wave_front_size: __u32,
5270 pub num_shader_visible_vgprs: __u32,
5271 pub num_cu_per_sh: __u32,
5272 pub num_tcc_blocks: __u32,
5273 pub gs_vgt_table_depth: __u32,
5274 pub gs_prim_buffer_depth: __u32,
5275 pub max_gs_waves_per_vgt: __u32,
5276 pub pcie_num_lanes: __u32,
5277 pub cu_ao_bitmap: [[__u32; 4usize]; 4usize],
5278 #[doc = " Starting high virtual address for UMDs."]
5279 pub high_va_offset: __u64,
5280 #[doc = " The maximum high virtual address"]
5281 pub high_va_max: __u64,
5282 pub pa_sc_tile_steering_override: __u32,
5283 pub tcc_disabled_mask: __u64,
5284 pub min_engine_clock: __u64,
5285 pub min_memory_clock: __u64,
5286 pub tcp_cache_size: __u32,
5287 pub num_sqc_per_wgp: __u32,
5288 pub sqc_data_cache_size: __u32,
5289 pub sqc_inst_cache_size: __u32,
5290 pub gl1c_cache_size: __u32,
5291 pub gl2c_cache_size: __u32,
5292 pub mall_size: __u64,
5293 pub enabled_rb_pipes_mask_hi: __u32,
5294 pub shadow_size: __u32,
5295 pub shadow_alignment: __u32,
5296 pub csa_size: __u32,
5297 pub csa_alignment: __u32,
5298}
5299#[repr(C)]
5300#[derive(Debug, Copy, Clone)]
5301pub struct drm_amdgpu_info_hw_ip {
5302 #[doc = " Version of h/w IP"]
5303 pub hw_ip_version_major: __u32,
5304 pub hw_ip_version_minor: __u32,
5305 #[doc = " Capabilities"]
5306 pub capabilities_flags: __u64,
5307 #[doc = " command buffer address start alignment"]
5308 pub ib_start_alignment: __u32,
5309 #[doc = " command buffer size alignment"]
5310 pub ib_size_alignment: __u32,
5311 #[doc = " Bitmask of available rings. Bit 0 means ring 0, etc."]
5312 pub available_rings: __u32,
5313 #[doc = " version info: bits 23:16 major, 15:8 minor, 7:0 revision"]
5314 pub ip_discovery_version: __u32,
5315}
5316#[repr(C)]
5317#[derive(Debug, Copy, Clone)]
5318pub struct drm_amdgpu_info_num_handles {
5319 #[doc = " Max handles as supported by firmware for UVD"]
5320 pub uvd_max_handles: __u32,
5321 #[doc = " Handles currently in use for UVD"]
5322 pub uvd_used_handles: __u32,
5323}
5324#[repr(C)]
5325#[derive(Debug, Copy, Clone)]
5326pub struct drm_amdgpu_info_vce_clock_table_entry {
5327 #[doc = " System clock"]
5328 pub sclk: __u32,
5329 #[doc = " Memory clock"]
5330 pub mclk: __u32,
5331 #[doc = " VCE clock"]
5332 pub eclk: __u32,
5333 pub pad: __u32,
5334}
5335#[repr(C)]
5336#[derive(Debug, Copy, Clone)]
5337pub struct drm_amdgpu_info_vce_clock_table {
5338 pub entries: [drm_amdgpu_info_vce_clock_table_entry; 6usize],
5339 pub num_valid_entries: __u32,
5340 pub pad: __u32,
5341}
5342#[repr(C)]
5343#[derive(Debug, Copy, Clone)]
5344pub struct drm_amdgpu_info_video_codec_info {
5345 pub valid: __u32,
5346 pub max_width: __u32,
5347 pub max_height: __u32,
5348 pub max_pixels_per_frame: __u32,
5349 pub max_level: __u32,
5350 pub pad: __u32,
5351}
5352#[repr(C)]
5353#[derive(Debug, Copy, Clone)]
5354pub struct drm_amdgpu_info_video_caps {
5355 pub codec_info: [drm_amdgpu_info_video_codec_info; 8usize],
5356}
5357#[repr(C)]
5358#[derive(Debug, Copy, Clone)]
5359pub struct drm_amdgpu_info_gpuvm_fault {
5360 pub addr: __u64,
5361 pub status: __u32,
5362 pub vmhub: __u32,
5363}
5364pub const atom_bios_header_version_def_ATOM_MAJOR_VERSION: atom_bios_header_version_def = 3;
5365pub const atom_bios_header_version_def_ATOM_MINOR_VERSION: atom_bios_header_version_def = 3;
5366pub type atom_bios_header_version_def = ::core::ffi::c_uint;
5367pub const atom_crtc_def_ATOM_CRTC1: atom_crtc_def = 0;
5368pub const atom_crtc_def_ATOM_CRTC2: atom_crtc_def = 1;
5369pub const atom_crtc_def_ATOM_CRTC3: atom_crtc_def = 2;
5370pub const atom_crtc_def_ATOM_CRTC4: atom_crtc_def = 3;
5371pub const atom_crtc_def_ATOM_CRTC5: atom_crtc_def = 4;
5372pub const atom_crtc_def_ATOM_CRTC6: atom_crtc_def = 5;
5373pub const atom_crtc_def_ATOM_CRTC_INVALID: atom_crtc_def = 255;
5374pub type atom_crtc_def = ::core::ffi::c_uint;
5375pub const atom_ppll_def_ATOM_PPLL0: atom_ppll_def = 2;
5376pub const atom_ppll_def_ATOM_GCK_DFS: atom_ppll_def = 8;
5377pub const atom_ppll_def_ATOM_FCH_CLK: atom_ppll_def = 9;
5378pub const atom_ppll_def_ATOM_DP_DTO: atom_ppll_def = 11;
5379pub const atom_ppll_def_ATOM_COMBOPHY_PLL0: atom_ppll_def = 20;
5380pub const atom_ppll_def_ATOM_COMBOPHY_PLL1: atom_ppll_def = 21;
5381pub const atom_ppll_def_ATOM_COMBOPHY_PLL2: atom_ppll_def = 22;
5382pub const atom_ppll_def_ATOM_COMBOPHY_PLL3: atom_ppll_def = 23;
5383pub const atom_ppll_def_ATOM_COMBOPHY_PLL4: atom_ppll_def = 24;
5384pub const atom_ppll_def_ATOM_COMBOPHY_PLL5: atom_ppll_def = 25;
5385pub const atom_ppll_def_ATOM_PPLL_INVALID: atom_ppll_def = 255;
5386pub type atom_ppll_def = ::core::ffi::c_uint;
5387pub const atom_dig_def_ASIC_INT_DIG1_ENCODER_ID: atom_dig_def = 3;
5388pub const atom_dig_def_ASIC_INT_DIG2_ENCODER_ID: atom_dig_def = 9;
5389pub const atom_dig_def_ASIC_INT_DIG3_ENCODER_ID: atom_dig_def = 10;
5390pub const atom_dig_def_ASIC_INT_DIG4_ENCODER_ID: atom_dig_def = 11;
5391pub const atom_dig_def_ASIC_INT_DIG5_ENCODER_ID: atom_dig_def = 12;
5392pub const atom_dig_def_ASIC_INT_DIG6_ENCODER_ID: atom_dig_def = 13;
5393pub const atom_dig_def_ASIC_INT_DIG7_ENCODER_ID: atom_dig_def = 14;
5394pub type atom_dig_def = ::core::ffi::c_uint;
5395pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP: atom_encode_mode_def = 0;
5396pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_SST: atom_encode_mode_def = 0;
5397pub const atom_encode_mode_def_ATOM_ENCODER_MODE_LVDS: atom_encode_mode_def = 1;
5398pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DVI: atom_encode_mode_def = 2;
5399pub const atom_encode_mode_def_ATOM_ENCODER_MODE_HDMI: atom_encode_mode_def = 3;
5400pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_AUDIO: atom_encode_mode_def = 5;
5401pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DP_MST: atom_encode_mode_def = 5;
5402pub const atom_encode_mode_def_ATOM_ENCODER_MODE_CRT: atom_encode_mode_def = 15;
5403pub const atom_encode_mode_def_ATOM_ENCODER_MODE_DVO: atom_encode_mode_def = 16;
5404pub type atom_encode_mode_def = ::core::ffi::c_uint;
5405pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P1PLL: atom_encoder_refclk_src_def = 0;
5406pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P2PLL: atom_encoder_refclk_src_def = 1;
5407pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_P3PLL: atom_encoder_refclk_src_def = 2;
5408pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_EXTCLK: atom_encoder_refclk_src_def = 3;
5409pub const atom_encoder_refclk_src_def_ENCODER_REFCLK_SRC_INVALID: atom_encoder_refclk_src_def = 255;
5410pub type atom_encoder_refclk_src_def = ::core::ffi::c_uint;
5411pub const atom_scaler_def_ATOM_SCALER_DISABLE: atom_scaler_def = 0;
5412pub const atom_scaler_def_ATOM_SCALER_CENTER: atom_scaler_def = 1;
5413pub const atom_scaler_def_ATOM_SCALER_EXPANSION: atom_scaler_def = 2;
5414pub type atom_scaler_def = ::core::ffi::c_uint;
5415pub const atom_operation_def_ATOM_DISABLE: atom_operation_def = 0;
5416pub const atom_operation_def_ATOM_ENABLE: atom_operation_def = 1;
5417pub const atom_operation_def_ATOM_INIT: atom_operation_def = 7;
5418pub const atom_operation_def_ATOM_GET_STATUS: atom_operation_def = 8;
5419pub type atom_operation_def = ::core::ffi::c_uint;
5420pub const atom_embedded_display_op_def_ATOM_LCD_BL_OFF: atom_embedded_display_op_def = 2;
5421pub const atom_embedded_display_op_def_ATOM_LCD_BL_OM: atom_embedded_display_op_def = 3;
5422pub const atom_embedded_display_op_def_ATOM_LCD_BL_BRIGHTNESS_CONTROL:
5423 atom_embedded_display_op_def = 4;
5424pub const atom_embedded_display_op_def_ATOM_LCD_SELFTEST_START: atom_embedded_display_op_def = 5;
5425pub const atom_embedded_display_op_def_ATOM_LCD_SELFTEST_STOP: atom_embedded_display_op_def = 6;
5426pub type atom_embedded_display_op_def = ::core::ffi::c_uint;
5427pub const atom_spread_spectrum_mode_ATOM_SS_CENTER_OR_DOWN_MODE_MASK: atom_spread_spectrum_mode = 1;
5428pub const atom_spread_spectrum_mode_ATOM_SS_DOWN_SPREAD_MODE: atom_spread_spectrum_mode = 0;
5429pub const atom_spread_spectrum_mode_ATOM_SS_CENTRE_SPREAD_MODE: atom_spread_spectrum_mode = 1;
5430pub const atom_spread_spectrum_mode_ATOM_INT_OR_EXT_SS_MASK: atom_spread_spectrum_mode = 2;
5431pub const atom_spread_spectrum_mode_ATOM_INTERNAL_SS_MASK: atom_spread_spectrum_mode = 0;
5432pub const atom_spread_spectrum_mode_ATOM_EXTERNAL_SS_MASK: atom_spread_spectrum_mode = 2;
5433pub type atom_spread_spectrum_mode = ::core::ffi::c_uint;
5434pub const atom_panel_bit_per_color_PANEL_BPC_UNDEFINE: atom_panel_bit_per_color = 0;
5435pub const atom_panel_bit_per_color_PANEL_6BIT_PER_COLOR: atom_panel_bit_per_color = 1;
5436pub const atom_panel_bit_per_color_PANEL_8BIT_PER_COLOR: atom_panel_bit_per_color = 2;
5437pub const atom_panel_bit_per_color_PANEL_10BIT_PER_COLOR: atom_panel_bit_per_color = 3;
5438pub const atom_panel_bit_per_color_PANEL_12BIT_PER_COLOR: atom_panel_bit_per_color = 4;
5439pub const atom_panel_bit_per_color_PANEL_16BIT_PER_COLOR: atom_panel_bit_per_color = 5;
5440pub type atom_panel_bit_per_color = ::core::ffi::c_uint;
5441pub const atom_voltage_type_VOLTAGE_TYPE_VDDC: atom_voltage_type = 1;
5442pub const atom_voltage_type_VOLTAGE_TYPE_MVDDC: atom_voltage_type = 2;
5443pub const atom_voltage_type_VOLTAGE_TYPE_MVDDQ: atom_voltage_type = 3;
5444pub const atom_voltage_type_VOLTAGE_TYPE_VDDCI: atom_voltage_type = 4;
5445pub const atom_voltage_type_VOLTAGE_TYPE_VDDGFX: atom_voltage_type = 5;
5446pub const atom_voltage_type_VOLTAGE_TYPE_PCC: atom_voltage_type = 6;
5447pub const atom_voltage_type_VOLTAGE_TYPE_MVPP: atom_voltage_type = 7;
5448pub const atom_voltage_type_VOLTAGE_TYPE_LEDDPM: atom_voltage_type = 8;
5449pub const atom_voltage_type_VOLTAGE_TYPE_PCC_MVDD: atom_voltage_type = 9;
5450pub const atom_voltage_type_VOLTAGE_TYPE_PCIE_VDDC: atom_voltage_type = 10;
5451pub const atom_voltage_type_VOLTAGE_TYPE_PCIE_VDDR: atom_voltage_type = 11;
5452pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_1: atom_voltage_type = 17;
5453pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_2: atom_voltage_type = 18;
5454pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_3: atom_voltage_type = 19;
5455pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_4: atom_voltage_type = 20;
5456pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_5: atom_voltage_type = 21;
5457pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_6: atom_voltage_type = 22;
5458pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_7: atom_voltage_type = 23;
5459pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_8: atom_voltage_type = 24;
5460pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_9: atom_voltage_type = 25;
5461pub const atom_voltage_type_VOLTAGE_TYPE_GENERIC_I2C_10: atom_voltage_type = 26;
5462pub type atom_voltage_type = ::core::ffi::c_uint;
5463pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_GDDR5: atom_dgpu_vram_type = 80;
5464pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM2: atom_dgpu_vram_type = 96;
5465pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM2E: atom_dgpu_vram_type = 97;
5466pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_GDDR6: atom_dgpu_vram_type = 112;
5467pub const atom_dgpu_vram_type_ATOM_DGPU_VRAM_TYPE_HBM3: atom_dgpu_vram_type = 128;
5468pub type atom_dgpu_vram_type = ::core::ffi::c_uint;
5469pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 0;
5470pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 1;
5471pub const atom_dp_vs_preemph_def_DP_VS_LEVEL2_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 2;
5472pub const atom_dp_vs_preemph_def_DP_VS_LEVEL3_PREEMPH_LEVEL0: atom_dp_vs_preemph_def = 3;
5473pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 8;
5474pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 9;
5475pub const atom_dp_vs_preemph_def_DP_VS_LEVEL2_PREEMPH_LEVEL1: atom_dp_vs_preemph_def = 10;
5476pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL2: atom_dp_vs_preemph_def = 16;
5477pub const atom_dp_vs_preemph_def_DP_VS_LEVEL1_PREEMPH_LEVEL2: atom_dp_vs_preemph_def = 17;
5478pub const atom_dp_vs_preemph_def_DP_VS_LEVEL0_PREEMPH_LEVEL3: atom_dp_vs_preemph_def = 24;
5479pub type atom_dp_vs_preemph_def = ::core::ffi::c_uint;
5480pub const atombios_image_offset_OFFSET_TO_ATOM_ROM_HEADER_POINTER: atombios_image_offset = 72;
5481pub const atombios_image_offset_OFFSET_TO_ATOM_ROM_IMAGE_SIZE: atombios_image_offset = 2;
5482pub const atombios_image_offset_OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE: atombios_image_offset = 148;
5483pub const atombios_image_offset_MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE: atombios_image_offset = 20;
5484pub const atombios_image_offset_OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS: atombios_image_offset =
5485 47;
5486pub const atombios_image_offset_OFFSET_TO_GET_ATOMBIOS_STRING_START: atombios_image_offset = 110;
5487pub const atombios_image_offset_OFFSET_TO_VBIOS_PART_NUMBER: atombios_image_offset = 128;
5488pub const atombios_image_offset_OFFSET_TO_VBIOS_DATE: atombios_image_offset = 80;
5489pub type atombios_image_offset = ::core::ffi::c_uint;
5490#[doc = " Common header for all tables (Data table, Command function).\n Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.\n And the pointer actually points to this header."]
5491#[repr(C, packed)]
5492#[derive(Debug, Copy, Clone)]
5493pub struct atom_common_table_header {
5494 pub structuresize: u16,
5495 pub format_revision: u8,
5496 pub content_revision: u8,
5497}
5498#[doc = " Structure stores the ROM header."]
5499#[repr(C, packed)]
5500#[derive(Debug, Copy, Clone)]
5501pub struct atom_rom_header_v2_2 {
5502 pub table_header: atom_common_table_header,
5503 pub atom_bios_string: [u8; 4usize],
5504 pub bios_segment_address: u16,
5505 pub protectedmodeoffset: u16,
5506 pub configfilenameoffset: u16,
5507 pub crc_block_offset: u16,
5508 pub vbios_bootupmessageoffset: u16,
5509 pub int10_offset: u16,
5510 pub pcibusdevinitcode: u16,
5511 pub iobaseaddress: u16,
5512 pub subsystem_vendor_id: u16,
5513 pub subsystem_id: u16,
5514 pub pci_info_offset: u16,
5515 pub masterhwfunction_offset: u16,
5516 pub masterdatatable_offset: u16,
5517 pub reserved: u16,
5518 pub pspdirtableoffset: u32,
5519}
5520#[doc = " Structures used in Command.mtb, each function name is not given here since those function could change from time to time\n The real functionality of each function is associated with the parameter structure version when defined\n For all internal cmd function definitions, please reference to atomstruct.h"]
5521#[repr(C, packed)]
5522#[derive(Debug, Copy, Clone)]
5523pub struct atom_master_list_of_command_functions_v2_1 {
5524 pub asic_init: u16,
5525 pub cmd_function1: u16,
5526 pub cmd_function2: u16,
5527 pub cmd_function3: u16,
5528 pub digxencodercontrol: u16,
5529 pub cmd_function5: u16,
5530 pub cmd_function6: u16,
5531 pub cmd_function7: u16,
5532 pub cmd_function8: u16,
5533 pub cmd_function9: u16,
5534 pub setengineclock: u16,
5535 pub setmemoryclock: u16,
5536 pub setpixelclock: u16,
5537 pub enabledisppowergating: u16,
5538 pub cmd_function14: u16,
5539 pub cmd_function15: u16,
5540 pub cmd_function16: u16,
5541 pub cmd_function17: u16,
5542 pub cmd_function18: u16,
5543 pub cmd_function19: u16,
5544 pub cmd_function20: u16,
5545 pub cmd_function21: u16,
5546 pub cmd_function22: u16,
5547 pub cmd_function23: u16,
5548 pub cmd_function24: u16,
5549 pub cmd_function25: u16,
5550 pub cmd_function26: u16,
5551 pub cmd_function27: u16,
5552 pub cmd_function28: u16,
5553 pub cmd_function29: u16,
5554 pub cmd_function30: u16,
5555 pub cmd_function31: u16,
5556 pub cmd_function32: u16,
5557 pub cmd_function33: u16,
5558 pub blankcrtc: u16,
5559 pub enablecrtc: u16,
5560 pub cmd_function36: u16,
5561 pub cmd_function37: u16,
5562 pub cmd_function38: u16,
5563 pub cmd_function39: u16,
5564 pub cmd_function40: u16,
5565 pub getsmuclockinfo: u16,
5566 pub selectcrtc_source: u16,
5567 pub cmd_function43: u16,
5568 pub cmd_function44: u16,
5569 pub cmd_function45: u16,
5570 pub setdceclock: u16,
5571 pub getmemoryclock: u16,
5572 pub getengineclock: u16,
5573 pub setcrtc_usingdtdtiming: u16,
5574 pub externalencodercontrol: u16,
5575 pub cmd_function51: u16,
5576 pub cmd_function52: u16,
5577 pub cmd_function53: u16,
5578 pub processi2cchanneltransaction: u16,
5579 pub cmd_function55: u16,
5580 pub cmd_function56: u16,
5581 pub cmd_function57: u16,
5582 pub cmd_function58: u16,
5583 pub cmd_function59: u16,
5584 pub computegpuclockparam: u16,
5585 pub cmd_function61: u16,
5586 pub cmd_function62: u16,
5587 pub dynamicmemorysettings: u16,
5588 pub memorytraining: u16,
5589 pub cmd_function65: u16,
5590 pub cmd_function66: u16,
5591 pub setvoltage: u16,
5592 pub cmd_function68: u16,
5593 pub readefusevalue: u16,
5594 pub cmd_function70: u16,
5595 pub cmd_function71: u16,
5596 pub cmd_function72: u16,
5597 pub cmd_function73: u16,
5598 pub cmd_function74: u16,
5599 pub cmd_function75: u16,
5600 pub dig1transmittercontrol: u16,
5601 pub cmd_function77: u16,
5602 pub processauxchanneltransaction: u16,
5603 pub cmd_function79: u16,
5604 pub getvoltageinfo: u16,
5605}
5606#[repr(C)]
5607#[derive(Debug, Copy, Clone)]
5608pub struct atom_master_command_function_v2_1 {
5609 pub table_header: atom_common_table_header,
5610 pub listofcmdfunctions: atom_master_list_of_command_functions_v2_1,
5611}
5612#[doc = " Structures used in every command function"]
5613#[repr(C)]
5614#[derive(Debug, Copy, Clone)]
5615pub struct atom_function_attribute {
5616 pub _bitfield_align_1: [u8; 0],
5617 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 2usize]>,
5618}
5619impl atom_function_attribute {
5620 #[inline]
5621 pub fn ws_in_bytes(&self) -> u16 {
5622 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u16) }
5623 }
5624 #[inline]
5625 pub fn set_ws_in_bytes(&mut self, val: u16) {
5626 unsafe {
5627 let val: u16 = ::core::mem::transmute(val);
5628 self._bitfield_1.set(0usize, 8u8, val as u64)
5629 }
5630 }
5631 #[inline]
5632 pub unsafe fn ws_in_bytes_raw(this: *const Self) -> u16 {
5633 unsafe {
5634 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
5635 ::core::ptr::addr_of!((*this)._bitfield_1),
5636 0usize,
5637 8u8,
5638 ) as u16)
5639 }
5640 }
5641 #[inline]
5642 pub unsafe fn set_ws_in_bytes_raw(this: *mut Self, val: u16) {
5643 unsafe {
5644 let val: u16 = ::core::mem::transmute(val);
5645 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
5646 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
5647 0usize,
5648 8u8,
5649 val as u64,
5650 )
5651 }
5652 }
5653 #[inline]
5654 pub fn ps_in_bytes(&self) -> u16 {
5655 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 7u8) as u16) }
5656 }
5657 #[inline]
5658 pub fn set_ps_in_bytes(&mut self, val: u16) {
5659 unsafe {
5660 let val: u16 = ::core::mem::transmute(val);
5661 self._bitfield_1.set(8usize, 7u8, val as u64)
5662 }
5663 }
5664 #[inline]
5665 pub unsafe fn ps_in_bytes_raw(this: *const Self) -> u16 {
5666 unsafe {
5667 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
5668 ::core::ptr::addr_of!((*this)._bitfield_1),
5669 8usize,
5670 7u8,
5671 ) as u16)
5672 }
5673 }
5674 #[inline]
5675 pub unsafe fn set_ps_in_bytes_raw(this: *mut Self, val: u16) {
5676 unsafe {
5677 let val: u16 = ::core::mem::transmute(val);
5678 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
5679 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
5680 8usize,
5681 7u8,
5682 val as u64,
5683 )
5684 }
5685 }
5686 #[inline]
5687 pub fn updated_by_util(&self) -> u16 {
5688 unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u16) }
5689 }
5690 #[inline]
5691 pub fn set_updated_by_util(&mut self, val: u16) {
5692 unsafe {
5693 let val: u16 = ::core::mem::transmute(val);
5694 self._bitfield_1.set(15usize, 1u8, val as u64)
5695 }
5696 }
5697 #[inline]
5698 pub unsafe fn updated_by_util_raw(this: *const Self) -> u16 {
5699 unsafe {
5700 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
5701 ::core::ptr::addr_of!((*this)._bitfield_1),
5702 15usize,
5703 1u8,
5704 ) as u16)
5705 }
5706 }
5707 #[inline]
5708 pub unsafe fn set_updated_by_util_raw(this: *mut Self, val: u16) {
5709 unsafe {
5710 let val: u16 = ::core::mem::transmute(val);
5711 <__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
5712 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
5713 15usize,
5714 1u8,
5715 val as u64,
5716 )
5717 }
5718 }
5719 #[inline]
5720 pub fn new_bitfield_1(
5721 ws_in_bytes: u16,
5722 ps_in_bytes: u16,
5723 updated_by_util: u16,
5724 ) -> __BindgenBitfieldUnit<[u8; 2usize]> {
5725 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 2usize]> = Default::default();
5726 __bindgen_bitfield_unit.set(0usize, 8u8, {
5727 let ws_in_bytes: u16 = unsafe { ::core::mem::transmute(ws_in_bytes) };
5728 ws_in_bytes as u64
5729 });
5730 __bindgen_bitfield_unit.set(8usize, 7u8, {
5731 let ps_in_bytes: u16 = unsafe { ::core::mem::transmute(ps_in_bytes) };
5732 ps_in_bytes as u64
5733 });
5734 __bindgen_bitfield_unit.set(15usize, 1u8, {
5735 let updated_by_util: u16 = unsafe { ::core::mem::transmute(updated_by_util) };
5736 updated_by_util as u64
5737 });
5738 __bindgen_bitfield_unit
5739 }
5740}
5741#[doc = " Common header for all hw functions.\n Every function pointed by _master_list_of_hw_function has this common header.\n And the pointer actually points to this header."]
5742#[repr(C)]
5743#[derive(Debug, Copy, Clone)]
5744pub struct atom_rom_hw_function_header {
5745 pub func_header: atom_common_table_header,
5746 pub func_attrib: atom_function_attribute,
5747}
5748#[doc = " Structures used in data.mtb, each data table name is not given here since those data table could change from time to time\n The real name of each table is given when its data structure version is defined"]
5749#[repr(C, packed)]
5750#[derive(Debug, Copy, Clone)]
5751pub struct atom_master_list_of_data_tables_v2_1 {
5752 pub utilitypipeline: u16,
5753 pub multimedia_info: u16,
5754 pub smc_dpm_info: u16,
5755 pub sw_datatable3: u16,
5756 pub firmwareinfo: u16,
5757 pub sw_datatable5: u16,
5758 pub lcd_info: u16,
5759 pub sw_datatable7: u16,
5760 pub smu_info: u16,
5761 pub sw_datatable9: u16,
5762 pub sw_datatable10: u16,
5763 pub vram_usagebyfirmware: u16,
5764 pub gpio_pin_lut: u16,
5765 pub sw_datatable13: u16,
5766 pub gfx_info: u16,
5767 pub powerplayinfo: u16,
5768 pub sw_datatable16: u16,
5769 pub sw_datatable17: u16,
5770 pub sw_datatable18: u16,
5771 pub sw_datatable19: u16,
5772 pub sw_datatable20: u16,
5773 pub sw_datatable21: u16,
5774 pub displayobjectinfo: u16,
5775 pub indirectioaccess: u16,
5776 pub umc_info: u16,
5777 pub sw_datatable25: u16,
5778 pub sw_datatable26: u16,
5779 pub dce_info: u16,
5780 pub vram_info: u16,
5781 pub sw_datatable29: u16,
5782 pub integratedsysteminfo: u16,
5783 pub asic_profiling_info: u16,
5784 pub voltageobject_info: u16,
5785 pub sw_datatable33: u16,
5786 pub sw_datatable34: u16,
5787}
5788#[repr(C)]
5789#[derive(Debug, Copy, Clone)]
5790pub struct atom_master_data_table_v2_1 {
5791 pub table_header: atom_common_table_header,
5792 pub listOfdatatables: atom_master_list_of_data_tables_v2_1,
5793}
5794#[repr(C, packed)]
5795#[derive(Debug, Copy, Clone)]
5796pub struct atom_dtd_format {
5797 pub pixclk: u16,
5798 pub h_active: u16,
5799 pub h_blanking_time: u16,
5800 pub v_active: u16,
5801 pub v_blanking_time: u16,
5802 pub h_sync_offset: u16,
5803 pub h_sync_width: u16,
5804 pub v_sync_offset: u16,
5805 pub v_syncwidth: u16,
5806 pub reserved: u16,
5807 pub reserved0: u16,
5808 pub h_border: u8,
5809 pub v_border: u8,
5810 pub miscinfo: u16,
5811 pub atom_mode_id: u8,
5812 pub refreshrate: u8,
5813}
5814pub const atom_dtd_format_modemiscinfo_ATOM_HSYNC_POLARITY: atom_dtd_format_modemiscinfo = 2;
5815pub const atom_dtd_format_modemiscinfo_ATOM_VSYNC_POLARITY: atom_dtd_format_modemiscinfo = 4;
5816pub const atom_dtd_format_modemiscinfo_ATOM_H_REPLICATIONBY2: atom_dtd_format_modemiscinfo = 16;
5817pub const atom_dtd_format_modemiscinfo_ATOM_V_REPLICATIONBY2: atom_dtd_format_modemiscinfo = 32;
5818pub const atom_dtd_format_modemiscinfo_ATOM_INTERLACE: atom_dtd_format_modemiscinfo = 128;
5819pub const atom_dtd_format_modemiscinfo_ATOM_COMPOSITESYNC: atom_dtd_format_modemiscinfo = 64;
5820pub type atom_dtd_format_modemiscinfo = ::core::ffi::c_uint;
5821#[repr(C, packed)]
5822#[derive(Debug, Copy, Clone)]
5823pub struct atom_firmware_info_v3_1 {
5824 pub table_header: atom_common_table_header,
5825 pub firmware_revision: u32,
5826 pub bootup_sclk_in10khz: u32,
5827 pub bootup_mclk_in10khz: u32,
5828 pub firmware_capability: u32,
5829 pub main_call_parser_entry: u32,
5830 pub bios_scratch_reg_startaddr: u32,
5831 pub bootup_vddc_mv: u16,
5832 pub bootup_vddci_mv: u16,
5833 pub bootup_mvddc_mv: u16,
5834 pub bootup_vddgfx_mv: u16,
5835 pub mem_module_id: u8,
5836 pub coolingsolution_id: u8,
5837 pub reserved1: [u8; 2usize],
5838 pub mc_baseaddr_high: u32,
5839 pub mc_baseaddr_low: u32,
5840 pub reserved2: [u32; 6usize],
5841}
5842pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_FIRMWARE_POSTED:
5843 atombios_firmware_capability = 1;
5844pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION:
5845 atombios_firmware_capability = 2;
5846pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_WMI_SUPPORT: atombios_firmware_capability =
5847 64;
5848pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_HWEMU_ENABLE:
5849 atombios_firmware_capability = 128;
5850pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG:
5851 atombios_firmware_capability = 256;
5852pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_SRAM_ECC: atombios_firmware_capability =
5853 512;
5854pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING:
5855 atombios_firmware_capability = 1024;
5856pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT:
5857 atombios_firmware_capability = 32768;
5858pub const atombios_firmware_capability_ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE:
5859 atombios_firmware_capability = 131072;
5860pub type atombios_firmware_capability = ::core::ffi::c_uint;
5861pub const atom_cooling_solution_id_AIR_COOLING: atom_cooling_solution_id = 0;
5862pub const atom_cooling_solution_id_LIQUID_COOLING: atom_cooling_solution_id = 1;
5863pub type atom_cooling_solution_id = ::core::ffi::c_uint;
5864#[repr(C, packed)]
5865#[derive(Debug, Copy, Clone)]
5866pub struct atom_firmware_info_v3_2 {
5867 pub table_header: atom_common_table_header,
5868 pub firmware_revision: u32,
5869 pub bootup_sclk_in10khz: u32,
5870 pub bootup_mclk_in10khz: u32,
5871 pub firmware_capability: u32,
5872 pub main_call_parser_entry: u32,
5873 pub bios_scratch_reg_startaddr: u32,
5874 pub bootup_vddc_mv: u16,
5875 pub bootup_vddci_mv: u16,
5876 pub bootup_mvddc_mv: u16,
5877 pub bootup_vddgfx_mv: u16,
5878 pub mem_module_id: u8,
5879 pub coolingsolution_id: u8,
5880 pub reserved1: [u8; 2usize],
5881 pub mc_baseaddr_high: u32,
5882 pub mc_baseaddr_low: u32,
5883 pub board_i2c_feature_id: u8,
5884 pub board_i2c_feature_gpio_id: u8,
5885 pub board_i2c_feature_slave_addr: u8,
5886 pub reserved3: u8,
5887 pub bootup_mvddq_mv: u16,
5888 pub bootup_mvpp_mv: u16,
5889 pub zfbstartaddrin16mb: u32,
5890 pub reserved2: [u32; 3usize],
5891}
5892#[repr(C, packed)]
5893#[derive(Debug, Copy, Clone)]
5894pub struct atom_firmware_info_v3_3 {
5895 pub table_header: atom_common_table_header,
5896 pub firmware_revision: u32,
5897 pub bootup_sclk_in10khz: u32,
5898 pub bootup_mclk_in10khz: u32,
5899 pub firmware_capability: u32,
5900 pub main_call_parser_entry: u32,
5901 pub bios_scratch_reg_startaddr: u32,
5902 pub bootup_vddc_mv: u16,
5903 pub bootup_vddci_mv: u16,
5904 pub bootup_mvddc_mv: u16,
5905 pub bootup_vddgfx_mv: u16,
5906 pub mem_module_id: u8,
5907 pub coolingsolution_id: u8,
5908 pub reserved1: [u8; 2usize],
5909 pub mc_baseaddr_high: u32,
5910 pub mc_baseaddr_low: u32,
5911 pub board_i2c_feature_id: u8,
5912 pub board_i2c_feature_gpio_id: u8,
5913 pub board_i2c_feature_slave_addr: u8,
5914 pub reserved3: u8,
5915 pub bootup_mvddq_mv: u16,
5916 pub bootup_mvpp_mv: u16,
5917 pub zfbstartaddrin16mb: u32,
5918 pub pplib_pptable_id: u32,
5919 pub reserved2: [u32; 2usize],
5920}
5921#[repr(C, packed)]
5922#[derive(Debug, Copy, Clone)]
5923pub struct atom_firmware_info_v3_4 {
5924 pub table_header: atom_common_table_header,
5925 pub firmware_revision: u32,
5926 pub bootup_sclk_in10khz: u32,
5927 pub bootup_mclk_in10khz: u32,
5928 pub firmware_capability: u32,
5929 pub main_call_parser_entry: u32,
5930 pub bios_scratch_reg_startaddr: u32,
5931 pub bootup_vddc_mv: u16,
5932 pub bootup_vddci_mv: u16,
5933 pub bootup_mvddc_mv: u16,
5934 pub bootup_vddgfx_mv: u16,
5935 pub mem_module_id: u8,
5936 pub coolingsolution_id: u8,
5937 pub reserved1: [u8; 2usize],
5938 pub mc_baseaddr_high: u32,
5939 pub mc_baseaddr_low: u32,
5940 pub board_i2c_feature_id: u8,
5941 pub board_i2c_feature_gpio_id: u8,
5942 pub board_i2c_feature_slave_addr: u8,
5943 pub ras_rom_i2c_slave_addr: u8,
5944 pub bootup_mvddq_mv: u16,
5945 pub bootup_mvpp_mv: u16,
5946 pub zfbstartaddrin16mb: u32,
5947 pub pplib_pptable_id: u32,
5948 pub mvdd_ratio: u32,
5949 pub hw_bootup_vddgfx_mv: u16,
5950 pub hw_bootup_vddc_mv: u16,
5951 pub hw_bootup_mvddc_mv: u16,
5952 pub hw_bootup_vddci_mv: u16,
5953 pub maco_pwrlimit_mw: u32,
5954 pub usb_pwrlimit_mw: u32,
5955 pub fw_reserved_size_in_kb: u32,
5956 pub pspbl_init_done_reg_addr: u32,
5957 pub pspbl_init_done_value: u32,
5958 pub pspbl_init_done_check_timeout: u32,
5959 pub reserved: [u32; 2usize],
5960}
5961#[repr(C, packed)]
5962#[derive(Debug, Copy, Clone)]
5963pub struct atom_firmware_info_v3_5 {
5964 pub table_header: atom_common_table_header,
5965 pub firmware_revision: u32,
5966 pub bootup_clk_reserved: [u32; 2usize],
5967 pub firmware_capability: u32,
5968 pub fw_protect_region_size_in_kb: u32,
5969 pub bios_scratch_reg_startaddr: u32,
5970 pub bootup_voltage_reserved: [u32; 2usize],
5971 pub mem_module_id: u8,
5972 pub coolingsolution_id: u8,
5973 pub hw_blt_mode: u8,
5974 pub reserved1: u8,
5975 pub mc_baseaddr_high: u32,
5976 pub mc_baseaddr_low: u32,
5977 pub board_i2c_feature_id: u8,
5978 pub board_i2c_feature_gpio_id: u8,
5979 pub board_i2c_feature_slave_addr: u8,
5980 pub ras_rom_i2c_slave_addr: u8,
5981 pub bootup_voltage_reserved1: u32,
5982 pub zfb_reserved: u32,
5983 pub pplib_pptable_id: u32,
5984 pub hw_voltage_reserved: [u32; 3usize],
5985 pub maco_pwrlimit_mw: u32,
5986 pub usb_pwrlimit_mw: u32,
5987 pub fw_reserved_size_in_kb: u32,
5988 pub pspbl_init_reserved: [u32; 3usize],
5989 pub spi_rom_size: u32,
5990 pub support_dev_in_objinfo: u16,
5991 pub disp_phy_tunning_size: u16,
5992 pub reserved: [u32; 16usize],
5993}
5994#[repr(C, packed)]
5995#[derive(Debug, Copy, Clone)]
5996pub struct lcd_info_v2_1 {
5997 pub table_header: atom_common_table_header,
5998 pub lcd_timing: atom_dtd_format,
5999 pub backlight_pwm: u16,
6000 pub special_handle_cap: u16,
6001 pub panel_misc: u16,
6002 pub lvds_max_slink_pclk: u16,
6003 pub lvds_ss_percentage: u16,
6004 pub lvds_ss_rate_10hz: u16,
6005 pub pwr_on_digon_to_de: u8,
6006 pub pwr_on_de_to_vary_bl: u8,
6007 pub pwr_down_vary_bloff_to_de: u8,
6008 pub pwr_down_de_to_digoff: u8,
6009 pub pwr_off_delay: u8,
6010 pub pwr_on_vary_bl_to_blon: u8,
6011 pub pwr_down_bloff_to_vary_bloff: u8,
6012 pub panel_bpc: u8,
6013 pub dpcd_edp_config_cap: u8,
6014 pub dpcd_max_link_rate: u8,
6015 pub dpcd_max_lane_count: u8,
6016 pub dpcd_max_downspread: u8,
6017 pub min_allowed_bl_level: u8,
6018 pub max_allowed_bl_level: u8,
6019 pub bootup_bl_level: u8,
6020 pub dplvdsrxid: u8,
6021 pub reserved1: [u32; 8usize],
6022}
6023pub const atom_lcd_info_panel_misc_ATOM_PANEL_MISC_FPDI: atom_lcd_info_panel_misc = 2;
6024pub type atom_lcd_info_panel_misc = ::core::ffi::c_uint;
6025pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_RX_DISABLE: atom_lcd_info_dptolvds_rx_id = 0;
6026pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_COMMON_ID: atom_lcd_info_dptolvds_rx_id = 1;
6027pub const atom_lcd_info_dptolvds_rx_id_eDP_TO_LVDS_REALTEK_ID: atom_lcd_info_dptolvds_rx_id = 2;
6028pub type atom_lcd_info_dptolvds_rx_id = ::core::ffi::c_uint;
6029#[repr(C, packed)]
6030#[derive(Debug, Copy, Clone)]
6031pub struct atom_gpio_pin_assignment {
6032 pub data_a_reg_index: u32,
6033 pub gpio_bitshift: u8,
6034 pub gpio_mask_bitshift: u8,
6035 pub gpio_id: u8,
6036 pub reserved: u8,
6037}
6038pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_LANE_MUX: atom_gpio_pin_assignment_gpio_id = 15;
6039pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_ENGINE_ID_MASK: atom_gpio_pin_assignment_gpio_id =
6040 112;
6041pub const atom_gpio_pin_assignment_gpio_id_I2C_HW_CAP: atom_gpio_pin_assignment_gpio_id = 128;
6042pub const atom_gpio_pin_assignment_gpio_id_PCIE_VDDC_CONTROL_GPIO_PINID:
6043 atom_gpio_pin_assignment_gpio_id = 56;
6044pub const atom_gpio_pin_assignment_gpio_id_PP_AC_DC_SWITCH_GPIO_PINID:
6045 atom_gpio_pin_assignment_gpio_id = 60;
6046pub const atom_gpio_pin_assignment_gpio_id_VDDC_VRHOT_GPIO_PINID: atom_gpio_pin_assignment_gpio_id =
6047 61;
6048pub const atom_gpio_pin_assignment_gpio_id_VDDC_PCC_GPIO_PINID: atom_gpio_pin_assignment_gpio_id =
6049 62;
6050pub const atom_gpio_pin_assignment_gpio_id_EFUSE_CUT_ENABLE_GPIO_PINID:
6051 atom_gpio_pin_assignment_gpio_id = 63;
6052pub const atom_gpio_pin_assignment_gpio_id_DRAM_SELF_REFRESH_GPIO_PINID:
6053 atom_gpio_pin_assignment_gpio_id = 64;
6054pub const atom_gpio_pin_assignment_gpio_id_THERMAL_INT_OUTPUT_GPIO_PINID:
6055 atom_gpio_pin_assignment_gpio_id = 65;
6056pub type atom_gpio_pin_assignment_gpio_id = ::core::ffi::c_uint;
6057#[repr(C)]
6058#[derive(Debug, Copy, Clone)]
6059pub struct atom_gpio_pin_lut_v2_1 {
6060 pub table_header: atom_common_table_header,
6061 pub gpio_pin: [atom_gpio_pin_assignment; 8usize],
6062}
6063#[repr(C, packed)]
6064#[derive(Debug, Copy, Clone)]
6065pub struct vram_usagebyfirmware_v2_1 {
6066 pub table_header: atom_common_table_header,
6067 pub start_address_in_kb: u32,
6068 pub used_by_firmware_in_kb: u16,
6069 pub used_by_driver_in_kb: u16,
6070}
6071#[repr(C, packed)]
6072#[derive(Debug, Copy, Clone)]
6073pub struct vram_usagebyfirmware_v2_2 {
6074 pub table_header: atom_common_table_header,
6075 pub fw_region_start_address_in_kb: u32,
6076 pub used_by_firmware_in_kb: u16,
6077 pub reserved: u16,
6078 pub driver_region0_start_address_in_kb: u32,
6079 pub used_by_driver_region0_in_kb: u32,
6080 pub reserved32: [u32; 7usize],
6081}
6082pub const atom_object_record_type_id_ATOM_I2C_RECORD_TYPE: atom_object_record_type_id = 1;
6083pub const atom_object_record_type_id_ATOM_HPD_INT_RECORD_TYPE: atom_object_record_type_id = 2;
6084pub const atom_object_record_type_id_ATOM_CONNECTOR_CAP_RECORD_TYPE: atom_object_record_type_id = 3;
6085pub const atom_object_record_type_id_ATOM_CONNECTOR_SPEED_UPTO: atom_object_record_type_id = 4;
6086pub const atom_object_record_type_id_ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE: atom_object_record_type_id =
6087 9;
6088pub const atom_object_record_type_id_ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE:
6089 atom_object_record_type_id = 16;
6090pub const atom_object_record_type_id_ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE:
6091 atom_object_record_type_id = 17;
6092pub const atom_object_record_type_id_ATOM_ENCODER_CAP_RECORD_TYPE: atom_object_record_type_id = 20;
6093pub const atom_object_record_type_id_ATOM_BRACKET_LAYOUT_RECORD_TYPE: atom_object_record_type_id =
6094 21;
6095pub const atom_object_record_type_id_ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE:
6096 atom_object_record_type_id = 22;
6097pub const atom_object_record_type_id_ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE:
6098 atom_object_record_type_id = 23;
6099pub const atom_object_record_type_id_ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE:
6100 atom_object_record_type_id = 25;
6101pub const atom_object_record_type_id_ATOM_RECORD_END_TYPE: atom_object_record_type_id = 255;
6102pub type atom_object_record_type_id = ::core::ffi::c_uint;
6103#[repr(C)]
6104#[derive(Debug, Copy, Clone)]
6105pub struct atom_common_record_header {
6106 pub record_type: u8,
6107 pub record_size: u8,
6108}
6109#[repr(C)]
6110#[derive(Debug, Copy, Clone)]
6111pub struct atom_i2c_record {
6112 pub record_header: atom_common_record_header,
6113 pub i2c_id: u8,
6114 pub i2c_slave_addr: u8,
6115}
6116#[repr(C)]
6117#[derive(Debug, Copy, Clone)]
6118pub struct atom_hpd_int_record {
6119 pub record_header: atom_common_record_header,
6120 pub pin_id: u8,
6121 pub plugin_pin_state: u8,
6122}
6123#[repr(C, packed)]
6124#[derive(Debug, Copy, Clone)]
6125pub struct atom_connector_caps_record {
6126 pub record_header: atom_common_record_header,
6127 pub connector_caps: u16,
6128}
6129#[repr(C, packed)]
6130#[derive(Debug, Copy, Clone)]
6131pub struct atom_connector_speed_record {
6132 pub record_header: atom_common_record_header,
6133 pub connector_max_speed: u32,
6134 pub reserved: u16,
6135}
6136pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR2: atom_encoder_caps_def = 1;
6137pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_MST_EN: atom_encoder_caps_def = 1;
6138pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR2_EN: atom_encoder_caps_def = 2;
6139pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN: atom_encoder_caps_def = 4;
6140pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_HBR3_EN: atom_encoder_caps_def = 8;
6141pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_DP2: atom_encoder_caps_def = 16;
6142pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR10_EN: atom_encoder_caps_def = 32;
6143pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN: atom_encoder_caps_def = 64;
6144pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_UHBR20_EN: atom_encoder_caps_def = 128;
6145pub const atom_encoder_caps_def_ATOM_ENCODER_CAP_RECORD_USB_C_TYPE: atom_encoder_caps_def = 256;
6146pub type atom_encoder_caps_def = ::core::ffi::c_uint;
6147#[repr(C, packed)]
6148#[derive(Debug, Copy, Clone)]
6149pub struct atom_encoder_caps_record {
6150 pub record_header: atom_common_record_header,
6151 pub encodercaps: u32,
6152}
6153pub const atom_connector_caps_def_ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY: atom_connector_caps_def = 1;
6154pub const atom_connector_caps_def_ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL: atom_connector_caps_def =
6155 2;
6156pub type atom_connector_caps_def = ::core::ffi::c_uint;
6157#[repr(C, packed)]
6158#[derive(Debug, Copy, Clone)]
6159pub struct atom_disp_connector_caps_record {
6160 pub record_header: atom_common_record_header,
6161 pub connectcaps: u32,
6162}
6163#[repr(C)]
6164#[derive(Debug, Copy, Clone)]
6165pub struct atom_gpio_pin_control_pair {
6166 pub gpio_id: u8,
6167 pub gpio_pinstate: u8,
6168}
6169#[repr(C)]
6170#[derive(Debug, Copy, Clone)]
6171pub struct atom_object_gpio_cntl_record {
6172 pub record_header: atom_common_record_header,
6173 pub flag: u8,
6174 pub number_of_pins: u8,
6175 pub gpio: [atom_gpio_pin_control_pair; 1usize],
6176}
6177pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_INPUT:
6178 atom_gpio_pin_control_pinstate_def = 0;
6179pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_OUTPUT:
6180 atom_gpio_pin_control_pinstate_def = 16;
6181pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_TYPE_HW_CONTROL:
6182 atom_gpio_pin_control_pinstate_def = 32;
6183pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_OUTPUT_STATE_MASK:
6184 atom_gpio_pin_control_pinstate_def = 1;
6185pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_OUTPUT_STATE_SHIFT:
6186 atom_gpio_pin_control_pinstate_def = 0;
6187pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_STATE_ACTIVE_LOW:
6188 atom_gpio_pin_control_pinstate_def = 0;
6189pub const atom_gpio_pin_control_pinstate_def_GPIO_PIN_STATE_ACTIVE_HIGH:
6190 atom_gpio_pin_control_pinstate_def = 1;
6191pub type atom_gpio_pin_control_pinstate_def = ::core::ffi::c_uint;
6192pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_REFCLK:
6193 atom_glsync_record_gpio_index_def = 0;
6194pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_HSYNC:
6195 atom_glsync_record_gpio_index_def = 1;
6196pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_VSYNC:
6197 atom_glsync_record_gpio_index_def = 2;
6198pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ:
6199 atom_glsync_record_gpio_index_def = 3;
6200pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT:
6201 atom_glsync_record_gpio_index_def = 4;
6202pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_INTERRUPT:
6203 atom_glsync_record_gpio_index_def = 5;
6204pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_V_RESET:
6205 atom_glsync_record_gpio_index_def = 6;
6206pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL:
6207 atom_glsync_record_gpio_index_def = 7;
6208pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL:
6209 atom_glsync_record_gpio_index_def = 8;
6210pub const atom_glsync_record_gpio_index_def_ATOM_GPIO_INDEX_GLSYNC_MAX:
6211 atom_glsync_record_gpio_index_def = 9;
6212pub type atom_glsync_record_gpio_index_def = ::core::ffi::c_uint;
6213#[repr(C)]
6214#[derive(Debug, Copy, Clone)]
6215pub struct atom_connector_hpdpin_lut_record {
6216 pub record_header: atom_common_record_header,
6217 pub hpd_pin_map: [u8; 8usize],
6218}
6219#[repr(C)]
6220#[derive(Debug, Copy, Clone)]
6221pub struct atom_connector_auxddc_lut_record {
6222 pub record_header: atom_common_record_header,
6223 pub aux_ddc_map: [u8; 8usize],
6224}
6225#[repr(C)]
6226#[derive(Debug, Copy, Clone)]
6227pub struct atom_connector_forced_tmds_cap_record {
6228 pub record_header: atom_common_record_header,
6229 pub maxtmdsclkrate_in2_5mhz: u8,
6230 pub reserved: u8,
6231}
6232#[repr(C, packed)]
6233#[derive(Debug, Copy, Clone)]
6234pub struct atom_connector_layout_info {
6235 pub connectorobjid: u16,
6236 pub connector_type: u8,
6237 pub position: u8,
6238}
6239pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_DVI_D:
6240 atom_connector_layout_info_connector_type_def = 1;
6241pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_HDMI:
6242 atom_connector_layout_info_connector_type_def = 4;
6243pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_DISPLAY_PORT:
6244 atom_connector_layout_info_connector_type_def = 5;
6245pub const atom_connector_layout_info_connector_type_def_CONNECTOR_TYPE_MINI_DISPLAY_PORT:
6246 atom_connector_layout_info_connector_type_def = 6;
6247pub type atom_connector_layout_info_connector_type_def = ::core::ffi::c_uint;
6248#[repr(C)]
6249#[derive(Debug, Copy, Clone)]
6250pub struct atom_bracket_layout_record {
6251 pub record_header: atom_common_record_header,
6252 pub bracketlen: u8,
6253 pub bracketwidth: u8,
6254 pub conn_num: u8,
6255 pub reserved: u8,
6256 pub conn_info: [atom_connector_layout_info; 1usize],
6257}
6258#[repr(C)]
6259#[derive(Debug, Copy, Clone)]
6260pub struct atom_bracket_layout_record_v2 {
6261 pub record_header: atom_common_record_header,
6262 pub bracketlen: u8,
6263 pub bracketwidth: u8,
6264 pub conn_num: u8,
6265 pub mini_type: u8,
6266 pub reserved1: u8,
6267 pub reserved2: u8,
6268}
6269pub const atom_connector_layout_info_mini_type_def_MINI_TYPE_NORMAL:
6270 atom_connector_layout_info_mini_type_def = 0;
6271pub const atom_connector_layout_info_mini_type_def_MINI_TYPE_MINI:
6272 atom_connector_layout_info_mini_type_def = 1;
6273pub type atom_connector_layout_info_mini_type_def = ::core::ffi::c_uint;
6274pub const atom_display_device_tag_def_ATOM_DISPLAY_LCD1_SUPPORT: atom_display_device_tag_def = 2;
6275pub const atom_display_device_tag_def_ATOM_DISPLAY_LCD2_SUPPORT: atom_display_device_tag_def = 32;
6276pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP1_SUPPORT: atom_display_device_tag_def = 8;
6277pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP2_SUPPORT: atom_display_device_tag_def = 128;
6278pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP3_SUPPORT: atom_display_device_tag_def = 512;
6279pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP4_SUPPORT: atom_display_device_tag_def = 1024;
6280pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP5_SUPPORT: atom_display_device_tag_def = 2048;
6281pub const atom_display_device_tag_def_ATOM_DISPLAY_DFP6_SUPPORT: atom_display_device_tag_def = 64;
6282pub const atom_display_device_tag_def_ATOM_DISPLAY_DFPx_SUPPORT: atom_display_device_tag_def = 3784;
6283pub type atom_display_device_tag_def = ::core::ffi::c_uint;
6284#[repr(C, packed)]
6285#[derive(Debug, Copy, Clone)]
6286pub struct atom_display_object_path_v2 {
6287 pub display_objid: u16,
6288 pub disp_recordoffset: u16,
6289 pub encoderobjid: u16,
6290 pub extencoderobjid: u16,
6291 pub encoder_recordoffset: u16,
6292 pub extencoder_recordoffset: u16,
6293 pub device_tag: u16,
6294 pub priority_id: u8,
6295 pub reserved: u8,
6296}
6297#[repr(C, packed)]
6298#[derive(Debug, Copy, Clone)]
6299pub struct atom_display_object_path_v3 {
6300 pub display_objid: u16,
6301 pub disp_recordoffset: u16,
6302 pub encoderobjid: u16,
6303 pub reserved1: u16,
6304 pub reserved2: u16,
6305 pub reserved3: u16,
6306 pub device_tag: u16,
6307 pub reserved4: u16,
6308}
6309#[repr(C, packed)]
6310#[derive(Debug, Copy, Clone)]
6311pub struct display_object_info_table_v1_4 {
6312 pub table_header: atom_common_table_header,
6313 pub supporteddevices: u16,
6314 pub number_of_path: u8,
6315 pub reserved: u8,
6316 pub display_path: [atom_display_object_path_v2; 8usize],
6317}
6318#[repr(C, packed)]
6319#[derive(Debug, Copy, Clone)]
6320pub struct display_object_info_table_v1_5 {
6321 pub table_header: atom_common_table_header,
6322 pub supporteddevices: u16,
6323 pub number_of_path: u8,
6324 pub reserved: u8,
6325 pub display_path: [atom_display_object_path_v3; 8usize],
6326}
6327#[repr(C, packed)]
6328#[derive(Debug, Copy, Clone)]
6329pub struct atom_display_controller_info_v4_1 {
6330 pub table_header: atom_common_table_header,
6331 pub display_caps: u32,
6332 pub bootup_dispclk_10khz: u32,
6333 pub dce_refclk_10khz: u16,
6334 pub i2c_engine_refclk_10khz: u16,
6335 pub dvi_ss_percentage: u16,
6336 pub dvi_ss_rate_10hz: u16,
6337 pub hdmi_ss_percentage: u16,
6338 pub hdmi_ss_rate_10hz: u16,
6339 pub dp_ss_percentage: u16,
6340 pub dp_ss_rate_10hz: u16,
6341 pub dvi_ss_mode: u8,
6342 pub hdmi_ss_mode: u8,
6343 pub dp_ss_mode: u8,
6344 pub ss_reserved: u8,
6345 pub hardcode_mode_num: u8,
6346 pub reserved1: [u8; 3usize],
6347 pub dpphy_refclk_10khz: u16,
6348 pub reserved2: u16,
6349 pub dceip_min_ver: u8,
6350 pub dceip_max_ver: u8,
6351 pub max_disp_pipe_num: u8,
6352 pub max_vbios_active_disp_pipe_num: u8,
6353 pub max_ppll_num: u8,
6354 pub max_disp_phy_num: u8,
6355 pub max_aux_pairs: u8,
6356 pub remotedisplayconfig: u8,
6357 pub reserved3: [u8; 8usize],
6358}
6359#[repr(C, packed)]
6360#[derive(Debug, Copy, Clone)]
6361pub struct atom_display_controller_info_v4_2 {
6362 pub table_header: atom_common_table_header,
6363 pub display_caps: u32,
6364 pub bootup_dispclk_10khz: u32,
6365 pub dce_refclk_10khz: u16,
6366 pub i2c_engine_refclk_10khz: u16,
6367 pub dvi_ss_percentage: u16,
6368 pub dvi_ss_rate_10hz: u16,
6369 pub hdmi_ss_percentage: u16,
6370 pub hdmi_ss_rate_10hz: u16,
6371 pub dp_ss_percentage: u16,
6372 pub dp_ss_rate_10hz: u16,
6373 pub dvi_ss_mode: u8,
6374 pub hdmi_ss_mode: u8,
6375 pub dp_ss_mode: u8,
6376 pub ss_reserved: u8,
6377 pub dfp_hardcode_mode_num: u8,
6378 pub dfp_hardcode_refreshrate: u8,
6379 pub vga_hardcode_mode_num: u8,
6380 pub vga_hardcode_refreshrate: u8,
6381 pub dpphy_refclk_10khz: u16,
6382 pub reserved2: u16,
6383 pub dcnip_min_ver: u8,
6384 pub dcnip_max_ver: u8,
6385 pub max_disp_pipe_num: u8,
6386 pub max_vbios_active_disp_pipe_num: u8,
6387 pub max_ppll_num: u8,
6388 pub max_disp_phy_num: u8,
6389 pub max_aux_pairs: u8,
6390 pub remotedisplayconfig: u8,
6391 pub reserved3: [u8; 8usize],
6392}
6393#[repr(C, packed)]
6394#[derive(Debug, Copy, Clone)]
6395pub struct atom_display_controller_info_v4_3 {
6396 pub table_header: atom_common_table_header,
6397 pub display_caps: u32,
6398 pub bootup_dispclk_10khz: u32,
6399 pub dce_refclk_10khz: u16,
6400 pub i2c_engine_refclk_10khz: u16,
6401 pub dvi_ss_percentage: u16,
6402 pub dvi_ss_rate_10hz: u16,
6403 pub hdmi_ss_percentage: u16,
6404 pub hdmi_ss_rate_10hz: u16,
6405 pub dp_ss_percentage: u16,
6406 pub dp_ss_rate_10hz: u16,
6407 pub dvi_ss_mode: u8,
6408 pub hdmi_ss_mode: u8,
6409 pub dp_ss_mode: u8,
6410 pub ss_reserved: u8,
6411 pub dfp_hardcode_mode_num: u8,
6412 pub dfp_hardcode_refreshrate: u8,
6413 pub vga_hardcode_mode_num: u8,
6414 pub vga_hardcode_refreshrate: u8,
6415 pub dpphy_refclk_10khz: u16,
6416 pub reserved2: u16,
6417 pub dcnip_min_ver: u8,
6418 pub dcnip_max_ver: u8,
6419 pub max_disp_pipe_num: u8,
6420 pub max_vbios_active_disp_pipe_num: u8,
6421 pub max_ppll_num: u8,
6422 pub max_disp_phy_num: u8,
6423 pub max_aux_pairs: u8,
6424 pub remotedisplayconfig: u8,
6425 pub reserved3: [u8; 8usize],
6426}
6427#[repr(C, packed)]
6428#[derive(Debug, Copy, Clone)]
6429pub struct atom_display_controller_info_v4_4 {
6430 pub table_header: atom_common_table_header,
6431 pub display_caps: u32,
6432 pub bootup_dispclk_10khz: u32,
6433 pub dce_refclk_10khz: u16,
6434 pub i2c_engine_refclk_10khz: u16,
6435 pub dvi_ss_percentage: u16,
6436 pub dvi_ss_rate_10hz: u16,
6437 pub hdmi_ss_percentage: u16,
6438 pub hdmi_ss_rate_10hz: u16,
6439 pub dp_ss_percentage: u16,
6440 pub dp_ss_rate_10hz: u16,
6441 pub dvi_ss_mode: u8,
6442 pub hdmi_ss_mode: u8,
6443 pub dp_ss_mode: u8,
6444 pub ss_reserved: u8,
6445 pub dfp_hardcode_mode_num: u8,
6446 pub dfp_hardcode_refreshrate: u8,
6447 pub vga_hardcode_mode_num: u8,
6448 pub vga_hardcode_refreshrate: u8,
6449 pub dpphy_refclk_10khz: u16,
6450 pub hw_chip_id: u16,
6451 pub dcnip_min_ver: u8,
6452 pub dcnip_max_ver: u8,
6453 pub max_disp_pipe_num: u8,
6454 pub max_vbios_active_disp_pipum: u8,
6455 pub max_ppll_num: u8,
6456 pub max_disp_phy_num: u8,
6457 pub max_aux_pairs: u8,
6458 pub remotedisplayconfig: u8,
6459 pub dispclk_pll_vco_freq: u32,
6460 pub dp_ref_clk_freq: u32,
6461 pub max_mclk_chg_lat: u32,
6462 pub max_sr_exit_lat: u32,
6463 pub max_sr_enter_exit_lat: u32,
6464 pub dc_golden_table_offset: u16,
6465 pub dc_golden_table_ver: u16,
6466 pub reserved3: [u32; 3usize],
6467}
6468#[repr(C, packed)]
6469#[derive(Debug, Copy, Clone)]
6470pub struct atom_dc_golden_table_v1 {
6471 pub aux_dphy_rx_control0_val: u32,
6472 pub aux_dphy_tx_control_val: u32,
6473 pub aux_dphy_rx_control1_val: u32,
6474 pub dc_gpio_aux_ctrl_0_val: u32,
6475 pub dc_gpio_aux_ctrl_1_val: u32,
6476 pub dc_gpio_aux_ctrl_2_val: u32,
6477 pub dc_gpio_aux_ctrl_3_val: u32,
6478 pub dc_gpio_aux_ctrl_4_val: u32,
6479 pub dc_gpio_aux_ctrl_5_val: u32,
6480 pub reserved: [u32; 23usize],
6481}
6482pub const dce_info_caps_def_DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED: dce_info_caps_def = 2;
6483pub const dce_info_caps_def_DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2: dce_info_caps_def = 4;
6484pub const dce_info_caps_def_DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING: dce_info_caps_def = 8;
6485pub const dce_info_caps_def_DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: dce_info_caps_def = 32;
6486pub const dce_info_caps_def_DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: dce_info_caps_def = 64;
6487pub type dce_info_caps_def = ::core::ffi::c_uint;
6488#[repr(C, packed)]
6489#[derive(Debug, Copy, Clone)]
6490pub struct atom_display_controller_info_v4_5 {
6491 pub table_header: atom_common_table_header,
6492 pub display_caps: u32,
6493 pub bootup_dispclk_10khz: u32,
6494 pub dce_refclk_10khz: u16,
6495 pub i2c_engine_refclk_10khz: u16,
6496 pub dvi_ss_percentage: u16,
6497 pub dvi_ss_rate_10hz: u16,
6498 pub hdmi_ss_percentage: u16,
6499 pub hdmi_ss_rate_10hz: u16,
6500 pub dp_ss_percentage: u16,
6501 pub dp_ss_rate_10hz: u16,
6502 pub dvi_ss_mode: u8,
6503 pub hdmi_ss_mode: u8,
6504 pub dp_ss_mode: u8,
6505 pub ss_reserved: u8,
6506 pub dfp_hardcode_mode_num: u8,
6507 pub dfp_hardcode_refreshrate: u8,
6508 pub vga_hardcode_mode_num: u8,
6509 pub vga_hardcode_refreshrate: u8,
6510 pub dpphy_refclk_10khz: u16,
6511 pub hw_chip_id: u16,
6512 pub dcnip_min_ver: u8,
6513 pub dcnip_max_ver: u8,
6514 pub max_disp_pipe_num: u8,
6515 pub max_vbios_active_disp_pipe_num: u8,
6516 pub max_ppll_num: u8,
6517 pub max_disp_phy_num: u8,
6518 pub max_aux_pairs: u8,
6519 pub remotedisplayconfig: u8,
6520 pub dispclk_pll_vco_freq: u32,
6521 pub dp_ref_clk_freq: u32,
6522 pub max_mclk_chg_lat: u32,
6523 pub max_sr_exit_lat: u32,
6524 pub max_sr_enter_exit_lat: u32,
6525 pub dc_golden_table_offset: u16,
6526 pub dc_golden_table_ver: u16,
6527 pub aux_dphy_rx_control0_val: u32,
6528 pub aux_dphy_tx_control_val: u32,
6529 pub aux_dphy_rx_control1_val: u32,
6530 pub dc_gpio_aux_ctrl_0_val: u32,
6531 pub dc_gpio_aux_ctrl_1_val: u32,
6532 pub dc_gpio_aux_ctrl_2_val: u32,
6533 pub dc_gpio_aux_ctrl_3_val: u32,
6534 pub dc_gpio_aux_ctrl_4_val: u32,
6535 pub dc_gpio_aux_ctrl_5_val: u32,
6536 pub reserved: [u32; 26usize],
6537}
6538#[repr(C, packed)]
6539#[derive(Debug, Copy, Clone)]
6540pub struct atom_ext_display_path {
6541 pub device_tag: u16,
6542 pub device_acpi_enum: u16,
6543 pub connectorobjid: u16,
6544 pub auxddclut_index: u8,
6545 pub hpdlut_index: u8,
6546 pub ext_encoder_objid: u16,
6547 pub channelmapping: u8,
6548 pub chpninvert: u8,
6549 pub caps: u16,
6550 pub reserved: u16,
6551}
6552pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE: ext_display_path_cap_def =
6553 1;
6554pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN: ext_display_path_cap_def =
6555 2;
6556pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK: ext_display_path_cap_def =
6557 124;
6558pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204:
6559 ext_display_path_cap_def = 4;
6560pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT:
6561 ext_display_path_cap_def = 8;
6562pub const ext_display_path_cap_def_EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175:
6563 ext_display_path_cap_def = 12;
6564pub type ext_display_path_cap_def = ::core::ffi::c_uint;
6565#[repr(C)]
6566#[derive(Debug, Copy, Clone)]
6567pub struct atom_external_display_connection_info {
6568 pub table_header: atom_common_table_header,
6569 pub guid: [u8; 16usize],
6570 pub path: [atom_ext_display_path; 7usize],
6571 pub checksum: u8,
6572 pub stereopinid: u8,
6573 pub remotedisplayconfig: u8,
6574 pub edptolvdsrxid: u8,
6575 pub fixdpvoltageswing: u8,
6576 pub reserved: [u8; 3usize],
6577}
6578#[repr(C, packed)]
6579#[derive(Debug, Copy, Clone)]
6580pub struct atom_camera_dphy_timing_param {
6581 pub profile_id: u8,
6582 pub param: u32,
6583}
6584#[repr(C, packed)]
6585#[derive(Debug, Copy, Clone)]
6586pub struct atom_camera_dphy_elec_param {
6587 pub param: [u16; 3usize],
6588}
6589#[repr(C)]
6590#[derive(Debug, Copy, Clone)]
6591pub struct atom_camera_module_info {
6592 pub module_id: u8,
6593 pub module_name: [u8; 8usize],
6594 pub timingparam: [atom_camera_dphy_timing_param; 6usize],
6595}
6596#[repr(C)]
6597#[derive(Debug, Copy, Clone)]
6598pub struct atom_camera_flashlight_info {
6599 pub flashlight_id: u8,
6600 pub name: [u8; 8usize],
6601}
6602#[repr(C, packed)]
6603#[derive(Debug, Copy, Clone)]
6604pub struct atom_camera_data {
6605 pub versionCode: u32,
6606 pub cameraInfo: [atom_camera_module_info; 3usize],
6607 pub flashInfo: atom_camera_flashlight_info,
6608 pub dphy_param: atom_camera_dphy_elec_param,
6609 pub crc_val: u32,
6610}
6611#[repr(C, packed)]
6612#[derive(Debug, Copy, Clone)]
6613pub struct atom_14nm_dpphy_dvihdmi_tuningset {
6614 pub max_symclk_in10khz: u32,
6615 pub encoder_mode: u8,
6616 pub phy_sel: u8,
6617 pub margindeemph: u16,
6618 pub deemph_6db_4: u8,
6619 pub boostadj: u8,
6620 pub tx_driver_fifty_ohms: u8,
6621 pub deemph_sel: u8,
6622}
6623#[repr(C, packed)]
6624#[derive(Debug, Copy, Clone)]
6625pub struct atom_14nm_dpphy_dp_setting {
6626 pub dp_vs_pemph_level: u8,
6627 pub margindeemph: u16,
6628 pub deemph_6db_4: u8,
6629 pub boostadj: u8,
6630}
6631#[repr(C, packed)]
6632#[derive(Debug, Copy, Clone)]
6633pub struct atom_14nm_dpphy_dp_tuningset {
6634 pub phy_sel: u8,
6635 pub version: u8,
6636 pub table_size: u16,
6637 pub reserved: u16,
6638 pub dptuning: [atom_14nm_dpphy_dp_setting; 10usize],
6639}
6640#[repr(C, packed)]
6641#[derive(Debug, Copy, Clone)]
6642pub struct atom_14nm_dig_transmitter_info_header_v4_0 {
6643 pub table_header: atom_common_table_header,
6644 pub pcie_phy_tmds_hdmi_macro_settings_offset: u16,
6645 pub uniphy_vs_emph_lookup_table_offset: u16,
6646 pub uniphy_xbar_settings_table_offset: u16,
6647}
6648#[repr(C, packed)]
6649#[derive(Debug, Copy, Clone)]
6650pub struct atom_14nm_combphy_tmds_vs_set {
6651 pub sym_clk: u8,
6652 pub dig_mode: u8,
6653 pub phy_sel: u8,
6654 pub common_mar_deemph_nom__margin_deemph_val: u16,
6655 pub common_seldeemph60__deemph_6db_4_val: u8,
6656 pub cmd_bus_global_for_tx_lane0__boostadj_val: u8,
6657 pub common_zcalcode_ctrl__tx_driver_fifty_ohms_val: u8,
6658 pub margin_deemph_lane0__deemph_sel_val: u8,
6659}
6660#[repr(C, packed)]
6661#[derive(Debug, Copy, Clone)]
6662pub struct atom_DCN_dpphy_dvihdmi_tuningset {
6663 pub max_symclk_in10khz: u32,
6664 pub encoder_mode: u8,
6665 pub phy_sel: u8,
6666 pub tx_eq_main: u8,
6667 pub tx_eq_pre: u8,
6668 pub tx_eq_post: u8,
6669 pub reserved1: u8,
6670 pub tx_vboost_lvl: u8,
6671 pub reserved2: u8,
6672}
6673#[repr(C)]
6674#[derive(Debug, Copy, Clone)]
6675pub struct atom_DCN_dpphy_dp_setting {
6676 pub dp_vs_pemph_level: u8,
6677 pub tx_eq_main: u8,
6678 pub tx_eq_pre: u8,
6679 pub tx_eq_post: u8,
6680 pub tx_vboost_lvl: u8,
6681}
6682#[repr(C, packed)]
6683#[derive(Debug, Copy, Clone)]
6684pub struct atom_DCN_dpphy_dp_tuningset {
6685 pub phy_sel: u8,
6686 pub version: u8,
6687 pub table_size: u16,
6688 pub reserved: u16,
6689 pub dptunings: [atom_DCN_dpphy_dp_setting; 10usize],
6690}
6691#[repr(C)]
6692#[derive(Debug, Copy, Clone)]
6693pub struct atom_i2c_reg_info {
6694 pub ucI2cRegIndex: u8,
6695 pub ucI2cRegVal: u8,
6696}
6697#[repr(C)]
6698#[derive(Debug, Copy, Clone)]
6699pub struct atom_hdmi_retimer_redriver_set {
6700 pub HdmiSlvAddr: u8,
6701 pub HdmiRegNum: u8,
6702 pub Hdmi6GRegNum: u8,
6703 pub HdmiRegSetting: [atom_i2c_reg_info; 9usize],
6704 pub Hdmi6GhzRegSetting: [atom_i2c_reg_info; 3usize],
6705}
6706#[repr(C, packed)]
6707#[derive(Debug, Copy, Clone)]
6708pub struct atom_integrated_system_info_v1_11 {
6709 pub table_header: atom_common_table_header,
6710 pub vbios_misc: u32,
6711 pub gpucapinfo: u32,
6712 pub system_config: u32,
6713 pub cpucapinfo: u32,
6714 pub gpuclk_ss_percentage: u16,
6715 pub gpuclk_ss_type: u16,
6716 pub lvds_ss_percentage: u16,
6717 pub lvds_ss_rate_10hz: u16,
6718 pub hdmi_ss_percentage: u16,
6719 pub hdmi_ss_rate_10hz: u16,
6720 pub dvi_ss_percentage: u16,
6721 pub dvi_ss_rate_10hz: u16,
6722 pub dpphy_override: u16,
6723 pub lvds_misc: u16,
6724 pub backlight_pwm_hz: u16,
6725 pub memorytype: u8,
6726 pub umachannelnumber: u8,
6727 pub pwr_on_digon_to_de: u8,
6728 pub pwr_on_de_to_vary_bl: u8,
6729 pub pwr_down_vary_bloff_to_de: u8,
6730 pub pwr_down_de_to_digoff: u8,
6731 pub pwr_off_delay: u8,
6732 pub pwr_on_vary_bl_to_blon: u8,
6733 pub pwr_down_bloff_to_vary_bloff: u8,
6734 pub min_allowed_bl_level: u8,
6735 pub htc_hyst_limit: u8,
6736 pub htc_tmp_limit: u8,
6737 pub reserved1: u8,
6738 pub reserved2: u8,
6739 pub extdispconninfo: atom_external_display_connection_info,
6740 pub dvi_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
6741 pub hdmi_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
6742 pub hdmi6g_tuningset: atom_14nm_dpphy_dvihdmi_tuningset,
6743 pub dp_tuningset: atom_14nm_dpphy_dp_tuningset,
6744 pub dp_hbr3_tuningset: atom_14nm_dpphy_dp_tuningset,
6745 pub camera_info: atom_camera_data,
6746 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
6747 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
6748 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
6749 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
6750 pub dp_hbr_tuningset: atom_14nm_dpphy_dp_tuningset,
6751 pub dp_hbr2_tuningset: atom_14nm_dpphy_dp_tuningset,
6752 pub edp_tuningset: atom_14nm_dpphy_dp_tuningset,
6753 pub reserved: [u32; 66usize],
6754}
6755#[repr(C, packed)]
6756#[derive(Debug, Copy, Clone)]
6757pub struct atom_integrated_system_info_v1_12 {
6758 pub table_header: atom_common_table_header,
6759 pub vbios_misc: u32,
6760 pub gpucapinfo: u32,
6761 pub system_config: u32,
6762 pub cpucapinfo: u32,
6763 pub gpuclk_ss_percentage: u16,
6764 pub gpuclk_ss_type: u16,
6765 pub lvds_ss_percentage: u16,
6766 pub lvds_ss_rate_10hz: u16,
6767 pub hdmi_ss_percentage: u16,
6768 pub hdmi_ss_rate_10hz: u16,
6769 pub dvi_ss_percentage: u16,
6770 pub dvi_ss_rate_10hz: u16,
6771 pub dpphy_override: u16,
6772 pub lvds_misc: u16,
6773 pub backlight_pwm_hz: u16,
6774 pub memorytype: u8,
6775 pub umachannelnumber: u8,
6776 pub pwr_on_digon_to_de: u8,
6777 pub pwr_on_de_to_vary_bl: u8,
6778 pub pwr_down_vary_bloff_to_de: u8,
6779 pub pwr_down_de_to_digoff: u8,
6780 pub pwr_off_delay: u8,
6781 pub pwr_on_vary_bl_to_blon: u8,
6782 pub pwr_down_bloff_to_vary_bloff: u8,
6783 pub min_allowed_bl_level: u8,
6784 pub htc_hyst_limit: u8,
6785 pub htc_tmp_limit: u8,
6786 pub reserved1: u8,
6787 pub reserved2: u8,
6788 pub extdispconninfo: atom_external_display_connection_info,
6789 pub TMDS_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6790 pub hdmiCLK5_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6791 pub hdmiCLK8_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6792 pub rbr_tuningset: atom_DCN_dpphy_dp_tuningset,
6793 pub hbr3_tuningset: atom_DCN_dpphy_dp_tuningset,
6794 pub camera_info: atom_camera_data,
6795 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
6796 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
6797 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
6798 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
6799 pub hbr_tuningset: atom_DCN_dpphy_dp_tuningset,
6800 pub hbr2_tuningset: atom_DCN_dpphy_dp_tuningset,
6801 pub edp_tunings: atom_DCN_dpphy_dp_tuningset,
6802 pub hdmiCLK6_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6803 pub reserved: [u32; 63usize],
6804}
6805#[repr(C, packed)]
6806#[derive(Debug, Copy, Clone)]
6807pub struct edp_info_table {
6808 pub edp_backlight_pwm_hz: u16,
6809 pub edp_ss_percentage: u16,
6810 pub edp_ss_rate_10hz: u16,
6811 pub reserved1: u16,
6812 pub reserved2: u32,
6813 pub edp_pwr_on_off_delay: u8,
6814 pub edp_pwr_on_vary_bl_to_blon: u8,
6815 pub edp_pwr_down_bloff_to_vary_bloff: u8,
6816 pub edp_panel_bpc: u8,
6817 pub edp_bootup_bl_level: u8,
6818 pub reserved3: [u8; 3usize],
6819 pub reserved4: [u32; 3usize],
6820}
6821#[repr(C, packed)]
6822#[derive(Debug, Copy, Clone)]
6823pub struct atom_integrated_system_info_v2_1 {
6824 pub table_header: atom_common_table_header,
6825 pub vbios_misc: u32,
6826 pub gpucapinfo: u32,
6827 pub system_config: u32,
6828 pub cpucapinfo: u32,
6829 pub gpuclk_ss_percentage: u16,
6830 pub gpuclk_ss_type: u16,
6831 pub dpphy_override: u16,
6832 pub memorytype: u8,
6833 pub umachannelnumber: u8,
6834 pub htc_hyst_limit: u8,
6835 pub htc_tmp_limit: u8,
6836 pub reserved1: u8,
6837 pub reserved2: u8,
6838 pub edp1_info: edp_info_table,
6839 pub edp2_info: edp_info_table,
6840 pub reserved3: [u32; 8usize],
6841 pub extdispconninfo: atom_external_display_connection_info,
6842 pub TMDS_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6843 pub hdmiCLK5_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6844 pub hdmiCLK6_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6845 pub hdmiCLK8_tuningset: atom_DCN_dpphy_dvihdmi_tuningset,
6846 pub reserved4: [u32; 6usize],
6847 pub rbr_tuningset: atom_DCN_dpphy_dp_tuningset,
6848 pub hbr_tuningset: atom_DCN_dpphy_dp_tuningset,
6849 pub hbr2_tuningset: atom_DCN_dpphy_dp_tuningset,
6850 pub hbr3_tuningset: atom_DCN_dpphy_dp_tuningset,
6851 pub edp_tunings: atom_DCN_dpphy_dp_tuningset,
6852 pub reserved5: [u32; 28usize],
6853 pub dp0_retimer_set: atom_hdmi_retimer_redriver_set,
6854 pub dp1_retimer_set: atom_hdmi_retimer_redriver_set,
6855 pub dp2_retimer_set: atom_hdmi_retimer_redriver_set,
6856 pub dp3_retimer_set: atom_hdmi_retimer_redriver_set,
6857 pub reserved6: [u32; 30usize],
6858 pub reserved7: [u32; 32usize],
6859}
6860#[repr(C, packed)]
6861#[derive(Debug, Copy, Clone)]
6862pub struct atom_n6_display_phy_tuning_set {
6863 pub display_signal_type: u8,
6864 pub phy_sel: u8,
6865 pub preset_level: u8,
6866 pub reserved1: u8,
6867 pub reserved2: u32,
6868 pub speed_upto: u32,
6869 pub tx_vboost_level: u8,
6870 pub tx_vreg_v2i: u8,
6871 pub tx_vregdrv_byp: u8,
6872 pub tx_term_cntl: u8,
6873 pub tx_peak_level: u8,
6874 pub tx_slew_en: u8,
6875 pub tx_eq_pre: u8,
6876 pub tx_eq_main: u8,
6877 pub tx_eq_post: u8,
6878 pub tx_en_inv_pre: u8,
6879 pub tx_en_inv_post: u8,
6880 pub reserved3: u8,
6881 pub reserved4: u32,
6882 pub reserved5: u32,
6883 pub reserved6: u32,
6884}
6885#[repr(C)]
6886#[derive(Debug, Copy, Clone)]
6887pub struct atom_display_phy_tuning_info {
6888 pub table_header: atom_common_table_header,
6889 pub disp_phy_tuning: [atom_n6_display_phy_tuning_set; 1usize],
6890}
6891#[repr(C, packed)]
6892#[derive(Debug, Copy, Clone)]
6893pub struct atom_integrated_system_info_v2_2 {
6894 pub table_header: atom_common_table_header,
6895 pub vbios_misc: u32,
6896 pub gpucapinfo: u32,
6897 pub system_config: u32,
6898 pub cpucapinfo: u32,
6899 pub gpuclk_ss_percentage: u16,
6900 pub gpuclk_ss_type: u16,
6901 pub dpphy_override: u16,
6902 pub memorytype: u8,
6903 pub umachannelnumber: u8,
6904 pub htc_hyst_limit: u8,
6905 pub htc_tmp_limit: u8,
6906 pub reserved1: u8,
6907 pub reserved2: u8,
6908 pub edp1_info: edp_info_table,
6909 pub edp2_info: edp_info_table,
6910 pub reserved3: [u32; 8usize],
6911 pub extdispconninfo: atom_external_display_connection_info,
6912 pub reserved4: [u32; 189usize],
6913}
6914pub const atom_system_vbiosmisc_def_INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT:
6915 atom_system_vbiosmisc_def = 1;
6916pub type atom_system_vbiosmisc_def = ::core::ffi::c_uint;
6917pub const atom_system_gpucapinf_def_SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS: atom_system_gpucapinf_def =
6918 16;
6919pub type atom_system_gpucapinf_def = ::core::ffi::c_uint;
6920pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DVI_TUNINGSET:
6921 atom_sysinfo_dpphy_override_def = 1;
6922pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_HDMI_TUNINGSET:
6923 atom_sysinfo_dpphy_override_def = 2;
6924pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_HDMI6G_TUNINGSET:
6925 atom_sysinfo_dpphy_override_def = 4;
6926pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DP_TUNINGSET:
6927 atom_sysinfo_dpphy_override_def = 8;
6928pub const atom_sysinfo_dpphy_override_def_ATOM_ENABLE_DP_HBR3_TUNINGSET:
6929 atom_sysinfo_dpphy_override_def = 16;
6930pub type atom_sysinfo_dpphy_override_def = ::core::ffi::c_uint;
6931pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_888_FPDI_MODE:
6932 atom_sys_info_lvds_misc_def = 1;
6933pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_888_BPC_MODE: atom_sys_info_lvds_misc_def =
6934 4;
6935pub const atom_sys_info_lvds_misc_def_SYS_INFO_LVDS_MISC_OVERRIDE_EN: atom_sys_info_lvds_misc_def =
6936 8;
6937pub type atom_sys_info_lvds_misc_def = ::core::ffi::c_uint;
6938#[doc = "< Assign 01 to Other"]
6939pub const atom_dmi_t17_mem_type_def_OtherMemType: atom_dmi_t17_mem_type_def = 1;
6940#[doc = "< Assign 02 to Unknown"]
6941pub const atom_dmi_t17_mem_type_def_UnknownMemType: atom_dmi_t17_mem_type_def = 2;
6942#[doc = "< Assign 03 to DRAM"]
6943pub const atom_dmi_t17_mem_type_def_DramMemType: atom_dmi_t17_mem_type_def = 3;
6944#[doc = "< Assign 04 to EDRAM"]
6945pub const atom_dmi_t17_mem_type_def_EdramMemType: atom_dmi_t17_mem_type_def = 4;
6946#[doc = "< Assign 05 to VRAM"]
6947pub const atom_dmi_t17_mem_type_def_VramMemType: atom_dmi_t17_mem_type_def = 5;
6948#[doc = "< Assign 06 to SRAM"]
6949pub const atom_dmi_t17_mem_type_def_SramMemType: atom_dmi_t17_mem_type_def = 6;
6950#[doc = "< Assign 07 to RAM"]
6951pub const atom_dmi_t17_mem_type_def_RamMemType: atom_dmi_t17_mem_type_def = 7;
6952#[doc = "< Assign 08 to ROM"]
6953pub const atom_dmi_t17_mem_type_def_RomMemType: atom_dmi_t17_mem_type_def = 8;
6954#[doc = "< Assign 09 to Flash"]
6955pub const atom_dmi_t17_mem_type_def_FlashMemType: atom_dmi_t17_mem_type_def = 9;
6956#[doc = "< Assign 10 to EEPROM"]
6957pub const atom_dmi_t17_mem_type_def_EepromMemType: atom_dmi_t17_mem_type_def = 10;
6958#[doc = "< Assign 11 to FEPROM"]
6959pub const atom_dmi_t17_mem_type_def_FepromMemType: atom_dmi_t17_mem_type_def = 11;
6960#[doc = "< Assign 12 to EPROM"]
6961pub const atom_dmi_t17_mem_type_def_EpromMemType: atom_dmi_t17_mem_type_def = 12;
6962#[doc = "< Assign 13 to CDRAM"]
6963pub const atom_dmi_t17_mem_type_def_CdramMemType: atom_dmi_t17_mem_type_def = 13;
6964#[doc = "< Assign 14 to 3DRAM"]
6965pub const atom_dmi_t17_mem_type_def_ThreeDramMemType: atom_dmi_t17_mem_type_def = 14;
6966#[doc = "< Assign 15 to SDRAM"]
6967pub const atom_dmi_t17_mem_type_def_SdramMemType: atom_dmi_t17_mem_type_def = 15;
6968#[doc = "< Assign 16 to SGRAM"]
6969pub const atom_dmi_t17_mem_type_def_SgramMemType: atom_dmi_t17_mem_type_def = 16;
6970#[doc = "< Assign 17 to RDRAM"]
6971pub const atom_dmi_t17_mem_type_def_RdramMemType: atom_dmi_t17_mem_type_def = 17;
6972#[doc = "< Assign 18 to DDR"]
6973pub const atom_dmi_t17_mem_type_def_DdrMemType: atom_dmi_t17_mem_type_def = 18;
6974#[doc = "< Assign 19 to DDR2"]
6975pub const atom_dmi_t17_mem_type_def_Ddr2MemType: atom_dmi_t17_mem_type_def = 19;
6976#[doc = "< Assign 20 to DDR2 FB-DIMM"]
6977pub const atom_dmi_t17_mem_type_def_Ddr2FbdimmMemType: atom_dmi_t17_mem_type_def = 20;
6978#[doc = "< Assign 24 to DDR3"]
6979pub const atom_dmi_t17_mem_type_def_Ddr3MemType: atom_dmi_t17_mem_type_def = 24;
6980#[doc = "< Assign 25 to FBD2"]
6981pub const atom_dmi_t17_mem_type_def_Fbd2MemType: atom_dmi_t17_mem_type_def = 25;
6982#[doc = "< Assign 26 to DDR4"]
6983pub const atom_dmi_t17_mem_type_def_Ddr4MemType: atom_dmi_t17_mem_type_def = 26;
6984#[doc = "< Assign 27 to LPDDR"]
6985pub const atom_dmi_t17_mem_type_def_LpDdrMemType: atom_dmi_t17_mem_type_def = 27;
6986#[doc = "< Assign 28 to LPDDR2"]
6987pub const atom_dmi_t17_mem_type_def_LpDdr2MemType: atom_dmi_t17_mem_type_def = 28;
6988#[doc = "< Assign 29 to LPDDR3"]
6989pub const atom_dmi_t17_mem_type_def_LpDdr3MemType: atom_dmi_t17_mem_type_def = 29;
6990#[doc = "< Assign 30 to LPDDR4"]
6991pub const atom_dmi_t17_mem_type_def_LpDdr4MemType: atom_dmi_t17_mem_type_def = 30;
6992#[doc = "< Assign 31 to GDDR6"]
6993pub const atom_dmi_t17_mem_type_def_GDdr6MemType: atom_dmi_t17_mem_type_def = 31;
6994#[doc = "< Assign 32 to HBM"]
6995pub const atom_dmi_t17_mem_type_def_HbmMemType: atom_dmi_t17_mem_type_def = 32;
6996#[doc = "< Assign 33 to HBM2"]
6997pub const atom_dmi_t17_mem_type_def_Hbm2MemType: atom_dmi_t17_mem_type_def = 33;
6998#[doc = "< Assign 34 to DDR5"]
6999pub const atom_dmi_t17_mem_type_def_Ddr5MemType: atom_dmi_t17_mem_type_def = 34;
7000#[doc = "< Assign 35 to LPDDR5"]
7001pub const atom_dmi_t17_mem_type_def_LpDdr5MemType: atom_dmi_t17_mem_type_def = 35;
7002pub type atom_dmi_t17_mem_type_def = ::core::ffi::c_uint;
7003#[repr(C, packed)]
7004#[derive(Debug, Copy, Clone)]
7005pub struct atom_fusion_system_info_v4 {
7006 pub sysinfo: atom_integrated_system_info_v1_11,
7007 pub powerplayinfo: [u32; 256usize],
7008}
7009#[repr(C, packed)]
7010#[derive(Debug, Copy, Clone)]
7011pub struct atom_gfx_info_v2_2 {
7012 pub table_header: atom_common_table_header,
7013 pub gfxip_min_ver: u8,
7014 pub gfxip_max_ver: u8,
7015 pub max_shader_engines: u8,
7016 pub max_tile_pipes: u8,
7017 pub max_cu_per_sh: u8,
7018 pub max_sh_per_se: u8,
7019 pub max_backends_per_se: u8,
7020 pub max_texture_channel_caches: u8,
7021 pub regaddr_cp_dma_src_addr: u32,
7022 pub regaddr_cp_dma_src_addr_hi: u32,
7023 pub regaddr_cp_dma_dst_addr: u32,
7024 pub regaddr_cp_dma_dst_addr_hi: u32,
7025 pub regaddr_cp_dma_command: u32,
7026 pub regaddr_cp_status: u32,
7027 pub regaddr_rlc_gpu_clock_32: u32,
7028 pub rlc_gpu_timer_refclk: u32,
7029}
7030#[repr(C, packed)]
7031#[derive(Debug, Copy, Clone)]
7032pub struct atom_gfx_info_v2_3 {
7033 pub table_header: atom_common_table_header,
7034 pub gfxip_min_ver: u8,
7035 pub gfxip_max_ver: u8,
7036 pub max_shader_engines: u8,
7037 pub max_tile_pipes: u8,
7038 pub max_cu_per_sh: u8,
7039 pub max_sh_per_se: u8,
7040 pub max_backends_per_se: u8,
7041 pub max_texture_channel_caches: u8,
7042 pub regaddr_cp_dma_src_addr: u32,
7043 pub regaddr_cp_dma_src_addr_hi: u32,
7044 pub regaddr_cp_dma_dst_addr: u32,
7045 pub regaddr_cp_dma_dst_addr_hi: u32,
7046 pub regaddr_cp_dma_command: u32,
7047 pub regaddr_cp_status: u32,
7048 pub regaddr_rlc_gpu_clock_32: u32,
7049 pub rlc_gpu_timer_refclk: u32,
7050 pub active_cu_per_sh: u8,
7051 pub active_rb_per_se: u8,
7052 pub gcgoldenoffset: u16,
7053 pub rm21_sram_vmin_value: u32,
7054}
7055#[repr(C, packed)]
7056#[derive(Debug, Copy, Clone)]
7057pub struct atom_gfx_info_v2_4 {
7058 pub table_header: atom_common_table_header,
7059 pub gfxip_min_ver: u8,
7060 pub gfxip_max_ver: u8,
7061 pub max_shader_engines: u8,
7062 pub reserved: u8,
7063 pub max_cu_per_sh: u8,
7064 pub max_sh_per_se: u8,
7065 pub max_backends_per_se: u8,
7066 pub max_texture_channel_caches: u8,
7067 pub regaddr_cp_dma_src_addr: u32,
7068 pub regaddr_cp_dma_src_addr_hi: u32,
7069 pub regaddr_cp_dma_dst_addr: u32,
7070 pub regaddr_cp_dma_dst_addr_hi: u32,
7071 pub regaddr_cp_dma_command: u32,
7072 pub regaddr_cp_status: u32,
7073 pub regaddr_rlc_gpu_clock_32: u32,
7074 pub rlc_gpu_timer_refclk: u32,
7075 pub active_cu_per_sh: u8,
7076 pub active_rb_per_se: u8,
7077 pub gcgoldenoffset: u16,
7078 pub gc_num_gprs: u16,
7079 pub gc_gsprim_buff_depth: u16,
7080 pub gc_parameter_cache_depth: u16,
7081 pub gc_wave_size: u16,
7082 pub gc_max_waves_per_simd: u16,
7083 pub gc_lds_size: u16,
7084 pub gc_num_max_gs_thds: u8,
7085 pub gc_gs_table_depth: u8,
7086 pub gc_double_offchip_lds_buffer: u8,
7087 pub gc_max_scratch_slots_per_cu: u8,
7088 pub sram_rm_fuses_val: u32,
7089 pub sram_custom_rm_fuses_val: u32,
7090}
7091#[repr(C, packed)]
7092#[derive(Debug, Copy, Clone)]
7093pub struct atom_gfx_info_v2_7 {
7094 pub table_header: atom_common_table_header,
7095 pub gfxip_min_ver: u8,
7096 pub gfxip_max_ver: u8,
7097 pub max_shader_engines: u8,
7098 pub reserved: u8,
7099 pub max_cu_per_sh: u8,
7100 pub max_sh_per_se: u8,
7101 pub max_backends_per_se: u8,
7102 pub max_texture_channel_caches: u8,
7103 pub regaddr_cp_dma_src_addr: u32,
7104 pub regaddr_cp_dma_src_addr_hi: u32,
7105 pub regaddr_cp_dma_dst_addr: u32,
7106 pub regaddr_cp_dma_dst_addr_hi: u32,
7107 pub regaddr_cp_dma_command: u32,
7108 pub regaddr_cp_status: u32,
7109 pub regaddr_rlc_gpu_clock_32: u32,
7110 pub rlc_gpu_timer_refclk: u32,
7111 pub active_cu_per_sh: u8,
7112 pub active_rb_per_se: u8,
7113 pub gcgoldenoffset: u16,
7114 pub gc_num_gprs: u16,
7115 pub gc_gsprim_buff_depth: u16,
7116 pub gc_parameter_cache_depth: u16,
7117 pub gc_wave_size: u16,
7118 pub gc_max_waves_per_simd: u16,
7119 pub gc_lds_size: u16,
7120 pub gc_num_max_gs_thds: u8,
7121 pub gc_gs_table_depth: u8,
7122 pub gc_double_offchip_lds_buffer: u8,
7123 pub gc_max_scratch_slots_per_cu: u8,
7124 pub sram_rm_fuses_val: u32,
7125 pub sram_custom_rm_fuses_val: u32,
7126 pub cut_cu: u8,
7127 pub active_cu_total: u8,
7128 pub cu_reserved: [u8; 2usize],
7129 pub gc_config: u32,
7130 pub inactive_cu_per_se: [u8; 8usize],
7131 pub reserved2: [u32; 6usize],
7132}
7133#[repr(C, packed)]
7134#[derive(Debug, Copy, Clone)]
7135pub struct atom_gfx_info_v3_0 {
7136 pub table_header: atom_common_table_header,
7137 pub gfxip_min_ver: u8,
7138 pub gfxip_max_ver: u8,
7139 pub max_shader_engines: u8,
7140 pub max_tile_pipes: u8,
7141 pub max_cu_per_sh: u8,
7142 pub max_sh_per_se: u8,
7143 pub max_backends_per_se: u8,
7144 pub max_texture_channel_caches: u8,
7145 pub regaddr_lsdma_queue0_rb_rptr: u32,
7146 pub regaddr_lsdma_queue0_rb_rptr_hi: u32,
7147 pub regaddr_lsdma_queue0_rb_wptr: u32,
7148 pub regaddr_lsdma_queue0_rb_wptr_hi: u32,
7149 pub regaddr_lsdma_command: u32,
7150 pub regaddr_lsdma_status: u32,
7151 pub regaddr_golden_tsc_count_lower: u32,
7152 pub golden_tsc_count_lower_refclk: u32,
7153 pub active_wgp_per_se: u8,
7154 pub active_rb_per_se: u8,
7155 pub active_se: u8,
7156 pub reserved1: u8,
7157 pub sram_rm_fuses_val: u32,
7158 pub sram_custom_rm_fuses_val: u32,
7159 pub inactive_sa_mask: u32,
7160 pub gc_config: u32,
7161 pub inactive_wgp: [u8; 16usize],
7162 pub inactive_rb: [u8; 16usize],
7163 pub gdfll_as_wait_ctrl_val: u32,
7164 pub gdfll_as_step_ctrl_val: u32,
7165 pub reserved: [u32; 8usize],
7166}
7167#[repr(C, packed)]
7168#[derive(Debug, Copy, Clone)]
7169pub struct atom_smu_info_v3_1 {
7170 pub table_header: atom_common_table_header,
7171 pub smuip_min_ver: u8,
7172 pub smuip_max_ver: u8,
7173 pub smu_rsd1: u8,
7174 pub gpuclk_ss_mode: u8,
7175 pub sclk_ss_percentage: u16,
7176 pub sclk_ss_rate_10hz: u16,
7177 pub gpuclk_ss_percentage: u16,
7178 pub gpuclk_ss_rate_10hz: u16,
7179 pub core_refclk_10khz: u32,
7180 pub ac_dc_gpio_bit: u8,
7181 pub ac_dc_polarity: u8,
7182 pub vr0hot_gpio_bit: u8,
7183 pub vr0hot_polarity: u8,
7184 pub vr1hot_gpio_bit: u8,
7185 pub vr1hot_polarity: u8,
7186 pub fw_ctf_gpio_bit: u8,
7187 pub fw_ctf_polarity: u8,
7188}
7189#[repr(C, packed)]
7190#[derive(Debug, Copy, Clone)]
7191pub struct atom_smu_info_v3_2 {
7192 pub table_header: atom_common_table_header,
7193 pub smuip_min_ver: u8,
7194 pub smuip_max_ver: u8,
7195 pub smu_rsd1: u8,
7196 pub gpuclk_ss_mode: u8,
7197 pub sclk_ss_percentage: u16,
7198 pub sclk_ss_rate_10hz: u16,
7199 pub gpuclk_ss_percentage: u16,
7200 pub gpuclk_ss_rate_10hz: u16,
7201 pub core_refclk_10khz: u32,
7202 pub ac_dc_gpio_bit: u8,
7203 pub ac_dc_polarity: u8,
7204 pub vr0hot_gpio_bit: u8,
7205 pub vr0hot_polarity: u8,
7206 pub vr1hot_gpio_bit: u8,
7207 pub vr1hot_polarity: u8,
7208 pub fw_ctf_gpio_bit: u8,
7209 pub fw_ctf_polarity: u8,
7210 pub pcc_gpio_bit: u8,
7211 pub pcc_gpio_polarity: u8,
7212 pub smugoldenoffset: u16,
7213 pub gpupll_vco_freq_10khz: u32,
7214 pub bootup_smnclk_10khz: u32,
7215 pub bootup_socclk_10khz: u32,
7216 pub bootup_mp0clk_10khz: u32,
7217 pub bootup_mp1clk_10khz: u32,
7218 pub bootup_lclk_10khz: u32,
7219 pub bootup_dcefclk_10khz: u32,
7220 pub ctf_threshold_override_value: u32,
7221 pub reserved: [u32; 5usize],
7222}
7223#[repr(C, packed)]
7224#[derive(Debug, Copy, Clone)]
7225pub struct atom_smu_info_v3_3 {
7226 pub table_header: atom_common_table_header,
7227 pub smuip_min_ver: u8,
7228 pub smuip_max_ver: u8,
7229 pub waflclk_ss_mode: u8,
7230 pub gpuclk_ss_mode: u8,
7231 pub sclk_ss_percentage: u16,
7232 pub sclk_ss_rate_10hz: u16,
7233 pub gpuclk_ss_percentage: u16,
7234 pub gpuclk_ss_rate_10hz: u16,
7235 pub core_refclk_10khz: u32,
7236 pub ac_dc_gpio_bit: u8,
7237 pub ac_dc_polarity: u8,
7238 pub vr0hot_gpio_bit: u8,
7239 pub vr0hot_polarity: u8,
7240 pub vr1hot_gpio_bit: u8,
7241 pub vr1hot_polarity: u8,
7242 pub fw_ctf_gpio_bit: u8,
7243 pub fw_ctf_polarity: u8,
7244 pub pcc_gpio_bit: u8,
7245 pub pcc_gpio_polarity: u8,
7246 pub smugoldenoffset: u16,
7247 pub gpupll_vco_freq_10khz: u32,
7248 pub bootup_smnclk_10khz: u32,
7249 pub bootup_socclk_10khz: u32,
7250 pub bootup_mp0clk_10khz: u32,
7251 pub bootup_mp1clk_10khz: u32,
7252 pub bootup_lclk_10khz: u32,
7253 pub bootup_dcefclk_10khz: u32,
7254 pub ctf_threshold_override_value: u32,
7255 pub syspll3_0_vco_freq_10khz: u32,
7256 pub syspll3_1_vco_freq_10khz: u32,
7257 pub bootup_fclk_10khz: u32,
7258 pub bootup_waflclk_10khz: u32,
7259 pub smu_info_caps: u32,
7260 pub waflclk_ss_percentage: u16,
7261 pub smuinitoffset: u16,
7262 pub reserved: u32,
7263}
7264#[repr(C, packed)]
7265#[derive(Debug, Copy, Clone)]
7266pub struct atom_smu_info_v3_5 {
7267 pub table_header: atom_common_table_header,
7268 pub smuip_min_ver: u8,
7269 pub smuip_max_ver: u8,
7270 pub waflclk_ss_mode: u8,
7271 pub gpuclk_ss_mode: u8,
7272 pub sclk_ss_percentage: u16,
7273 pub sclk_ss_rate_10hz: u16,
7274 pub gpuclk_ss_percentage: u16,
7275 pub gpuclk_ss_rate_10hz: u16,
7276 pub core_refclk_10khz: u32,
7277 pub syspll0_1_vco_freq_10khz: u32,
7278 pub syspll0_2_vco_freq_10khz: u32,
7279 pub pcc_gpio_bit: u8,
7280 pub pcc_gpio_polarity: u8,
7281 pub smugoldenoffset: u16,
7282 pub syspll0_0_vco_freq_10khz: u32,
7283 pub bootup_smnclk_10khz: u32,
7284 pub bootup_socclk_10khz: u32,
7285 pub bootup_mp0clk_10khz: u32,
7286 pub bootup_mp1clk_10khz: u32,
7287 pub bootup_lclk_10khz: u32,
7288 pub bootup_dcefclk_10khz: u32,
7289 pub ctf_threshold_override_value: u32,
7290 pub syspll3_0_vco_freq_10khz: u32,
7291 pub syspll3_1_vco_freq_10khz: u32,
7292 pub bootup_fclk_10khz: u32,
7293 pub bootup_waflclk_10khz: u32,
7294 pub smu_info_caps: u32,
7295 pub waflclk_ss_percentage: u16,
7296 pub smuinitoffset: u16,
7297 pub bootup_dprefclk_10khz: u32,
7298 pub bootup_usbclk_10khz: u32,
7299 pub smb_slave_address: u32,
7300 pub cg_fdo_ctrl0_val: u32,
7301 pub cg_fdo_ctrl1_val: u32,
7302 pub cg_fdo_ctrl2_val: u32,
7303 pub gdfll_as_wait_ctrl_val: u32,
7304 pub gdfll_as_step_ctrl_val: u32,
7305 pub bootup_dtbclk_10khz: u32,
7306 pub fclk_syspll_refclk_10khz: u32,
7307 pub smusvi_svc0_val: u32,
7308 pub smusvi_svc1_val: u32,
7309 pub smusvi_svd0_val: u32,
7310 pub smusvi_svd1_val: u32,
7311 pub smusvi_svt0_val: u32,
7312 pub smusvi_svt1_val: u32,
7313 pub cg_tach_ctrl_val: u32,
7314 pub cg_pump_ctrl1_val: u32,
7315 pub cg_pump_tach_ctrl_val: u32,
7316 pub thm_ctf_delay_val: u32,
7317 pub thm_thermal_int_ctrl_val: u32,
7318 pub thm_tmon_config_val: u32,
7319 pub reserved: [u32; 16usize],
7320}
7321#[repr(C, packed)]
7322#[derive(Debug, Copy, Clone)]
7323pub struct atom_smu_info_v3_6 {
7324 pub table_header: atom_common_table_header,
7325 pub smuip_min_ver: u8,
7326 pub smuip_max_ver: u8,
7327 pub waflclk_ss_mode: u8,
7328 pub gpuclk_ss_mode: u8,
7329 pub sclk_ss_percentage: u16,
7330 pub sclk_ss_rate_10hz: u16,
7331 pub gpuclk_ss_percentage: u16,
7332 pub gpuclk_ss_rate_10hz: u16,
7333 pub core_refclk_10khz: u32,
7334 pub syspll0_1_vco_freq_10khz: u32,
7335 pub syspll0_2_vco_freq_10khz: u32,
7336 pub pcc_gpio_bit: u8,
7337 pub pcc_gpio_polarity: u8,
7338 pub smugoldenoffset: u16,
7339 pub syspll0_0_vco_freq_10khz: u32,
7340 pub bootup_smnclk_10khz: u32,
7341 pub bootup_socclk_10khz: u32,
7342 pub bootup_mp0clk_10khz: u32,
7343 pub bootup_mp1clk_10khz: u32,
7344 pub bootup_lclk_10khz: u32,
7345 pub bootup_dxioclk_10khz: u32,
7346 pub ctf_threshold_override_value: u32,
7347 pub syspll3_0_vco_freq_10khz: u32,
7348 pub syspll3_1_vco_freq_10khz: u32,
7349 pub bootup_fclk_10khz: u32,
7350 pub bootup_waflclk_10khz: u32,
7351 pub smu_info_caps: u32,
7352 pub waflclk_ss_percentage: u16,
7353 pub smuinitoffset: u16,
7354 pub bootup_gfxavsclk_10khz: u32,
7355 pub bootup_mpioclk_10khz: u32,
7356 pub smb_slave_address: u32,
7357 pub cg_fdo_ctrl0_val: u32,
7358 pub cg_fdo_ctrl1_val: u32,
7359 pub cg_fdo_ctrl2_val: u32,
7360 pub gdfll_as_wait_ctrl_val: u32,
7361 pub gdfll_as_step_ctrl_val: u32,
7362 pub reserved_clk: u32,
7363 pub fclk_syspll_refclk_10khz: u32,
7364 pub smusvi_svc0_val: u32,
7365 pub smusvi_svc1_val: u32,
7366 pub smusvi_svd0_val: u32,
7367 pub smusvi_svd1_val: u32,
7368 pub smusvi_svt0_val: u32,
7369 pub smusvi_svt1_val: u32,
7370 pub cg_tach_ctrl_val: u32,
7371 pub cg_pump_ctrl1_val: u32,
7372 pub cg_pump_tach_ctrl_val: u32,
7373 pub thm_ctf_delay_val: u32,
7374 pub thm_thermal_int_ctrl_val: u32,
7375 pub thm_tmon_config_val: u32,
7376 pub bootup_vclk_10khz: u32,
7377 pub bootup_dclk_10khz: u32,
7378 pub smu_gpiopad_pu_en_val: u32,
7379 pub smu_gpiopad_pd_en_val: u32,
7380 pub reserved: [u32; 12usize],
7381}
7382#[repr(C, packed)]
7383#[derive(Debug, Copy, Clone)]
7384pub struct atom_smu_info_v4_0 {
7385 pub table_header: atom_common_table_header,
7386 pub bootup_gfxclk_bypass_10khz: u32,
7387 pub bootup_usrclk_10khz: u32,
7388 pub bootup_csrclk_10khz: u32,
7389 pub core_refclk_10khz: u32,
7390 pub syspll1_vco_freq_10khz: u32,
7391 pub syspll2_vco_freq_10khz: u32,
7392 pub pcc_gpio_bit: u8,
7393 pub pcc_gpio_polarity: u8,
7394 pub bootup_vddusr_mv: u16,
7395 pub syspll0_vco_freq_10khz: u32,
7396 pub bootup_smnclk_10khz: u32,
7397 pub bootup_socclk_10khz: u32,
7398 pub bootup_mp0clk_10khz: u32,
7399 pub bootup_mp1clk_10khz: u32,
7400 pub bootup_lclk_10khz: u32,
7401 pub bootup_dcefclk_10khz: u32,
7402 pub ctf_threshold_override_value: u32,
7403 pub syspll3_vco_freq_10khz: u32,
7404 pub mm_syspll_vco_freq_10khz: u32,
7405 pub bootup_fclk_10khz: u32,
7406 pub bootup_waflclk_10khz: u32,
7407 pub smu_info_caps: u32,
7408 pub waflclk_ss_percentage: u16,
7409 pub smuinitoffset: u16,
7410 pub bootup_dprefclk_10khz: u32,
7411 pub bootup_usbclk_10khz: u32,
7412 pub smb_slave_address: u32,
7413 pub cg_fdo_ctrl0_val: u32,
7414 pub cg_fdo_ctrl1_val: u32,
7415 pub cg_fdo_ctrl2_val: u32,
7416 pub gdfll_as_wait_ctrl_val: u32,
7417 pub gdfll_as_step_ctrl_val: u32,
7418 pub bootup_dtbclk_10khz: u32,
7419 pub fclk_syspll_refclk_10khz: u32,
7420 pub smusvi_svc0_val: u32,
7421 pub smusvi_svc1_val: u32,
7422 pub smusvi_svd0_val: u32,
7423 pub smusvi_svd1_val: u32,
7424 pub smusvi_svt0_val: u32,
7425 pub smusvi_svt1_val: u32,
7426 pub cg_tach_ctrl_val: u32,
7427 pub cg_pump_ctrl1_val: u32,
7428 pub cg_pump_tach_ctrl_val: u32,
7429 pub thm_ctf_delay_val: u32,
7430 pub thm_thermal_int_ctrl_val: u32,
7431 pub thm_tmon_config_val: u32,
7432 pub smbus_timing_cntrl0_val: u32,
7433 pub smbus_timing_cntrl1_val: u32,
7434 pub smbus_timing_cntrl2_val: u32,
7435 pub pwr_disp_timer_global_control_val: u32,
7436 pub bootup_mpioclk_10khz: u32,
7437 pub bootup_dclk0_10khz: u32,
7438 pub bootup_vclk0_10khz: u32,
7439 pub bootup_dclk1_10khz: u32,
7440 pub bootup_vclk1_10khz: u32,
7441 pub bootup_baco400clk_10khz: u32,
7442 pub bootup_baco1200clk_bypass_10khz: u32,
7443 pub bootup_baco700clk_bypass_10khz: u32,
7444 pub reserved: [u32; 16usize],
7445}
7446#[repr(C, packed)]
7447#[derive(Debug, Copy, Clone)]
7448pub struct atom_smc_dpm_info_v4_1 {
7449 pub table_header: atom_common_table_header,
7450 pub liquid1_i2c_address: u8,
7451 pub liquid2_i2c_address: u8,
7452 pub vr_i2c_address: u8,
7453 pub plx_i2c_address: u8,
7454 pub liquid_i2c_linescl: u8,
7455 pub liquid_i2c_linesda: u8,
7456 pub vr_i2c_linescl: u8,
7457 pub vr_i2c_linesda: u8,
7458 pub plx_i2c_linescl: u8,
7459 pub plx_i2c_linesda: u8,
7460 pub vrsensorpresent: u8,
7461 pub liquidsensorpresent: u8,
7462 pub maxvoltagestepgfx: u16,
7463 pub maxvoltagestepsoc: u16,
7464 pub vddgfxvrmapping: u8,
7465 pub vddsocvrmapping: u8,
7466 pub vddmem0vrmapping: u8,
7467 pub vddmem1vrmapping: u8,
7468 pub gfxulvphasesheddingmask: u8,
7469 pub soculvphasesheddingmask: u8,
7470 pub padding8_v: [u8; 2usize],
7471 pub gfxmaxcurrent: u16,
7472 pub gfxoffset: u8,
7473 pub padding_telemetrygfx: u8,
7474 pub socmaxcurrent: u16,
7475 pub socoffset: u8,
7476 pub padding_telemetrysoc: u8,
7477 pub mem0maxcurrent: u16,
7478 pub mem0offset: u8,
7479 pub padding_telemetrymem0: u8,
7480 pub mem1maxcurrent: u16,
7481 pub mem1offset: u8,
7482 pub padding_telemetrymem1: u8,
7483 pub acdcgpio: u8,
7484 pub acdcpolarity: u8,
7485 pub vr0hotgpio: u8,
7486 pub vr0hotpolarity: u8,
7487 pub vr1hotgpio: u8,
7488 pub vr1hotpolarity: u8,
7489 pub padding1: u8,
7490 pub padding2: u8,
7491 pub ledpin0: u8,
7492 pub ledpin1: u8,
7493 pub ledpin2: u8,
7494 pub padding8_4: u8,
7495 pub pllgfxclkspreadenabled: u8,
7496 pub pllgfxclkspreadpercent: u8,
7497 pub pllgfxclkspreadfreq: u16,
7498 pub uclkspreadenabled: u8,
7499 pub uclkspreadpercent: u8,
7500 pub uclkspreadfreq: u16,
7501 pub socclkspreadenabled: u8,
7502 pub socclkspreadpercent: u8,
7503 pub socclkspreadfreq: u16,
7504 pub acggfxclkspreadenabled: u8,
7505 pub acggfxclkspreadpercent: u8,
7506 pub acggfxclkspreadfreq: u16,
7507 pub Vr2_I2C_address: u8,
7508 pub padding_vr2: [u8; 3usize],
7509 pub boardreserved: [u32; 9usize],
7510}
7511#[repr(C, packed)]
7512#[derive(Debug, Copy, Clone)]
7513pub struct atom_smc_dpm_info_v4_3 {
7514 pub table_header: atom_common_table_header,
7515 pub liquid1_i2c_address: u8,
7516 pub liquid2_i2c_address: u8,
7517 pub vr_i2c_address: u8,
7518 pub plx_i2c_address: u8,
7519 pub liquid_i2c_linescl: u8,
7520 pub liquid_i2c_linesda: u8,
7521 pub vr_i2c_linescl: u8,
7522 pub vr_i2c_linesda: u8,
7523 pub plx_i2c_linescl: u8,
7524 pub plx_i2c_linesda: u8,
7525 pub vrsensorpresent: u8,
7526 pub liquidsensorpresent: u8,
7527 pub maxvoltagestepgfx: u16,
7528 pub maxvoltagestepsoc: u16,
7529 pub vddgfxvrmapping: u8,
7530 pub vddsocvrmapping: u8,
7531 pub vddmem0vrmapping: u8,
7532 pub vddmem1vrmapping: u8,
7533 pub gfxulvphasesheddingmask: u8,
7534 pub soculvphasesheddingmask: u8,
7535 pub externalsensorpresent: u8,
7536 pub padding8_v: u8,
7537 pub gfxmaxcurrent: u16,
7538 pub gfxoffset: u8,
7539 pub padding_telemetrygfx: u8,
7540 pub socmaxcurrent: u16,
7541 pub socoffset: u8,
7542 pub padding_telemetrysoc: u8,
7543 pub mem0maxcurrent: u16,
7544 pub mem0offset: u8,
7545 pub padding_telemetrymem0: u8,
7546 pub mem1maxcurrent: u16,
7547 pub mem1offset: u8,
7548 pub padding_telemetrymem1: u8,
7549 pub acdcgpio: u8,
7550 pub acdcpolarity: u8,
7551 pub vr0hotgpio: u8,
7552 pub vr0hotpolarity: u8,
7553 pub vr1hotgpio: u8,
7554 pub vr1hotpolarity: u8,
7555 pub padding1: u8,
7556 pub padding2: u8,
7557 pub ledpin0: u8,
7558 pub ledpin1: u8,
7559 pub ledpin2: u8,
7560 pub padding8_4: u8,
7561 pub pllgfxclkspreadenabled: u8,
7562 pub pllgfxclkspreadpercent: u8,
7563 pub pllgfxclkspreadfreq: u16,
7564 pub uclkspreadenabled: u8,
7565 pub uclkspreadpercent: u8,
7566 pub uclkspreadfreq: u16,
7567 pub fclkspreadenabled: u8,
7568 pub fclkspreadpercent: u8,
7569 pub fclkspreadfreq: u16,
7570 pub fllgfxclkspreadenabled: u8,
7571 pub fllgfxclkspreadpercent: u8,
7572 pub fllgfxclkspreadfreq: u16,
7573 pub boardreserved: [u32; 10usize],
7574}
7575#[repr(C, packed)]
7576#[derive(Debug, Copy, Clone)]
7577pub struct smudpm_i2ccontrollerconfig_t {
7578 pub enabled: u32,
7579 pub slaveaddress: u32,
7580 pub controllerport: u32,
7581 pub controllername: u32,
7582 pub thermalthrottler: u32,
7583 pub i2cprotocol: u32,
7584 pub i2cspeed: u32,
7585}
7586#[repr(C, packed)]
7587#[derive(Debug, Copy, Clone)]
7588pub struct atom_smc_dpm_info_v4_4 {
7589 pub table_header: atom_common_table_header,
7590 pub i2c_padding: [u32; 3usize],
7591 pub maxvoltagestepgfx: u16,
7592 pub maxvoltagestepsoc: u16,
7593 pub vddgfxvrmapping: u8,
7594 pub vddsocvrmapping: u8,
7595 pub vddmem0vrmapping: u8,
7596 pub vddmem1vrmapping: u8,
7597 pub gfxulvphasesheddingmask: u8,
7598 pub soculvphasesheddingmask: u8,
7599 pub externalsensorpresent: u8,
7600 pub padding8_v: u8,
7601 pub gfxmaxcurrent: u16,
7602 pub gfxoffset: u8,
7603 pub padding_telemetrygfx: u8,
7604 pub socmaxcurrent: u16,
7605 pub socoffset: u8,
7606 pub padding_telemetrysoc: u8,
7607 pub mem0maxcurrent: u16,
7608 pub mem0offset: u8,
7609 pub padding_telemetrymem0: u8,
7610 pub mem1maxcurrent: u16,
7611 pub mem1offset: u8,
7612 pub padding_telemetrymem1: u8,
7613 pub acdcgpio: u8,
7614 pub acdcpolarity: u8,
7615 pub vr0hotgpio: u8,
7616 pub vr0hotpolarity: u8,
7617 pub vr1hotgpio: u8,
7618 pub vr1hotpolarity: u8,
7619 pub padding1: u8,
7620 pub padding2: u8,
7621 pub ledpin0: u8,
7622 pub ledpin1: u8,
7623 pub ledpin2: u8,
7624 pub padding8_4: u8,
7625 pub pllgfxclkspreadenabled: u8,
7626 pub pllgfxclkspreadpercent: u8,
7627 pub pllgfxclkspreadfreq: u16,
7628 pub uclkspreadenabled: u8,
7629 pub uclkspreadpercent: u8,
7630 pub uclkspreadfreq: u16,
7631 pub fclkspreadenabled: u8,
7632 pub fclkspreadpercent: u8,
7633 pub fclkspreadfreq: u16,
7634 pub fllgfxclkspreadenabled: u8,
7635 pub fllgfxclkspreadpercent: u8,
7636 pub fllgfxclkspreadfreq: u16,
7637 pub i2ccontrollers: [smudpm_i2ccontrollerconfig_t; 7usize],
7638 pub boardreserved: [u32; 10usize],
7639}
7640pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX:
7641 smudpm_v4_5_i2ccontrollername_e = 0;
7642pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC:
7643 smudpm_v4_5_i2ccontrollername_e = 1;
7644pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI:
7645 smudpm_v4_5_i2ccontrollername_e = 2;
7646pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD:
7647 smudpm_v4_5_i2ccontrollername_e = 3;
7648pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0:
7649 smudpm_v4_5_i2ccontrollername_e = 4;
7650pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1:
7651 smudpm_v4_5_i2ccontrollername_e = 5;
7652pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_PLX:
7653 smudpm_v4_5_i2ccontrollername_e = 6;
7654pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_SPARE:
7655 smudpm_v4_5_i2ccontrollername_e = 7;
7656pub const smudpm_v4_5_i2ccontrollername_e_SMC_V4_5_I2C_CONTROLLER_NAME_COUNT:
7657 smudpm_v4_5_i2ccontrollername_e = 8;
7658pub type smudpm_v4_5_i2ccontrollername_e = ::core::ffi::c_uint;
7659pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE:
7660 smudpm_v4_5_i2ccontrollerthrottler_e = 0;
7661pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX:
7662 smudpm_v4_5_i2ccontrollerthrottler_e = 1;
7663pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC:
7664 smudpm_v4_5_i2ccontrollerthrottler_e = 2;
7665pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI:
7666 smudpm_v4_5_i2ccontrollerthrottler_e = 3;
7667pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD:
7668 smudpm_v4_5_i2ccontrollerthrottler_e = 4;
7669pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0:
7670 smudpm_v4_5_i2ccontrollerthrottler_e = 5;
7671pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1:
7672 smudpm_v4_5_i2ccontrollerthrottler_e = 6;
7673pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX:
7674 smudpm_v4_5_i2ccontrollerthrottler_e = 7;
7675pub const smudpm_v4_5_i2ccontrollerthrottler_e_SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT:
7676 smudpm_v4_5_i2ccontrollerthrottler_e = 8;
7677pub type smudpm_v4_5_i2ccontrollerthrottler_e = ::core::ffi::c_uint;
7678pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0:
7679 smudpm_v4_5_i2ccontrollerprotocol_e = 0;
7680pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1:
7681 smudpm_v4_5_i2ccontrollerprotocol_e = 1;
7682pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0:
7683 smudpm_v4_5_i2ccontrollerprotocol_e = 2;
7684pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1:
7685 smudpm_v4_5_i2ccontrollerprotocol_e = 3;
7686pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0:
7687 smudpm_v4_5_i2ccontrollerprotocol_e = 4;
7688pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1:
7689 smudpm_v4_5_i2ccontrollerprotocol_e = 5;
7690pub const smudpm_v4_5_i2ccontrollerprotocol_e_SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT:
7691 smudpm_v4_5_i2ccontrollerprotocol_e = 6;
7692pub type smudpm_v4_5_i2ccontrollerprotocol_e = ::core::ffi::c_uint;
7693#[repr(C, packed)]
7694#[derive(Debug, Copy, Clone)]
7695pub struct smudpm_i2c_controller_config_v2 {
7696 pub Enabled: u8,
7697 pub Speed: u8,
7698 pub Padding: [u8; 2usize],
7699 pub SlaveAddress: u32,
7700 pub ControllerPort: u8,
7701 pub ControllerName: u8,
7702 pub ThermalThrotter: u8,
7703 pub I2cProtocol: u8,
7704}
7705#[repr(C, packed)]
7706#[derive(Debug, Copy, Clone)]
7707pub struct atom_smc_dpm_info_v4_5 {
7708 pub table_header: atom_common_table_header,
7709 pub I2cControllers: [smudpm_i2c_controller_config_v2; 8usize],
7710 pub MaxVoltageStepGfx: u16,
7711 pub MaxVoltageStepSoc: u16,
7712 pub VddGfxVrMapping: u8,
7713 pub VddSocVrMapping: u8,
7714 pub VddMem0VrMapping: u8,
7715 pub VddMem1VrMapping: u8,
7716 pub GfxUlvPhaseSheddingMask: u8,
7717 pub SocUlvPhaseSheddingMask: u8,
7718 pub ExternalSensorPresent: u8,
7719 pub Padding8_V: u8,
7720 pub GfxMaxCurrent: u16,
7721 pub GfxOffset: u8,
7722 pub Padding_TelemetryGfx: u8,
7723 pub SocMaxCurrent: u16,
7724 pub SocOffset: u8,
7725 pub Padding_TelemetrySoc: u8,
7726 pub Mem0MaxCurrent: u16,
7727 pub Mem0Offset: u8,
7728 pub Padding_TelemetryMem0: u8,
7729 pub Mem1MaxCurrent: u16,
7730 pub Mem1Offset: u8,
7731 pub Padding_TelemetryMem1: u8,
7732 pub AcDcGpio: u8,
7733 pub AcDcPolarity: u8,
7734 pub VR0HotGpio: u8,
7735 pub VR0HotPolarity: u8,
7736 pub VR1HotGpio: u8,
7737 pub VR1HotPolarity: u8,
7738 pub GthrGpio: u8,
7739 pub GthrPolarity: u8,
7740 pub LedPin0: u8,
7741 pub LedPin1: u8,
7742 pub LedPin2: u8,
7743 pub padding8_4: u8,
7744 pub PllGfxclkSpreadEnabled: u8,
7745 pub PllGfxclkSpreadPercent: u8,
7746 pub PllGfxclkSpreadFreq: u16,
7747 pub DfllGfxclkSpreadEnabled: u8,
7748 pub DfllGfxclkSpreadPercent: u8,
7749 pub DfllGfxclkSpreadFreq: u16,
7750 pub UclkSpreadEnabled: u8,
7751 pub UclkSpreadPercent: u8,
7752 pub UclkSpreadFreq: u16,
7753 pub SoclkSpreadEnabled: u8,
7754 pub SocclkSpreadPercent: u8,
7755 pub SocclkSpreadFreq: u16,
7756 pub TotalBoardPower: u16,
7757 pub BoardPadding: u16,
7758 pub MvddRatio: u32,
7759 pub BoardReserved: [u32; 9usize],
7760}
7761#[repr(C, packed)]
7762#[derive(Debug, Copy, Clone)]
7763pub struct atom_smc_dpm_info_v4_6 {
7764 pub table_header: atom_common_table_header,
7765 pub i2c_padding: [u32; 3usize],
7766 pub maxvoltagestepgfx: u16,
7767 pub maxvoltagestepsoc: u16,
7768 pub vddgfxvrmapping: u8,
7769 pub vddsocvrmapping: u8,
7770 pub vddmemvrmapping: u8,
7771 pub boardvrmapping: u8,
7772 pub gfxulvphasesheddingmask: u8,
7773 pub externalsensorpresent: u8,
7774 pub padding8_v: [u8; 2usize],
7775 pub gfxmaxcurrent: u16,
7776 pub gfxoffset: u8,
7777 pub padding_telemetrygfx: u8,
7778 pub socmaxcurrent: u16,
7779 pub socoffset: u8,
7780 pub padding_telemetrysoc: u8,
7781 pub memmaxcurrent: u16,
7782 pub memoffset: u8,
7783 pub padding_telemetrymem: u8,
7784 pub boardmaxcurrent: u16,
7785 pub boardoffset: u8,
7786 pub padding_telemetryboardinput: u8,
7787 pub vr0hotgpio: u8,
7788 pub vr0hotpolarity: u8,
7789 pub vr1hotgpio: u8,
7790 pub vr1hotpolarity: u8,
7791 pub pllgfxclkspreadenabled: u8,
7792 pub pllgfxclkspreadpercent: u8,
7793 pub pllgfxclkspreadfreq: u16,
7794 pub uclkspreadenabled: u8,
7795 pub uclkspreadpercent: u8,
7796 pub uclkspreadfreq: u16,
7797 pub fclkspreadenabled: u8,
7798 pub fclkspreadpercent: u8,
7799 pub fclkspreadfreq: u16,
7800 pub fllgfxclkspreadenabled: u8,
7801 pub fllgfxclkspreadpercent: u8,
7802 pub fllgfxclkspreadfreq: u16,
7803 pub i2ccontrollers: [smudpm_i2c_controller_config_v2; 8usize],
7804 pub memorychannelenabled: u32,
7805 pub drambitwidth: u8,
7806 pub paddingmem: [u8; 3usize],
7807 pub totalboardpower: u16,
7808 pub boardpadding: u16,
7809 pub xgmilinkspeed: [u8; 4usize],
7810 pub xgmilinkwidth: [u8; 4usize],
7811 pub xgmifclkfreq: [u16; 4usize],
7812 pub xgmisocvoltage: [u16; 4usize],
7813 pub boardreserved: [u32; 10usize],
7814}
7815#[repr(C, packed)]
7816#[derive(Debug, Copy, Clone)]
7817pub struct atom_smc_dpm_info_v4_7 {
7818 pub table_header: atom_common_table_header,
7819 pub I2cControllers: [smudpm_i2c_controller_config_v2; 8usize],
7820 pub MaxVoltageStepGfx: u16,
7821 pub MaxVoltageStepSoc: u16,
7822 pub VddGfxVrMapping: u8,
7823 pub VddSocVrMapping: u8,
7824 pub VddMem0VrMapping: u8,
7825 pub VddMem1VrMapping: u8,
7826 pub GfxUlvPhaseSheddingMask: u8,
7827 pub SocUlvPhaseSheddingMask: u8,
7828 pub ExternalSensorPresent: u8,
7829 pub Padding8_V: u8,
7830 pub GfxMaxCurrent: u16,
7831 pub GfxOffset: u8,
7832 pub Padding_TelemetryGfx: u8,
7833 pub SocMaxCurrent: u16,
7834 pub SocOffset: u8,
7835 pub Padding_TelemetrySoc: u8,
7836 pub Mem0MaxCurrent: u16,
7837 pub Mem0Offset: u8,
7838 pub Padding_TelemetryMem0: u8,
7839 pub Mem1MaxCurrent: u16,
7840 pub Mem1Offset: u8,
7841 pub Padding_TelemetryMem1: u8,
7842 pub AcDcGpio: u8,
7843 pub AcDcPolarity: u8,
7844 pub VR0HotGpio: u8,
7845 pub VR0HotPolarity: u8,
7846 pub VR1HotGpio: u8,
7847 pub VR1HotPolarity: u8,
7848 pub GthrGpio: u8,
7849 pub GthrPolarity: u8,
7850 pub LedPin0: u8,
7851 pub LedPin1: u8,
7852 pub LedPin2: u8,
7853 pub padding8_4: u8,
7854 pub PllGfxclkSpreadEnabled: u8,
7855 pub PllGfxclkSpreadPercent: u8,
7856 pub PllGfxclkSpreadFreq: u16,
7857 pub DfllGfxclkSpreadEnabled: u8,
7858 pub DfllGfxclkSpreadPercent: u8,
7859 pub DfllGfxclkSpreadFreq: u16,
7860 pub UclkSpreadEnabled: u8,
7861 pub UclkSpreadPercent: u8,
7862 pub UclkSpreadFreq: u16,
7863 pub SoclkSpreadEnabled: u8,
7864 pub SocclkSpreadPercent: u8,
7865 pub SocclkSpreadFreq: u16,
7866 pub TotalBoardPower: u16,
7867 pub BoardPadding: u16,
7868 pub MvddRatio: u32,
7869 pub GpioI2cScl: u8,
7870 pub GpioI2cSda: u8,
7871 pub GpioPadding: u16,
7872 pub LedPin3: u8,
7873 pub LedPin4: u8,
7874 pub LedEnableMask: u16,
7875 pub PowerLimitScalar: [u8; 4usize],
7876 pub MvddUlvPhaseSheddingMask: u8,
7877 pub VddciUlvPhaseSheddingMask: u8,
7878 pub Padding8_Psi1: u8,
7879 pub Padding8_Psi2: u8,
7880 pub BoardReserved: [u32; 5usize],
7881}
7882#[repr(C)]
7883#[derive(Debug, Copy, Clone)]
7884pub struct smudpm_i2c_controller_config_v3 {
7885 pub Enabled: u8,
7886 pub Speed: u8,
7887 pub SlaveAddress: u8,
7888 pub ControllerPort: u8,
7889 pub ControllerName: u8,
7890 pub ThermalThrotter: u8,
7891 pub I2cProtocol: u8,
7892 pub PaddingConfig: u8,
7893}
7894#[repr(C, packed)]
7895#[derive(Debug, Copy, Clone)]
7896pub struct atom_smc_dpm_info_v4_9 {
7897 pub table_header: atom_common_table_header,
7898 pub I2cControllers: [smudpm_i2c_controller_config_v3; 16usize],
7899 pub GpioScl: u8,
7900 pub GpioSda: u8,
7901 pub FchUsbPdSlaveAddr: u8,
7902 pub I2cSpare: u8,
7903 pub VddGfxVrMapping: u8,
7904 pub VddSocVrMapping: u8,
7905 pub VddMem0VrMapping: u8,
7906 pub VddMem1VrMapping: u8,
7907 pub GfxUlvPhaseSheddingMask: u8,
7908 pub SocUlvPhaseSheddingMask: u8,
7909 pub VddciUlvPhaseSheddingMask: u8,
7910 pub MvddUlvPhaseSheddingMask: u8,
7911 pub GfxMaxCurrent: u16,
7912 pub GfxOffset: u8,
7913 pub Padding_TelemetryGfx: u8,
7914 pub SocMaxCurrent: u16,
7915 pub SocOffset: u8,
7916 pub Padding_TelemetrySoc: u8,
7917 pub Mem0MaxCurrent: u16,
7918 pub Mem0Offset: u8,
7919 pub Padding_TelemetryMem0: u8,
7920 pub Mem1MaxCurrent: u16,
7921 pub Mem1Offset: u8,
7922 pub Padding_TelemetryMem1: u8,
7923 pub MvddRatio: u32,
7924 pub AcDcGpio: u8,
7925 pub AcDcPolarity: u8,
7926 pub VR0HotGpio: u8,
7927 pub VR0HotPolarity: u8,
7928 pub VR1HotGpio: u8,
7929 pub VR1HotPolarity: u8,
7930 pub GthrGpio: u8,
7931 pub GthrPolarity: u8,
7932 pub LedPin0: u8,
7933 pub LedPin1: u8,
7934 pub LedPin2: u8,
7935 pub LedEnableMask: u8,
7936 pub LedPcie: u8,
7937 pub LedError: u8,
7938 pub LedSpare1: [u8; 2usize],
7939 pub PllGfxclkSpreadEnabled: u8,
7940 pub PllGfxclkSpreadPercent: u8,
7941 pub PllGfxclkSpreadFreq: u16,
7942 pub DfllGfxclkSpreadEnabled: u8,
7943 pub DfllGfxclkSpreadPercent: u8,
7944 pub DfllGfxclkSpreadFreq: u16,
7945 pub UclkSpreadEnabled: u8,
7946 pub UclkSpreadPercent: u8,
7947 pub UclkSpreadFreq: u16,
7948 pub FclkSpreadEnabled: u8,
7949 pub FclkSpreadPercent: u8,
7950 pub FclkSpreadFreq: u16,
7951 pub MemoryChannelEnabled: u32,
7952 pub DramBitWidth: u8,
7953 pub PaddingMem1: [u8; 3usize],
7954 pub TotalBoardPower: u16,
7955 pub BoardPowerPadding: u16,
7956 pub XgmiLinkSpeed: [u8; 4usize],
7957 pub XgmiLinkWidth: [u8; 4usize],
7958 pub XgmiFclkFreq: [u16; 4usize],
7959 pub XgmiSocVoltage: [u16; 4usize],
7960 pub BoardReserved: [u32; 16usize],
7961}
7962#[repr(C, packed)]
7963#[derive(Debug, Copy, Clone)]
7964pub struct atom_smc_dpm_info_v4_10 {
7965 pub table_header: atom_common_table_header,
7966 pub GfxMaxCurrent: u16,
7967 pub GfxOffset: u8,
7968 pub Padding_TelemetryGfx: u8,
7969 pub SocMaxCurrent: u16,
7970 pub SocOffset: u8,
7971 pub Padding_TelemetrySoc: u8,
7972 pub MemMaxCurrent: u16,
7973 pub MemOffset: u8,
7974 pub Padding_TelemetryMem: u8,
7975 pub BoardMaxCurrent: u16,
7976 pub BoardOffset: u8,
7977 pub Padding_TelemetryBoardInput: u8,
7978 pub BoardVoltageCoeffA: u32,
7979 pub BoardVoltageCoeffB: u32,
7980 pub VR0HotGpio: u8,
7981 pub VR0HotPolarity: u8,
7982 pub VR1HotGpio: u8,
7983 pub VR1HotPolarity: u8,
7984 pub UclkSpreadEnabled: u8,
7985 pub UclkSpreadPercent: u8,
7986 pub UclkSpreadFreq: u16,
7987 pub FclkSpreadEnabled: u8,
7988 pub FclkSpreadPercent: u8,
7989 pub FclkSpreadFreq: u16,
7990 pub I2cControllers: [smudpm_i2c_controller_config_v3; 8usize],
7991 pub GpioI2cScl: u8,
7992 pub GpioI2cSda: u8,
7993 pub spare5: u16,
7994 pub reserved: [u32; 16usize],
7995}
7996#[repr(C, packed)]
7997#[derive(Debug, Copy, Clone)]
7998pub struct atom_asic_profiling_info_v4_1 {
7999 pub table_header: atom_common_table_header,
8000 pub maxvddc: u32,
8001 pub minvddc: u32,
8002 pub avfs_meannsigma_acontant0: u32,
8003 pub avfs_meannsigma_acontant1: u32,
8004 pub avfs_meannsigma_acontant2: u32,
8005 pub avfs_meannsigma_dc_tol_sigma: u16,
8006 pub avfs_meannsigma_platform_mean: u16,
8007 pub avfs_meannsigma_platform_sigma: u16,
8008 pub gb_vdroop_table_cksoff_a0: u32,
8009 pub gb_vdroop_table_cksoff_a1: u32,
8010 pub gb_vdroop_table_cksoff_a2: u32,
8011 pub gb_vdroop_table_ckson_a0: u32,
8012 pub gb_vdroop_table_ckson_a1: u32,
8013 pub gb_vdroop_table_ckson_a2: u32,
8014 pub avfsgb_fuse_table_cksoff_m1: u32,
8015 pub avfsgb_fuse_table_cksoff_m2: u32,
8016 pub avfsgb_fuse_table_cksoff_b: u32,
8017 pub avfsgb_fuse_table_ckson_m1: u32,
8018 pub avfsgb_fuse_table_ckson_m2: u32,
8019 pub avfsgb_fuse_table_ckson_b: u32,
8020 pub max_voltage_0_25mv: u16,
8021 pub enable_gb_vdroop_table_cksoff: u8,
8022 pub enable_gb_vdroop_table_ckson: u8,
8023 pub enable_gb_fuse_table_cksoff: u8,
8024 pub enable_gb_fuse_table_ckson: u8,
8025 pub psm_age_comfactor: u16,
8026 pub enable_apply_avfs_cksoff_voltage: u8,
8027 pub reserved: u8,
8028 pub dispclk2gfxclk_a: u32,
8029 pub dispclk2gfxclk_b: u32,
8030 pub dispclk2gfxclk_c: u32,
8031 pub pixclk2gfxclk_a: u32,
8032 pub pixclk2gfxclk_b: u32,
8033 pub pixclk2gfxclk_c: u32,
8034 pub dcefclk2gfxclk_a: u32,
8035 pub dcefclk2gfxclk_b: u32,
8036 pub dcefclk2gfxclk_c: u32,
8037 pub phyclk2gfxclk_a: u32,
8038 pub phyclk2gfxclk_b: u32,
8039 pub phyclk2gfxclk_c: u32,
8040}
8041#[repr(C, packed)]
8042#[derive(Debug, Copy, Clone)]
8043pub struct atom_asic_profiling_info_v4_2 {
8044 pub table_header: atom_common_table_header,
8045 pub maxvddc: u32,
8046 pub minvddc: u32,
8047 pub avfs_meannsigma_acontant0: u32,
8048 pub avfs_meannsigma_acontant1: u32,
8049 pub avfs_meannsigma_acontant2: u32,
8050 pub avfs_meannsigma_dc_tol_sigma: u16,
8051 pub avfs_meannsigma_platform_mean: u16,
8052 pub avfs_meannsigma_platform_sigma: u16,
8053 pub gb_vdroop_table_cksoff_a0: u32,
8054 pub gb_vdroop_table_cksoff_a1: u32,
8055 pub gb_vdroop_table_cksoff_a2: u32,
8056 pub gb_vdroop_table_ckson_a0: u32,
8057 pub gb_vdroop_table_ckson_a1: u32,
8058 pub gb_vdroop_table_ckson_a2: u32,
8059 pub avfsgb_fuse_table_cksoff_m1: u32,
8060 pub avfsgb_fuse_table_cksoff_m2: u32,
8061 pub avfsgb_fuse_table_cksoff_b: u32,
8062 pub avfsgb_fuse_table_ckson_m1: u32,
8063 pub avfsgb_fuse_table_ckson_m2: u32,
8064 pub avfsgb_fuse_table_ckson_b: u32,
8065 pub max_voltage_0_25mv: u16,
8066 pub enable_gb_vdroop_table_cksoff: u8,
8067 pub enable_gb_vdroop_table_ckson: u8,
8068 pub enable_gb_fuse_table_cksoff: u8,
8069 pub enable_gb_fuse_table_ckson: u8,
8070 pub psm_age_comfactor: u16,
8071 pub enable_apply_avfs_cksoff_voltage: u8,
8072 pub reserved: u8,
8073 pub dispclk2gfxclk_a: u32,
8074 pub dispclk2gfxclk_b: u32,
8075 pub dispclk2gfxclk_c: u32,
8076 pub pixclk2gfxclk_a: u32,
8077 pub pixclk2gfxclk_b: u32,
8078 pub pixclk2gfxclk_c: u32,
8079 pub dcefclk2gfxclk_a: u32,
8080 pub dcefclk2gfxclk_b: u32,
8081 pub dcefclk2gfxclk_c: u32,
8082 pub phyclk2gfxclk_a: u32,
8083 pub phyclk2gfxclk_b: u32,
8084 pub phyclk2gfxclk_c: u32,
8085 pub acg_gb_vdroop_table_a0: u32,
8086 pub acg_gb_vdroop_table_a1: u32,
8087 pub acg_gb_vdroop_table_a2: u32,
8088 pub acg_avfsgb_fuse_table_m1: u32,
8089 pub acg_avfsgb_fuse_table_m2: u32,
8090 pub acg_avfsgb_fuse_table_b: u32,
8091 pub enable_acg_gb_vdroop_table: u8,
8092 pub enable_acg_gb_fuse_table: u8,
8093 pub acg_dispclk2gfxclk_a: u32,
8094 pub acg_dispclk2gfxclk_b: u32,
8095 pub acg_dispclk2gfxclk_c: u32,
8096 pub acg_pixclk2gfxclk_a: u32,
8097 pub acg_pixclk2gfxclk_b: u32,
8098 pub acg_pixclk2gfxclk_c: u32,
8099 pub acg_dcefclk2gfxclk_a: u32,
8100 pub acg_dcefclk2gfxclk_b: u32,
8101 pub acg_dcefclk2gfxclk_c: u32,
8102 pub acg_phyclk2gfxclk_a: u32,
8103 pub acg_phyclk2gfxclk_b: u32,
8104 pub acg_phyclk2gfxclk_c: u32,
8105}
8106#[repr(C, packed)]
8107#[derive(Debug, Copy, Clone)]
8108pub struct atom_multimedia_info_v2_1 {
8109 pub table_header: atom_common_table_header,
8110 pub uvdip_min_ver: u8,
8111 pub uvdip_max_ver: u8,
8112 pub vceip_min_ver: u8,
8113 pub vceip_max_ver: u8,
8114 pub uvd_enc_max_input_width_pixels: u16,
8115 pub uvd_enc_max_input_height_pixels: u16,
8116 pub vce_enc_max_input_width_pixels: u16,
8117 pub vce_enc_max_input_height_pixels: u16,
8118 pub uvd_enc_max_bandwidth: u32,
8119 pub vce_enc_max_bandwidth: u32,
8120}
8121#[repr(C, packed)]
8122#[derive(Debug, Copy, Clone)]
8123pub struct atom_umc_info_v3_1 {
8124 pub table_header: atom_common_table_header,
8125 pub ucode_version: u32,
8126 pub ucode_rom_startaddr: u32,
8127 pub ucode_length: u32,
8128 pub umc_reg_init_offset: u16,
8129 pub customer_ucode_name_offset: u16,
8130 pub mclk_ss_percentage: u16,
8131 pub mclk_ss_rate_10hz: u16,
8132 pub umcip_min_ver: u8,
8133 pub umcip_max_ver: u8,
8134 pub vram_type: u8,
8135 pub umc_config: u8,
8136 pub mem_refclk_10khz: u32,
8137}
8138pub const atom_umc_config_def_UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE: atom_umc_config_def = 1;
8139pub const atom_umc_config_def_UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE: atom_umc_config_def = 2;
8140pub const atom_umc_config_def_UMC_CONFIG__ENABLE_HBM_LANE_REPAIR: atom_umc_config_def = 4;
8141pub const atom_umc_config_def_UMC_CONFIG__ENABLE_BANK_HARVESTING: atom_umc_config_def = 8;
8142pub const atom_umc_config_def_UMC_CONFIG__ENABLE_PHY_REINIT: atom_umc_config_def = 16;
8143pub const atom_umc_config_def_UMC_CONFIG__DISABLE_UCODE_CHKSTATUS: atom_umc_config_def = 32;
8144pub type atom_umc_config_def = ::core::ffi::c_uint;
8145#[repr(C, packed)]
8146#[derive(Debug, Copy, Clone)]
8147pub struct atom_umc_info_v3_2 {
8148 pub table_header: atom_common_table_header,
8149 pub ucode_version: u32,
8150 pub ucode_rom_startaddr: u32,
8151 pub ucode_length: u32,
8152 pub umc_reg_init_offset: u16,
8153 pub customer_ucode_name_offset: u16,
8154 pub mclk_ss_percentage: u16,
8155 pub mclk_ss_rate_10hz: u16,
8156 pub umcip_min_ver: u8,
8157 pub umcip_max_ver: u8,
8158 pub vram_type: u8,
8159 pub umc_config: u8,
8160 pub mem_refclk_10khz: u32,
8161 pub pstate_uclk_10khz: [u32; 4usize],
8162 pub umcgoldenoffset: u16,
8163 pub densitygoldenoffset: u16,
8164}
8165#[repr(C, packed)]
8166#[derive(Debug, Copy, Clone)]
8167pub struct atom_umc_info_v3_3 {
8168 pub table_header: atom_common_table_header,
8169 pub ucode_reserved: u32,
8170 pub ucode_rom_startaddr: u32,
8171 pub ucode_length: u32,
8172 pub umc_reg_init_offset: u16,
8173 pub customer_ucode_name_offset: u16,
8174 pub mclk_ss_percentage: u16,
8175 pub mclk_ss_rate_10hz: u16,
8176 pub umcip_min_ver: u8,
8177 pub umcip_max_ver: u8,
8178 pub vram_type: u8,
8179 pub umc_config: u8,
8180 pub mem_refclk_10khz: u32,
8181 pub pstate_uclk_10khz: [u32; 4usize],
8182 pub umcgoldenoffset: u16,
8183 pub densitygoldenoffset: u16,
8184 pub umc_config1: u32,
8185 pub bist_data_startaddr: u32,
8186 pub reserved: [u32; 2usize],
8187}
8188pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN: atom_umc_config1_def =
8189 1;
8190pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_AUTO_FRAMING: atom_umc_config1_def = 2;
8191pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA: atom_umc_config1_def = 4;
8192pub const atom_umc_config1_def_UMC_CONFIG1__DISABLE_STROBE_MODE: atom_umc_config1_def = 8;
8193pub const atom_umc_config1_def_UMC_CONFIG1__DEBUG_DATA_PARITY_EN: atom_umc_config1_def = 16;
8194pub const atom_umc_config1_def_UMC_CONFIG1__ENABLE_ECC_CAPABLE: atom_umc_config1_def = 65536;
8195pub type atom_umc_config1_def = ::core::ffi::c_uint;
8196#[repr(C, packed)]
8197#[derive(Debug, Copy, Clone)]
8198pub struct atom_umc_info_v4_0 {
8199 pub table_header: atom_common_table_header,
8200 pub ucode_reserved: [u32; 5usize],
8201 pub umcip_min_ver: u8,
8202 pub umcip_max_ver: u8,
8203 pub vram_type: u8,
8204 pub umc_config: u8,
8205 pub mem_refclk_10khz: u32,
8206 pub clk_reserved: [u32; 4usize],
8207 pub golden_reserved: u32,
8208 pub umc_config1: u32,
8209 pub reserved: [u32; 2usize],
8210 pub channel_num: u8,
8211 pub channel_width: u8,
8212 pub channel_reserve: [u8; 2usize],
8213 pub umc_info_reserved: [u8; 16usize],
8214}
8215#[repr(C, packed)]
8216#[derive(Debug, Copy, Clone)]
8217pub struct atom_vram_module_v9 {
8218 pub memory_size: u32,
8219 pub channel_enable: u32,
8220 pub max_mem_clk: u32,
8221 pub reserved: [u16; 3usize],
8222 pub mem_voltage: u16,
8223 pub vram_module_size: u16,
8224 pub ext_memory_id: u8,
8225 pub memory_type: u8,
8226 pub channel_num: u8,
8227 pub channel_width: u8,
8228 pub density: u8,
8229 pub tunningset_id: u8,
8230 pub vender_rev_id: u8,
8231 pub refreshrate: u8,
8232 pub hbm_ven_rev_id: u8,
8233 pub vram_rsd2: u8,
8234 pub dram_pnstring: [::core::ffi::c_char; 20usize],
8235}
8236#[repr(C, packed)]
8237#[derive(Debug, Copy, Clone)]
8238pub struct atom_vram_info_header_v2_3 {
8239 pub table_header: atom_common_table_header,
8240 pub mem_adjust_tbloffset: u16,
8241 pub mem_clk_patch_tbloffset: u16,
8242 pub mc_adjust_pertile_tbloffset: u16,
8243 pub mc_phyinit_tbloffset: u16,
8244 pub dram_data_remap_tbloffset: u16,
8245 pub tmrs_seq_offset: u16,
8246 pub post_ucode_init_offset: u16,
8247 pub vram_rsd2: u16,
8248 pub vram_module_num: u8,
8249 pub umcip_min_ver: u8,
8250 pub umcip_max_ver: u8,
8251 pub mc_phy_tile_num: u8,
8252 pub vram_module: [atom_vram_module_v9; 16usize],
8253}
8254#[repr(C, packed)]
8255#[derive(Debug, Copy, Clone)]
8256pub struct atom_vram_module_v3_0 {
8257 pub density: u8,
8258 pub tunningset_id: u8,
8259 pub ext_memory_id: u8,
8260 pub dram_vendor_id: u8,
8261 pub dram_info_offset: u16,
8262 pub mem_tuning_offset: u16,
8263 pub tmrs_seq_offset: u16,
8264 pub reserved1: u16,
8265 pub dram_size_per_ch: u32,
8266 pub reserved: [u32; 3usize],
8267 pub dram_pnstring: [::core::ffi::c_char; 40usize],
8268}
8269#[repr(C, packed)]
8270#[derive(Debug, Copy, Clone)]
8271pub struct atom_vram_info_header_v3_0 {
8272 pub table_header: atom_common_table_header,
8273 pub mem_tuning_table_offset: u16,
8274 pub dram_info_table_offset: u16,
8275 pub tmrs_table_offset: u16,
8276 pub mc_init_table_offset: u16,
8277 pub dram_data_remap_table_offset: u16,
8278 pub umc_emuinittable_offset: u16,
8279 pub reserved_sub_table_offset: [u16; 2usize],
8280 pub vram_module_num: u8,
8281 pub umcip_min_ver: u8,
8282 pub umcip_max_ver: u8,
8283 pub mc_phy_tile_num: u8,
8284 pub memory_type: u8,
8285 pub channel_num: u8,
8286 pub channel_width: u8,
8287 pub reserved1: u8,
8288 pub channel_enable: u32,
8289 pub channel1_enable: u32,
8290 pub feature_enable: u32,
8291 pub feature1_enable: u32,
8292 pub hardcode_mem_size: u32,
8293 pub reserved4: [u32; 4usize],
8294 pub vram_module: [atom_vram_module_v3_0; 8usize],
8295}
8296#[repr(C)]
8297#[derive(Debug, Copy, Clone)]
8298pub struct atom_umc_register_addr_info {
8299 pub _bitfield_align_1: [u8; 0],
8300 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8301}
8302impl atom_umc_register_addr_info {
8303 #[inline]
8304 pub fn umc_register_addr(&self) -> u32 {
8305 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8306 }
8307 #[inline]
8308 pub fn set_umc_register_addr(&mut self, val: u32) {
8309 unsafe {
8310 let val: u32 = ::core::mem::transmute(val);
8311 self._bitfield_1.set(0usize, 24u8, val as u64)
8312 }
8313 }
8314 #[inline]
8315 pub unsafe fn umc_register_addr_raw(this: *const Self) -> u32 {
8316 unsafe {
8317 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8318 ::core::ptr::addr_of!((*this)._bitfield_1),
8319 0usize,
8320 24u8,
8321 ) as u32)
8322 }
8323 }
8324 #[inline]
8325 pub unsafe fn set_umc_register_addr_raw(this: *mut Self, val: u32) {
8326 unsafe {
8327 let val: u32 = ::core::mem::transmute(val);
8328 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8329 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8330 0usize,
8331 24u8,
8332 val as u64,
8333 )
8334 }
8335 }
8336 #[inline]
8337 pub fn umc_reg_type_ind(&self) -> u32 {
8338 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
8339 }
8340 #[inline]
8341 pub fn set_umc_reg_type_ind(&mut self, val: u32) {
8342 unsafe {
8343 let val: u32 = ::core::mem::transmute(val);
8344 self._bitfield_1.set(24usize, 1u8, val as u64)
8345 }
8346 }
8347 #[inline]
8348 pub unsafe fn umc_reg_type_ind_raw(this: *const Self) -> u32 {
8349 unsafe {
8350 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8351 ::core::ptr::addr_of!((*this)._bitfield_1),
8352 24usize,
8353 1u8,
8354 ) as u32)
8355 }
8356 }
8357 #[inline]
8358 pub unsafe fn set_umc_reg_type_ind_raw(this: *mut Self, val: u32) {
8359 unsafe {
8360 let val: u32 = ::core::mem::transmute(val);
8361 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8362 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8363 24usize,
8364 1u8,
8365 val as u64,
8366 )
8367 }
8368 }
8369 #[inline]
8370 pub fn umc_reg_rsvd(&self) -> u32 {
8371 unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 7u8) as u32) }
8372 }
8373 #[inline]
8374 pub fn set_umc_reg_rsvd(&mut self, val: u32) {
8375 unsafe {
8376 let val: u32 = ::core::mem::transmute(val);
8377 self._bitfield_1.set(25usize, 7u8, val as u64)
8378 }
8379 }
8380 #[inline]
8381 pub unsafe fn umc_reg_rsvd_raw(this: *const Self) -> u32 {
8382 unsafe {
8383 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8384 ::core::ptr::addr_of!((*this)._bitfield_1),
8385 25usize,
8386 7u8,
8387 ) as u32)
8388 }
8389 }
8390 #[inline]
8391 pub unsafe fn set_umc_reg_rsvd_raw(this: *mut Self, val: u32) {
8392 unsafe {
8393 let val: u32 = ::core::mem::transmute(val);
8394 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8395 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8396 25usize,
8397 7u8,
8398 val as u64,
8399 )
8400 }
8401 }
8402 #[inline]
8403 pub fn new_bitfield_1(
8404 umc_register_addr: u32,
8405 umc_reg_type_ind: u32,
8406 umc_reg_rsvd: u32,
8407 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
8408 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
8409 __bindgen_bitfield_unit.set(0usize, 24u8, {
8410 let umc_register_addr: u32 = unsafe { ::core::mem::transmute(umc_register_addr) };
8411 umc_register_addr as u64
8412 });
8413 __bindgen_bitfield_unit.set(24usize, 1u8, {
8414 let umc_reg_type_ind: u32 = unsafe { ::core::mem::transmute(umc_reg_type_ind) };
8415 umc_reg_type_ind as u64
8416 });
8417 __bindgen_bitfield_unit.set(25usize, 7u8, {
8418 let umc_reg_rsvd: u32 = unsafe { ::core::mem::transmute(umc_reg_rsvd) };
8419 umc_reg_rsvd as u64
8420 });
8421 __bindgen_bitfield_unit
8422 }
8423}
8424pub const atom_umc_register_addr_info_flag_b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS:
8425 atom_umc_register_addr_info_flag = 1;
8426pub type atom_umc_register_addr_info_flag = ::core::ffi::c_uint;
8427#[repr(C, packed)]
8428#[derive(Copy, Clone)]
8429pub union atom_umc_register_addr_info_access {
8430 pub umc_reg_addr: atom_umc_register_addr_info,
8431 pub u32umc_reg_addr: u32,
8432}
8433#[repr(C)]
8434#[derive(Debug, Copy, Clone)]
8435pub struct atom_umc_reg_setting_id_config {
8436 pub _bitfield_align_1: [u8; 0],
8437 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8438}
8439impl atom_umc_reg_setting_id_config {
8440 #[inline]
8441 pub fn memclockrange(&self) -> u32 {
8442 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8443 }
8444 #[inline]
8445 pub fn set_memclockrange(&mut self, val: u32) {
8446 unsafe {
8447 let val: u32 = ::core::mem::transmute(val);
8448 self._bitfield_1.set(0usize, 24u8, val as u64)
8449 }
8450 }
8451 #[inline]
8452 pub unsafe fn memclockrange_raw(this: *const Self) -> u32 {
8453 unsafe {
8454 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8455 ::core::ptr::addr_of!((*this)._bitfield_1),
8456 0usize,
8457 24u8,
8458 ) as u32)
8459 }
8460 }
8461 #[inline]
8462 pub unsafe fn set_memclockrange_raw(this: *mut Self, val: u32) {
8463 unsafe {
8464 let val: u32 = ::core::mem::transmute(val);
8465 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8466 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8467 0usize,
8468 24u8,
8469 val as u64,
8470 )
8471 }
8472 }
8473 #[inline]
8474 pub fn mem_blk_id(&self) -> u32 {
8475 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
8476 }
8477 #[inline]
8478 pub fn set_mem_blk_id(&mut self, val: u32) {
8479 unsafe {
8480 let val: u32 = ::core::mem::transmute(val);
8481 self._bitfield_1.set(24usize, 8u8, val as u64)
8482 }
8483 }
8484 #[inline]
8485 pub unsafe fn mem_blk_id_raw(this: *const Self) -> u32 {
8486 unsafe {
8487 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8488 ::core::ptr::addr_of!((*this)._bitfield_1),
8489 24usize,
8490 8u8,
8491 ) as u32)
8492 }
8493 }
8494 #[inline]
8495 pub unsafe fn set_mem_blk_id_raw(this: *mut Self, val: u32) {
8496 unsafe {
8497 let val: u32 = ::core::mem::transmute(val);
8498 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8499 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8500 24usize,
8501 8u8,
8502 val as u64,
8503 )
8504 }
8505 }
8506 #[inline]
8507 pub fn new_bitfield_1(
8508 memclockrange: u32,
8509 mem_blk_id: u32,
8510 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
8511 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
8512 __bindgen_bitfield_unit.set(0usize, 24u8, {
8513 let memclockrange: u32 = unsafe { ::core::mem::transmute(memclockrange) };
8514 memclockrange as u64
8515 });
8516 __bindgen_bitfield_unit.set(24usize, 8u8, {
8517 let mem_blk_id: u32 = unsafe { ::core::mem::transmute(mem_blk_id) };
8518 mem_blk_id as u64
8519 });
8520 __bindgen_bitfield_unit
8521 }
8522}
8523#[repr(C, packed)]
8524#[derive(Copy, Clone)]
8525pub union atom_umc_reg_setting_id_config_access {
8526 pub umc_id_access: atom_umc_reg_setting_id_config,
8527 pub u32umc_id_access: u32,
8528}
8529#[repr(C, packed)]
8530#[derive(Copy, Clone)]
8531pub struct atom_umc_reg_setting_data_block {
8532 pub block_id: atom_umc_reg_setting_id_config_access,
8533 pub u32umc_reg_data: [u32; 1usize],
8534}
8535#[repr(C, packed)]
8536#[derive(Copy, Clone)]
8537pub struct atom_umc_init_reg_block {
8538 pub umc_reg_num: u16,
8539 pub reserved: u16,
8540 pub umc_reg_list: [atom_umc_register_addr_info_access; 1usize],
8541 pub umc_reg_setting_list: [atom_umc_reg_setting_data_block; 1usize],
8542}
8543#[repr(C, packed)]
8544#[derive(Debug, Copy, Clone)]
8545pub struct atom_vram_module_v10 {
8546 pub memory_size: u32,
8547 pub channel_enable: u32,
8548 pub max_mem_clk: u32,
8549 pub reserved: [u16; 3usize],
8550 pub mem_voltage: u16,
8551 pub vram_module_size: u16,
8552 pub ext_memory_id: u8,
8553 pub memory_type: u8,
8554 pub channel_num: u8,
8555 pub channel_width: u8,
8556 pub density: u8,
8557 pub tunningset_id: u8,
8558 pub vender_rev_id: u8,
8559 pub refreshrate: u8,
8560 pub vram_flags: u8,
8561 pub vram_rsd2: u8,
8562 pub gddr6_mr10: u16,
8563 pub gddr6_mr1: u16,
8564 pub gddr6_mr2: u16,
8565 pub gddr6_mr7: u16,
8566 pub dram_pnstring: [::core::ffi::c_char; 20usize],
8567}
8568#[repr(C, packed)]
8569#[derive(Debug, Copy, Clone)]
8570pub struct atom_vram_info_header_v2_4 {
8571 pub table_header: atom_common_table_header,
8572 pub mem_adjust_tbloffset: u16,
8573 pub mem_clk_patch_tbloffset: u16,
8574 pub mc_adjust_pertile_tbloffset: u16,
8575 pub mc_phyinit_tbloffset: u16,
8576 pub dram_data_remap_tbloffset: u16,
8577 pub reserved: u16,
8578 pub post_ucode_init_offset: u16,
8579 pub vram_rsd2: u16,
8580 pub vram_module_num: u8,
8581 pub umcip_min_ver: u8,
8582 pub umcip_max_ver: u8,
8583 pub mc_phy_tile_num: u8,
8584 pub vram_module: [atom_vram_module_v10; 16usize],
8585}
8586#[repr(C, packed)]
8587#[derive(Debug, Copy, Clone)]
8588pub struct atom_vram_module_v11 {
8589 pub memory_size: u32,
8590 pub channel_enable: u32,
8591 pub mem_voltage: u16,
8592 pub vram_module_size: u16,
8593 pub ext_memory_id: u8,
8594 pub memory_type: u8,
8595 pub channel_num: u8,
8596 pub channel_width: u8,
8597 pub density: u8,
8598 pub tunningset_id: u8,
8599 pub reserved: [u16; 4usize],
8600 pub vender_rev_id: u8,
8601 pub refreshrate: u8,
8602 pub vram_flags: u8,
8603 pub vram_rsd2: u8,
8604 pub gddr6_mr10: u16,
8605 pub gddr6_mr0: u16,
8606 pub gddr6_mr1: u16,
8607 pub gddr6_mr2: u16,
8608 pub gddr6_mr4: u16,
8609 pub gddr6_mr7: u16,
8610 pub gddr6_mr8: u16,
8611 pub dram_pnstring: [::core::ffi::c_char; 40usize],
8612}
8613#[repr(C, packed)]
8614#[derive(Debug, Copy, Clone)]
8615pub struct atom_gddr6_ac_timing_v2_5 {
8616 pub u32umc_id_access: u32,
8617 pub RL: u8,
8618 pub WL: u8,
8619 pub tRAS: u8,
8620 pub tRC: u8,
8621 pub tREFI: u16,
8622 pub tRFC: u8,
8623 pub tRFCpb: u8,
8624 pub tRREFD: u8,
8625 pub tRCDRD: u8,
8626 pub tRCDWR: u8,
8627 pub tRP: u8,
8628 pub tRRDS: u8,
8629 pub tRRDL: u8,
8630 pub tWR: u8,
8631 pub tWTRS: u8,
8632 pub tWTRL: u8,
8633 pub tFAW: u8,
8634 pub tCCDS: u8,
8635 pub tCCDL: u8,
8636 pub tCRCRL: u8,
8637 pub tCRCWL: u8,
8638 pub tCKE: u8,
8639 pub tCKSRE: u8,
8640 pub tCKSRX: u8,
8641 pub tRTPS: u8,
8642 pub tRTPL: u8,
8643 pub tMRD: u8,
8644 pub tMOD: u8,
8645 pub tXS: u8,
8646 pub tXHP: u8,
8647 pub tXSMRS: u8,
8648 pub tXSH: u32,
8649 pub tPD: u8,
8650 pub tXP: u8,
8651 pub tCPDED: u8,
8652 pub tACTPDE: u8,
8653 pub tPREPDE: u8,
8654 pub tREFPDE: u8,
8655 pub tMRSPDEN: u8,
8656 pub tRDSRE: u8,
8657 pub tWRSRE: u8,
8658 pub tPPD: u8,
8659 pub tCCDMW: u8,
8660 pub tWTRTR: u8,
8661 pub tLTLTR: u8,
8662 pub tREFTR: u8,
8663 pub VNDR: u8,
8664 pub reserved: [u8; 9usize],
8665}
8666#[repr(C, packed)]
8667#[derive(Debug, Copy, Clone)]
8668pub struct atom_gddr6_bit_byte_remap {
8669 pub dphy_byteremap: u32,
8670 pub dphy_bitremap0: u32,
8671 pub dphy_bitremap1: u32,
8672 pub dphy_bitremap2: u32,
8673 pub aphy_bitremap0: u32,
8674 pub aphy_bitremap1: u32,
8675 pub phy_dram: u32,
8676}
8677#[repr(C, packed)]
8678#[derive(Debug, Copy, Clone)]
8679pub struct atom_gddr6_dram_data_remap {
8680 pub table_size: u32,
8681 pub phyintf_ck_inverted: [u8; 8usize],
8682 pub bit_byte_remap: [atom_gddr6_bit_byte_remap; 16usize],
8683}
8684#[repr(C, packed)]
8685#[derive(Debug, Copy, Clone)]
8686pub struct atom_vram_info_header_v2_5 {
8687 pub table_header: atom_common_table_header,
8688 pub mem_adjust_tbloffset: u16,
8689 pub gddr6_ac_timing_offset: u16,
8690 pub mc_adjust_pertile_tbloffset: u16,
8691 pub mc_phyinit_tbloffset: u16,
8692 pub dram_data_remap_tbloffset: u16,
8693 pub reserved: u16,
8694 pub post_ucode_init_offset: u16,
8695 pub strobe_mode_patch_tbloffset: u16,
8696 pub vram_module_num: u8,
8697 pub umcip_min_ver: u8,
8698 pub umcip_max_ver: u8,
8699 pub mc_phy_tile_num: u8,
8700 pub vram_module: [atom_vram_module_v11; 16usize],
8701}
8702#[repr(C, packed)]
8703#[derive(Debug, Copy, Clone)]
8704pub struct atom_vram_info_header_v2_6 {
8705 pub table_header: atom_common_table_header,
8706 pub mem_adjust_tbloffset: u16,
8707 pub mem_clk_patch_tbloffset: u16,
8708 pub mc_adjust_pertile_tbloffset: u16,
8709 pub mc_phyinit_tbloffset: u16,
8710 pub dram_data_remap_tbloffset: u16,
8711 pub tmrs_seq_offset: u16,
8712 pub post_ucode_init_offset: u16,
8713 pub vram_rsd2: u16,
8714 pub vram_module_num: u8,
8715 pub umcip_min_ver: u8,
8716 pub umcip_max_ver: u8,
8717 pub mc_phy_tile_num: u8,
8718 pub vram_module: [atom_vram_module_v9; 16usize],
8719}
8720#[repr(C, packed)]
8721#[derive(Debug, Copy, Clone)]
8722pub struct atom_i2c_data_entry {
8723 pub i2c_reg_index: u16,
8724 pub i2c_reg_data: u16,
8725}
8726#[repr(C, packed)]
8727#[derive(Debug, Copy, Clone)]
8728pub struct atom_voltage_object_header_v4 {
8729 pub voltage_type: u8,
8730 pub voltage_mode: u8,
8731 pub object_size: u16,
8732}
8733pub const atom_voltage_object_mode_VOLTAGE_OBJ_GPIO_LUT: atom_voltage_object_mode = 0;
8734pub const atom_voltage_object_mode_VOLTAGE_OBJ_VR_I2C_INIT_SEQ: atom_voltage_object_mode = 3;
8735pub const atom_voltage_object_mode_VOLTAGE_OBJ_PHASE_LUT: atom_voltage_object_mode = 4;
8736pub const atom_voltage_object_mode_VOLTAGE_OBJ_SVID2: atom_voltage_object_mode = 7;
8737pub const atom_voltage_object_mode_VOLTAGE_OBJ_EVV: atom_voltage_object_mode = 8;
8738pub const atom_voltage_object_mode_VOLTAGE_OBJ_MERGED_POWER: atom_voltage_object_mode = 9;
8739pub type atom_voltage_object_mode = ::core::ffi::c_uint;
8740#[repr(C)]
8741#[derive(Debug, Copy, Clone)]
8742pub struct atom_i2c_voltage_object_v4 {
8743 pub header: atom_voltage_object_header_v4,
8744 pub regulator_id: u8,
8745 pub i2c_id: u8,
8746 pub i2c_slave_addr: u8,
8747 pub i2c_control_offset: u8,
8748 pub i2c_flag: u8,
8749 pub i2c_speed: u8,
8750 pub reserved: [u8; 2usize],
8751 pub i2cdatalut: [atom_i2c_data_entry; 1usize],
8752}
8753pub const atom_i2c_voltage_control_flag_VOLTAGE_DATA_ONE_BYTE: atom_i2c_voltage_control_flag = 0;
8754pub const atom_i2c_voltage_control_flag_VOLTAGE_DATA_TWO_BYTE: atom_i2c_voltage_control_flag = 1;
8755pub type atom_i2c_voltage_control_flag = ::core::ffi::c_uint;
8756#[repr(C, packed)]
8757#[derive(Debug, Copy, Clone)]
8758pub struct atom_voltage_gpio_map_lut {
8759 pub voltage_gpio_reg_val: u32,
8760 pub voltage_level_mv: u16,
8761}
8762#[repr(C, packed)]
8763#[derive(Debug, Copy, Clone)]
8764pub struct atom_gpio_voltage_object_v4 {
8765 pub header: atom_voltage_object_header_v4,
8766 pub gpio_control_id: u8,
8767 pub gpio_entry_num: u8,
8768 pub phase_delay_us: u8,
8769 pub reserved: u8,
8770 pub gpio_mask_val: u32,
8771 pub voltage_gpio_lut: [atom_voltage_gpio_map_lut; 1usize],
8772}
8773#[repr(C, packed)]
8774#[derive(Debug, Copy, Clone)]
8775pub struct atom_svid2_voltage_object_v4 {
8776 pub header: atom_voltage_object_header_v4,
8777 pub loadline_psi1: u8,
8778 pub psi0_l_vid_thresd: u8,
8779 pub psi0_enable: u8,
8780 pub maxvstep: u8,
8781 pub telemetry_offset: u8,
8782 pub telemetry_gain: u8,
8783 pub reserved1: u16,
8784}
8785#[repr(C)]
8786#[derive(Debug, Copy, Clone)]
8787pub struct atom_merged_voltage_object_v4 {
8788 pub header: atom_voltage_object_header_v4,
8789 pub merged_powerrail_type: u8,
8790 pub reserved: [u8; 3usize],
8791}
8792#[repr(C)]
8793#[derive(Copy, Clone)]
8794pub union atom_voltage_object_v4 {
8795 pub gpio_voltage_obj: atom_gpio_voltage_object_v4,
8796 pub i2c_voltage_obj: atom_i2c_voltage_object_v4,
8797 pub svid2_voltage_obj: atom_svid2_voltage_object_v4,
8798 pub merged_voltage_obj: atom_merged_voltage_object_v4,
8799}
8800#[repr(C)]
8801#[derive(Copy, Clone)]
8802pub struct atom_voltage_objects_info_v4_1 {
8803 pub table_header: atom_common_table_header,
8804 pub voltage_object: [atom_voltage_object_v4; 1usize],
8805}
8806#[repr(C)]
8807#[derive(Debug, Copy, Clone)]
8808pub struct asic_init_engine_parameters {
8809 pub _bitfield_align_1: [u8; 0],
8810 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8811}
8812impl asic_init_engine_parameters {
8813 #[inline]
8814 pub fn sclkfreqin10khz(&self) -> u32 {
8815 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8816 }
8817 #[inline]
8818 pub fn set_sclkfreqin10khz(&mut self, val: u32) {
8819 unsafe {
8820 let val: u32 = ::core::mem::transmute(val);
8821 self._bitfield_1.set(0usize, 24u8, val as u64)
8822 }
8823 }
8824 #[inline]
8825 pub unsafe fn sclkfreqin10khz_raw(this: *const Self) -> u32 {
8826 unsafe {
8827 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8828 ::core::ptr::addr_of!((*this)._bitfield_1),
8829 0usize,
8830 24u8,
8831 ) as u32)
8832 }
8833 }
8834 #[inline]
8835 pub unsafe fn set_sclkfreqin10khz_raw(this: *mut Self, val: u32) {
8836 unsafe {
8837 let val: u32 = ::core::mem::transmute(val);
8838 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8839 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8840 0usize,
8841 24u8,
8842 val as u64,
8843 )
8844 }
8845 }
8846 #[inline]
8847 pub fn engineflag(&self) -> u32 {
8848 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
8849 }
8850 #[inline]
8851 pub fn set_engineflag(&mut self, val: u32) {
8852 unsafe {
8853 let val: u32 = ::core::mem::transmute(val);
8854 self._bitfield_1.set(24usize, 8u8, val as u64)
8855 }
8856 }
8857 #[inline]
8858 pub unsafe fn engineflag_raw(this: *const Self) -> u32 {
8859 unsafe {
8860 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8861 ::core::ptr::addr_of!((*this)._bitfield_1),
8862 24usize,
8863 8u8,
8864 ) as u32)
8865 }
8866 }
8867 #[inline]
8868 pub unsafe fn set_engineflag_raw(this: *mut Self, val: u32) {
8869 unsafe {
8870 let val: u32 = ::core::mem::transmute(val);
8871 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8872 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8873 24usize,
8874 8u8,
8875 val as u64,
8876 )
8877 }
8878 }
8879 #[inline]
8880 pub fn new_bitfield_1(
8881 sclkfreqin10khz: u32,
8882 engineflag: u32,
8883 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
8884 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
8885 __bindgen_bitfield_unit.set(0usize, 24u8, {
8886 let sclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(sclkfreqin10khz) };
8887 sclkfreqin10khz as u64
8888 });
8889 __bindgen_bitfield_unit.set(24usize, 8u8, {
8890 let engineflag: u32 = unsafe { ::core::mem::transmute(engineflag) };
8891 engineflag as u64
8892 });
8893 __bindgen_bitfield_unit
8894 }
8895}
8896#[repr(C)]
8897#[derive(Debug, Copy, Clone)]
8898pub struct asic_init_mem_parameters {
8899 pub _bitfield_align_1: [u8; 0],
8900 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
8901}
8902impl asic_init_mem_parameters {
8903 #[inline]
8904 pub fn mclkfreqin10khz(&self) -> u32 {
8905 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
8906 }
8907 #[inline]
8908 pub fn set_mclkfreqin10khz(&mut self, val: u32) {
8909 unsafe {
8910 let val: u32 = ::core::mem::transmute(val);
8911 self._bitfield_1.set(0usize, 24u8, val as u64)
8912 }
8913 }
8914 #[inline]
8915 pub unsafe fn mclkfreqin10khz_raw(this: *const Self) -> u32 {
8916 unsafe {
8917 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8918 ::core::ptr::addr_of!((*this)._bitfield_1),
8919 0usize,
8920 24u8,
8921 ) as u32)
8922 }
8923 }
8924 #[inline]
8925 pub unsafe fn set_mclkfreqin10khz_raw(this: *mut Self, val: u32) {
8926 unsafe {
8927 let val: u32 = ::core::mem::transmute(val);
8928 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8929 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8930 0usize,
8931 24u8,
8932 val as u64,
8933 )
8934 }
8935 }
8936 #[inline]
8937 pub fn memflag(&self) -> u32 {
8938 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
8939 }
8940 #[inline]
8941 pub fn set_memflag(&mut self, val: u32) {
8942 unsafe {
8943 let val: u32 = ::core::mem::transmute(val);
8944 self._bitfield_1.set(24usize, 8u8, val as u64)
8945 }
8946 }
8947 #[inline]
8948 pub unsafe fn memflag_raw(this: *const Self) -> u32 {
8949 unsafe {
8950 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
8951 ::core::ptr::addr_of!((*this)._bitfield_1),
8952 24usize,
8953 8u8,
8954 ) as u32)
8955 }
8956 }
8957 #[inline]
8958 pub unsafe fn set_memflag_raw(this: *mut Self, val: u32) {
8959 unsafe {
8960 let val: u32 = ::core::mem::transmute(val);
8961 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
8962 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
8963 24usize,
8964 8u8,
8965 val as u64,
8966 )
8967 }
8968 }
8969 #[inline]
8970 pub fn new_bitfield_1(
8971 mclkfreqin10khz: u32,
8972 memflag: u32,
8973 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
8974 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
8975 __bindgen_bitfield_unit.set(0usize, 24u8, {
8976 let mclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(mclkfreqin10khz) };
8977 mclkfreqin10khz as u64
8978 });
8979 __bindgen_bitfield_unit.set(24usize, 8u8, {
8980 let memflag: u32 = unsafe { ::core::mem::transmute(memflag) };
8981 memflag as u64
8982 });
8983 __bindgen_bitfield_unit
8984 }
8985}
8986#[repr(C)]
8987#[derive(Debug, Copy, Clone)]
8988pub struct asic_init_parameters_v2_1 {
8989 pub engineparam: asic_init_engine_parameters,
8990 pub memparam: asic_init_mem_parameters,
8991}
8992#[repr(C, packed)]
8993#[derive(Debug, Copy, Clone)]
8994pub struct asic_init_ps_allocation_v2_1 {
8995 pub param: asic_init_parameters_v2_1,
8996 pub reserved: [u32; 16usize],
8997}
8998pub const atom_asic_init_engine_flag_b3NORMAL_ENGINE_INIT: atom_asic_init_engine_flag = 0;
8999pub const atom_asic_init_engine_flag_b3SRIOV_SKIP_ASIC_INIT: atom_asic_init_engine_flag = 2;
9000pub const atom_asic_init_engine_flag_b3SRIOV_LOAD_UCODE: atom_asic_init_engine_flag = 64;
9001pub type atom_asic_init_engine_flag = ::core::ffi::c_uint;
9002pub const atom_asic_init_mem_flag_b3NORMAL_MEM_INIT: atom_asic_init_mem_flag = 0;
9003pub const atom_asic_init_mem_flag_b3DRAM_SELF_REFRESH_EXIT: atom_asic_init_mem_flag = 32;
9004pub type atom_asic_init_mem_flag = ::core::ffi::c_uint;
9005#[repr(C, packed)]
9006#[derive(Debug, Copy, Clone)]
9007pub struct set_engine_clock_parameters_v2_1 {
9008 pub _bitfield_align_1: [u8; 0],
9009 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9010 pub reserved: [u32; 10usize],
9011}
9012impl set_engine_clock_parameters_v2_1 {
9013 #[inline]
9014 pub fn sclkfreqin10khz(&self) -> u32 {
9015 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9016 }
9017 #[inline]
9018 pub fn set_sclkfreqin10khz(&mut self, val: u32) {
9019 unsafe {
9020 let val: u32 = ::core::mem::transmute(val);
9021 self._bitfield_1.set(0usize, 24u8, val as u64)
9022 }
9023 }
9024 #[inline]
9025 pub unsafe fn sclkfreqin10khz_raw(this: *const Self) -> u32 {
9026 unsafe {
9027 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9028 ::core::ptr::addr_of!((*this)._bitfield_1),
9029 0usize,
9030 24u8,
9031 ) as u32)
9032 }
9033 }
9034 #[inline]
9035 pub unsafe fn set_sclkfreqin10khz_raw(this: *mut Self, val: u32) {
9036 unsafe {
9037 let val: u32 = ::core::mem::transmute(val);
9038 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9039 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9040 0usize,
9041 24u8,
9042 val as u64,
9043 )
9044 }
9045 }
9046 #[inline]
9047 pub fn sclkflag(&self) -> u32 {
9048 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9049 }
9050 #[inline]
9051 pub fn set_sclkflag(&mut self, val: u32) {
9052 unsafe {
9053 let val: u32 = ::core::mem::transmute(val);
9054 self._bitfield_1.set(24usize, 8u8, val as u64)
9055 }
9056 }
9057 #[inline]
9058 pub unsafe fn sclkflag_raw(this: *const Self) -> u32 {
9059 unsafe {
9060 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9061 ::core::ptr::addr_of!((*this)._bitfield_1),
9062 24usize,
9063 8u8,
9064 ) as u32)
9065 }
9066 }
9067 #[inline]
9068 pub unsafe fn set_sclkflag_raw(this: *mut Self, val: u32) {
9069 unsafe {
9070 let val: u32 = ::core::mem::transmute(val);
9071 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9072 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9073 24usize,
9074 8u8,
9075 val as u64,
9076 )
9077 }
9078 }
9079 #[inline]
9080 pub fn new_bitfield_1(
9081 sclkfreqin10khz: u32,
9082 sclkflag: u32,
9083 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9084 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9085 __bindgen_bitfield_unit.set(0usize, 24u8, {
9086 let sclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(sclkfreqin10khz) };
9087 sclkfreqin10khz as u64
9088 });
9089 __bindgen_bitfield_unit.set(24usize, 8u8, {
9090 let sclkflag: u32 = unsafe { ::core::mem::transmute(sclkflag) };
9091 sclkflag as u64
9092 });
9093 __bindgen_bitfield_unit
9094 }
9095}
9096#[repr(C, packed)]
9097#[derive(Debug, Copy, Clone)]
9098pub struct set_engine_clock_ps_allocation_v2_1 {
9099 pub clockinfo: set_engine_clock_parameters_v2_1,
9100 pub reserved: [u32; 10usize],
9101}
9102pub const atom_set_engine_mem_clock_flag_b3NORMAL_CHANGE_CLOCK: atom_set_engine_mem_clock_flag = 0;
9103pub const atom_set_engine_mem_clock_flag_b3FIRST_TIME_CHANGE_CLOCK: atom_set_engine_mem_clock_flag =
9104 8;
9105pub const atom_set_engine_mem_clock_flag_b3STORE_DPM_TRAINGING: atom_set_engine_mem_clock_flag = 64;
9106pub type atom_set_engine_mem_clock_flag = ::core::ffi::c_uint;
9107#[repr(C, packed)]
9108#[derive(Debug, Copy, Clone)]
9109pub struct get_engine_clock_parameter {
9110 pub sclk_10khz: u32,
9111 pub reserved: u32,
9112}
9113#[repr(C, packed)]
9114#[derive(Debug, Copy, Clone)]
9115pub struct set_memory_clock_parameters_v2_1 {
9116 pub _bitfield_align_1: [u8; 0],
9117 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9118 pub reserved: [u32; 10usize],
9119}
9120impl set_memory_clock_parameters_v2_1 {
9121 #[inline]
9122 pub fn mclkfreqin10khz(&self) -> u32 {
9123 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9124 }
9125 #[inline]
9126 pub fn set_mclkfreqin10khz(&mut self, val: u32) {
9127 unsafe {
9128 let val: u32 = ::core::mem::transmute(val);
9129 self._bitfield_1.set(0usize, 24u8, val as u64)
9130 }
9131 }
9132 #[inline]
9133 pub unsafe fn mclkfreqin10khz_raw(this: *const Self) -> u32 {
9134 unsafe {
9135 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9136 ::core::ptr::addr_of!((*this)._bitfield_1),
9137 0usize,
9138 24u8,
9139 ) as u32)
9140 }
9141 }
9142 #[inline]
9143 pub unsafe fn set_mclkfreqin10khz_raw(this: *mut Self, val: u32) {
9144 unsafe {
9145 let val: u32 = ::core::mem::transmute(val);
9146 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9147 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9148 0usize,
9149 24u8,
9150 val as u64,
9151 )
9152 }
9153 }
9154 #[inline]
9155 pub fn mclkflag(&self) -> u32 {
9156 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9157 }
9158 #[inline]
9159 pub fn set_mclkflag(&mut self, val: u32) {
9160 unsafe {
9161 let val: u32 = ::core::mem::transmute(val);
9162 self._bitfield_1.set(24usize, 8u8, val as u64)
9163 }
9164 }
9165 #[inline]
9166 pub unsafe fn mclkflag_raw(this: *const Self) -> u32 {
9167 unsafe {
9168 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9169 ::core::ptr::addr_of!((*this)._bitfield_1),
9170 24usize,
9171 8u8,
9172 ) as u32)
9173 }
9174 }
9175 #[inline]
9176 pub unsafe fn set_mclkflag_raw(this: *mut Self, val: u32) {
9177 unsafe {
9178 let val: u32 = ::core::mem::transmute(val);
9179 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9180 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9181 24usize,
9182 8u8,
9183 val as u64,
9184 )
9185 }
9186 }
9187 #[inline]
9188 pub fn new_bitfield_1(
9189 mclkfreqin10khz: u32,
9190 mclkflag: u32,
9191 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9192 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9193 __bindgen_bitfield_unit.set(0usize, 24u8, {
9194 let mclkfreqin10khz: u32 = unsafe { ::core::mem::transmute(mclkfreqin10khz) };
9195 mclkfreqin10khz as u64
9196 });
9197 __bindgen_bitfield_unit.set(24usize, 8u8, {
9198 let mclkflag: u32 = unsafe { ::core::mem::transmute(mclkflag) };
9199 mclkflag as u64
9200 });
9201 __bindgen_bitfield_unit
9202 }
9203}
9204#[repr(C, packed)]
9205#[derive(Debug, Copy, Clone)]
9206pub struct set_memory_clock_ps_allocation_v2_1 {
9207 pub clockinfo: set_memory_clock_parameters_v2_1,
9208 pub reserved: [u32; 10usize],
9209}
9210#[repr(C, packed)]
9211#[derive(Debug, Copy, Clone)]
9212pub struct get_memory_clock_parameter {
9213 pub mclk_10khz: u32,
9214 pub reserved: u32,
9215}
9216#[repr(C, packed)]
9217#[derive(Debug, Copy, Clone)]
9218pub struct set_voltage_parameters_v1_4 {
9219 pub voltagetype: u8,
9220 pub command: u8,
9221 pub vlevel_mv: u16,
9222}
9223pub const atom_set_voltage_command_ATOM_SET_VOLTAGE: atom_set_voltage_command = 0;
9224pub const atom_set_voltage_command_ATOM_INIT_VOLTAGE_REGULATOR: atom_set_voltage_command = 3;
9225pub const atom_set_voltage_command_ATOM_SET_VOLTAGE_PHASE: atom_set_voltage_command = 4;
9226pub const atom_set_voltage_command_ATOM_GET_LEAKAGE_ID: atom_set_voltage_command = 8;
9227pub type atom_set_voltage_command = ::core::ffi::c_uint;
9228#[repr(C, packed)]
9229#[derive(Debug, Copy, Clone)]
9230pub struct set_voltage_ps_allocation_v1_4 {
9231 pub setvoltageparam: set_voltage_parameters_v1_4,
9232 pub reserved: [u32; 10usize],
9233}
9234pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK: atom_gpu_clock_type = 0;
9235pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK: atom_gpu_clock_type = 1;
9236pub const atom_gpu_clock_type_COMPUTE_GPUCLK_INPUT_FLAG_UCLK: atom_gpu_clock_type = 2;
9237pub type atom_gpu_clock_type = ::core::ffi::c_uint;
9238#[repr(C, packed)]
9239#[derive(Debug, Copy, Clone)]
9240pub struct compute_gpu_clock_input_parameter_v1_8 {
9241 pub _bitfield_align_1: [u8; 0],
9242 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9243 pub reserved: [u32; 5usize],
9244}
9245impl compute_gpu_clock_input_parameter_v1_8 {
9246 #[inline]
9247 pub fn gpuclock_10khz(&self) -> u32 {
9248 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9249 }
9250 #[inline]
9251 pub fn set_gpuclock_10khz(&mut self, val: u32) {
9252 unsafe {
9253 let val: u32 = ::core::mem::transmute(val);
9254 self._bitfield_1.set(0usize, 24u8, val as u64)
9255 }
9256 }
9257 #[inline]
9258 pub unsafe fn gpuclock_10khz_raw(this: *const Self) -> u32 {
9259 unsafe {
9260 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9261 ::core::ptr::addr_of!((*this)._bitfield_1),
9262 0usize,
9263 24u8,
9264 ) as u32)
9265 }
9266 }
9267 #[inline]
9268 pub unsafe fn set_gpuclock_10khz_raw(this: *mut Self, val: u32) {
9269 unsafe {
9270 let val: u32 = ::core::mem::transmute(val);
9271 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9272 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9273 0usize,
9274 24u8,
9275 val as u64,
9276 )
9277 }
9278 }
9279 #[inline]
9280 pub fn gpu_clock_type(&self) -> u32 {
9281 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9282 }
9283 #[inline]
9284 pub fn set_gpu_clock_type(&mut self, val: u32) {
9285 unsafe {
9286 let val: u32 = ::core::mem::transmute(val);
9287 self._bitfield_1.set(24usize, 8u8, val as u64)
9288 }
9289 }
9290 #[inline]
9291 pub unsafe fn gpu_clock_type_raw(this: *const Self) -> u32 {
9292 unsafe {
9293 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9294 ::core::ptr::addr_of!((*this)._bitfield_1),
9295 24usize,
9296 8u8,
9297 ) as u32)
9298 }
9299 }
9300 #[inline]
9301 pub unsafe fn set_gpu_clock_type_raw(this: *mut Self, val: u32) {
9302 unsafe {
9303 let val: u32 = ::core::mem::transmute(val);
9304 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9305 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9306 24usize,
9307 8u8,
9308 val as u64,
9309 )
9310 }
9311 }
9312 #[inline]
9313 pub fn new_bitfield_1(
9314 gpuclock_10khz: u32,
9315 gpu_clock_type: u32,
9316 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9317 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9318 __bindgen_bitfield_unit.set(0usize, 24u8, {
9319 let gpuclock_10khz: u32 = unsafe { ::core::mem::transmute(gpuclock_10khz) };
9320 gpuclock_10khz as u64
9321 });
9322 __bindgen_bitfield_unit.set(24usize, 8u8, {
9323 let gpu_clock_type: u32 = unsafe { ::core::mem::transmute(gpu_clock_type) };
9324 gpu_clock_type as u64
9325 });
9326 __bindgen_bitfield_unit
9327 }
9328}
9329#[repr(C, packed)]
9330#[derive(Debug, Copy, Clone)]
9331pub struct compute_gpu_clock_output_parameter_v1_8 {
9332 pub _bitfield_align_1: [u8; 0],
9333 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9334 pub pll_fb_mult: u32,
9335 pub pll_ss_fbsmult: u32,
9336 pub pll_ss_slew_frac: u16,
9337 pub pll_ss_enable: u8,
9338 pub reserved: u8,
9339 pub reserved1: [u32; 2usize],
9340}
9341impl compute_gpu_clock_output_parameter_v1_8 {
9342 #[inline]
9343 pub fn gpuclock_10khz(&self) -> u32 {
9344 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9345 }
9346 #[inline]
9347 pub fn set_gpuclock_10khz(&mut self, val: u32) {
9348 unsafe {
9349 let val: u32 = ::core::mem::transmute(val);
9350 self._bitfield_1.set(0usize, 24u8, val as u64)
9351 }
9352 }
9353 #[inline]
9354 pub unsafe fn gpuclock_10khz_raw(this: *const Self) -> u32 {
9355 unsafe {
9356 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9357 ::core::ptr::addr_of!((*this)._bitfield_1),
9358 0usize,
9359 24u8,
9360 ) as u32)
9361 }
9362 }
9363 #[inline]
9364 pub unsafe fn set_gpuclock_10khz_raw(this: *mut Self, val: u32) {
9365 unsafe {
9366 let val: u32 = ::core::mem::transmute(val);
9367 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9368 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9369 0usize,
9370 24u8,
9371 val as u64,
9372 )
9373 }
9374 }
9375 #[inline]
9376 pub fn dfs_did(&self) -> u32 {
9377 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9378 }
9379 #[inline]
9380 pub fn set_dfs_did(&mut self, val: u32) {
9381 unsafe {
9382 let val: u32 = ::core::mem::transmute(val);
9383 self._bitfield_1.set(24usize, 8u8, val as u64)
9384 }
9385 }
9386 #[inline]
9387 pub unsafe fn dfs_did_raw(this: *const Self) -> u32 {
9388 unsafe {
9389 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9390 ::core::ptr::addr_of!((*this)._bitfield_1),
9391 24usize,
9392 8u8,
9393 ) as u32)
9394 }
9395 }
9396 #[inline]
9397 pub unsafe fn set_dfs_did_raw(this: *mut Self, val: u32) {
9398 unsafe {
9399 let val: u32 = ::core::mem::transmute(val);
9400 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9401 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9402 24usize,
9403 8u8,
9404 val as u64,
9405 )
9406 }
9407 }
9408 #[inline]
9409 pub fn new_bitfield_1(
9410 gpuclock_10khz: u32,
9411 dfs_did: u32,
9412 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9413 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9414 __bindgen_bitfield_unit.set(0usize, 24u8, {
9415 let gpuclock_10khz: u32 = unsafe { ::core::mem::transmute(gpuclock_10khz) };
9416 gpuclock_10khz as u64
9417 });
9418 __bindgen_bitfield_unit.set(24usize, 8u8, {
9419 let dfs_did: u32 = unsafe { ::core::mem::transmute(dfs_did) };
9420 dfs_did as u64
9421 });
9422 __bindgen_bitfield_unit
9423 }
9424}
9425#[repr(C, packed)]
9426#[derive(Debug, Copy, Clone)]
9427pub struct read_efuse_input_parameters_v3_1 {
9428 pub efuse_start_index: u16,
9429 pub reserved: u8,
9430 pub bitslen: u8,
9431}
9432#[repr(C, packed)]
9433#[derive(Copy, Clone)]
9434pub union read_efuse_value_parameters_v3_1 {
9435 pub efuse_info: read_efuse_input_parameters_v3_1,
9436 pub efusevalue: u32,
9437}
9438#[repr(C)]
9439#[derive(Debug, Copy, Clone)]
9440pub struct atom_get_smu_clock_info_parameters_v3_1 {
9441 pub syspll_id: u8,
9442 pub clk_id: u8,
9443 pub command: u8,
9444 pub dfsdid: u8,
9445}
9446pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ:
9447 atom_get_smu_clock_info_command = 0;
9448pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ:
9449 atom_get_smu_clock_info_command = 1;
9450pub const atom_get_smu_clock_info_command_GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ:
9451 atom_get_smu_clock_info_command = 2;
9452pub type atom_get_smu_clock_info_command = ::core::ffi::c_uint;
9453pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_SMNCLK_ID: atom_smu9_syspll0_clock_id = 0;
9454pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_SOCCLK_ID: atom_smu9_syspll0_clock_id = 1;
9455pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_MP0CLK_ID: atom_smu9_syspll0_clock_id = 2;
9456pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_MP1CLK_ID: atom_smu9_syspll0_clock_id = 3;
9457pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_LCLK_ID: atom_smu9_syspll0_clock_id = 4;
9458pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DCLK_ID: atom_smu9_syspll0_clock_id = 5;
9459pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_VCLK_ID: atom_smu9_syspll0_clock_id = 6;
9460pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_ECLK_ID: atom_smu9_syspll0_clock_id = 7;
9461pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DCEFCLK_ID: atom_smu9_syspll0_clock_id = 8;
9462pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DPREFCLK_ID: atom_smu9_syspll0_clock_id = 10;
9463pub const atom_smu9_syspll0_clock_id_SMU9_SYSPLL0_DISPCLK_ID: atom_smu9_syspll0_clock_id = 11;
9464pub type atom_smu9_syspll0_clock_id = ::core::ffi::c_uint;
9465pub const atom_smu11_syspll_id_SMU11_SYSPLL0_ID: atom_smu11_syspll_id = 0;
9466pub const atom_smu11_syspll_id_SMU11_SYSPLL1_0_ID: atom_smu11_syspll_id = 1;
9467pub const atom_smu11_syspll_id_SMU11_SYSPLL1_1_ID: atom_smu11_syspll_id = 2;
9468pub const atom_smu11_syspll_id_SMU11_SYSPLL1_2_ID: atom_smu11_syspll_id = 3;
9469pub const atom_smu11_syspll_id_SMU11_SYSPLL2_ID: atom_smu11_syspll_id = 4;
9470pub const atom_smu11_syspll_id_SMU11_SYSPLL3_0_ID: atom_smu11_syspll_id = 5;
9471pub const atom_smu11_syspll_id_SMU11_SYSPLL3_1_ID: atom_smu11_syspll_id = 6;
9472pub type atom_smu11_syspll_id = ::core::ffi::c_uint;
9473pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_ECLK_ID: atom_smu11_syspll0_clock_id = 0;
9474pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_SOCCLK_ID: atom_smu11_syspll0_clock_id = 1;
9475pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_MP0CLK_ID: atom_smu11_syspll0_clock_id = 2;
9476pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_DCLK_ID: atom_smu11_syspll0_clock_id = 3;
9477pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_VCLK_ID: atom_smu11_syspll0_clock_id = 4;
9478pub const atom_smu11_syspll0_clock_id_SMU11_SYSPLL0_DCEFCLK_ID: atom_smu11_syspll0_clock_id = 5;
9479pub type atom_smu11_syspll0_clock_id = ::core::ffi::c_uint;
9480pub const atom_smu11_syspll1_0_clock_id_SMU11_SYSPLL1_0_UCLKA_ID: atom_smu11_syspll1_0_clock_id = 0;
9481pub type atom_smu11_syspll1_0_clock_id = ::core::ffi::c_uint;
9482pub const atom_smu11_syspll1_1_clock_id_SMU11_SYSPLL1_0_UCLKB_ID: atom_smu11_syspll1_1_clock_id = 0;
9483pub type atom_smu11_syspll1_1_clock_id = ::core::ffi::c_uint;
9484pub const atom_smu11_syspll1_2_clock_id_SMU11_SYSPLL1_0_FCLK_ID: atom_smu11_syspll1_2_clock_id = 0;
9485pub type atom_smu11_syspll1_2_clock_id = ::core::ffi::c_uint;
9486pub const atom_smu11_syspll2_clock_id_SMU11_SYSPLL2_GFXCLK_ID: atom_smu11_syspll2_clock_id = 0;
9487pub type atom_smu11_syspll2_clock_id = ::core::ffi::c_uint;
9488pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_WAFCLK_ID: atom_smu11_syspll3_0_clock_id =
9489 0;
9490pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_DISPCLK_ID: atom_smu11_syspll3_0_clock_id =
9491 1;
9492pub const atom_smu11_syspll3_0_clock_id_SMU11_SYSPLL3_0_DPREFCLK_ID: atom_smu11_syspll3_0_clock_id =
9493 2;
9494pub type atom_smu11_syspll3_0_clock_id = ::core::ffi::c_uint;
9495pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_MP1CLK_ID: atom_smu11_syspll3_1_clock_id =
9496 0;
9497pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_SMNCLK_ID: atom_smu11_syspll3_1_clock_id =
9498 1;
9499pub const atom_smu11_syspll3_1_clock_id_SMU11_SYSPLL3_1_LCLK_ID: atom_smu11_syspll3_1_clock_id = 2;
9500pub type atom_smu11_syspll3_1_clock_id = ::core::ffi::c_uint;
9501pub const atom_smu12_syspll_id_SMU12_SYSPLL0_ID: atom_smu12_syspll_id = 0;
9502pub const atom_smu12_syspll_id_SMU12_SYSPLL1_ID: atom_smu12_syspll_id = 1;
9503pub const atom_smu12_syspll_id_SMU12_SYSPLL2_ID: atom_smu12_syspll_id = 2;
9504pub const atom_smu12_syspll_id_SMU12_SYSPLL3_0_ID: atom_smu12_syspll_id = 3;
9505pub const atom_smu12_syspll_id_SMU12_SYSPLL3_1_ID: atom_smu12_syspll_id = 4;
9506pub type atom_smu12_syspll_id = ::core::ffi::c_uint;
9507pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SMNCLK_ID: atom_smu12_syspll0_clock_id = 0;
9508pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SOCCLK_ID: atom_smu12_syspll0_clock_id = 1;
9509pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP0CLK_ID: atom_smu12_syspll0_clock_id = 2;
9510pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP1CLK_ID: atom_smu12_syspll0_clock_id = 3;
9511pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_MP2CLK_ID: atom_smu12_syspll0_clock_id = 4;
9512pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_VCLK_ID: atom_smu12_syspll0_clock_id = 5;
9513pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_LCLK_ID: atom_smu12_syspll0_clock_id = 6;
9514pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_DCLK_ID: atom_smu12_syspll0_clock_id = 7;
9515pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_ACLK_ID: atom_smu12_syspll0_clock_id = 8;
9516pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_ISPCLK_ID: atom_smu12_syspll0_clock_id = 9;
9517pub const atom_smu12_syspll0_clock_id_SMU12_SYSPLL0_SHUBCLK_ID: atom_smu12_syspll0_clock_id = 10;
9518pub type atom_smu12_syspll0_clock_id = ::core::ffi::c_uint;
9519pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DISPCLK_ID: atom_smu12_syspll1_clock_id = 0;
9520pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DPPCLK_ID: atom_smu12_syspll1_clock_id = 1;
9521pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DPREFCLK_ID: atom_smu12_syspll1_clock_id = 2;
9522pub const atom_smu12_syspll1_clock_id_SMU12_SYSPLL1_DCFCLK_ID: atom_smu12_syspll1_clock_id = 3;
9523pub type atom_smu12_syspll1_clock_id = ::core::ffi::c_uint;
9524pub const atom_smu12_syspll2_clock_id_SMU12_SYSPLL2_Pre_GFXCLK_ID: atom_smu12_syspll2_clock_id = 0;
9525pub type atom_smu12_syspll2_clock_id = ::core::ffi::c_uint;
9526pub const atom_smu12_syspll3_0_clock_id_SMU12_SYSPLL3_0_FCLK_ID: atom_smu12_syspll3_0_clock_id = 0;
9527pub type atom_smu12_syspll3_0_clock_id = ::core::ffi::c_uint;
9528pub const atom_smu12_syspll3_1_clock_id_SMU12_SYSPLL3_1_UMCCLK_ID: atom_smu12_syspll3_1_clock_id =
9529 0;
9530pub type atom_smu12_syspll3_1_clock_id = ::core::ffi::c_uint;
9531#[repr(C)]
9532#[derive(Copy, Clone)]
9533pub struct atom_get_smu_clock_info_output_parameters_v3_1 {
9534 pub atom_smu_outputclkfreq: atom_get_smu_clock_info_output_parameters_v3_1__bindgen_ty_1,
9535}
9536#[repr(C, packed)]
9537#[derive(Copy, Clone)]
9538pub union atom_get_smu_clock_info_output_parameters_v3_1__bindgen_ty_1 {
9539 pub smu_clock_freq_hz: u32,
9540 pub syspllvcofreq_10khz: u32,
9541 pub sysspllrefclk_10khz: u32,
9542}
9543pub const atom_dynamic_memory_setting_command_COMPUTE_MEMORY_PLL_PARAM:
9544 atom_dynamic_memory_setting_command = 1;
9545pub const atom_dynamic_memory_setting_command_COMPUTE_ENGINE_PLL_PARAM:
9546 atom_dynamic_memory_setting_command = 2;
9547pub const atom_dynamic_memory_setting_command_ADJUST_MC_SETTING_PARAM:
9548 atom_dynamic_memory_setting_command = 3;
9549pub type atom_dynamic_memory_setting_command = ::core::ffi::c_uint;
9550#[repr(C, packed)]
9551#[derive(Debug, Copy, Clone)]
9552pub struct dynamic_mclk_settings_parameters_v2_1 {
9553 pub _bitfield_align_1: [u8; 0],
9554 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9555 pub reserved: u32,
9556}
9557impl dynamic_mclk_settings_parameters_v2_1 {
9558 #[inline]
9559 pub fn mclk_10khz(&self) -> u32 {
9560 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9561 }
9562 #[inline]
9563 pub fn set_mclk_10khz(&mut self, val: u32) {
9564 unsafe {
9565 let val: u32 = ::core::mem::transmute(val);
9566 self._bitfield_1.set(0usize, 24u8, val as u64)
9567 }
9568 }
9569 #[inline]
9570 pub unsafe fn mclk_10khz_raw(this: *const Self) -> u32 {
9571 unsafe {
9572 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9573 ::core::ptr::addr_of!((*this)._bitfield_1),
9574 0usize,
9575 24u8,
9576 ) as u32)
9577 }
9578 }
9579 #[inline]
9580 pub unsafe fn set_mclk_10khz_raw(this: *mut Self, val: u32) {
9581 unsafe {
9582 let val: u32 = ::core::mem::transmute(val);
9583 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9584 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9585 0usize,
9586 24u8,
9587 val as u64,
9588 )
9589 }
9590 }
9591 #[inline]
9592 pub fn command(&self) -> u32 {
9593 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9594 }
9595 #[inline]
9596 pub fn set_command(&mut self, val: u32) {
9597 unsafe {
9598 let val: u32 = ::core::mem::transmute(val);
9599 self._bitfield_1.set(24usize, 8u8, val as u64)
9600 }
9601 }
9602 #[inline]
9603 pub unsafe fn command_raw(this: *const Self) -> u32 {
9604 unsafe {
9605 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9606 ::core::ptr::addr_of!((*this)._bitfield_1),
9607 24usize,
9608 8u8,
9609 ) as u32)
9610 }
9611 }
9612 #[inline]
9613 pub unsafe fn set_command_raw(this: *mut Self, val: u32) {
9614 unsafe {
9615 let val: u32 = ::core::mem::transmute(val);
9616 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9617 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9618 24usize,
9619 8u8,
9620 val as u64,
9621 )
9622 }
9623 }
9624 #[inline]
9625 pub fn new_bitfield_1(mclk_10khz: u32, command: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9626 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9627 __bindgen_bitfield_unit.set(0usize, 24u8, {
9628 let mclk_10khz: u32 = unsafe { ::core::mem::transmute(mclk_10khz) };
9629 mclk_10khz as u64
9630 });
9631 __bindgen_bitfield_unit.set(24usize, 8u8, {
9632 let command: u32 = unsafe { ::core::mem::transmute(command) };
9633 command as u64
9634 });
9635 __bindgen_bitfield_unit
9636 }
9637}
9638#[repr(C, packed)]
9639#[derive(Debug, Copy, Clone)]
9640pub struct dynamic_sclk_settings_parameters_v2_1 {
9641 pub _bitfield_align_1: [u8; 0],
9642 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
9643 pub mclk_10khz: u32,
9644 pub reserved: u32,
9645}
9646impl dynamic_sclk_settings_parameters_v2_1 {
9647 #[inline]
9648 pub fn sclk_10khz(&self) -> u32 {
9649 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
9650 }
9651 #[inline]
9652 pub fn set_sclk_10khz(&mut self, val: u32) {
9653 unsafe {
9654 let val: u32 = ::core::mem::transmute(val);
9655 self._bitfield_1.set(0usize, 24u8, val as u64)
9656 }
9657 }
9658 #[inline]
9659 pub unsafe fn sclk_10khz_raw(this: *const Self) -> u32 {
9660 unsafe {
9661 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9662 ::core::ptr::addr_of!((*this)._bitfield_1),
9663 0usize,
9664 24u8,
9665 ) as u32)
9666 }
9667 }
9668 #[inline]
9669 pub unsafe fn set_sclk_10khz_raw(this: *mut Self, val: u32) {
9670 unsafe {
9671 let val: u32 = ::core::mem::transmute(val);
9672 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9673 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9674 0usize,
9675 24u8,
9676 val as u64,
9677 )
9678 }
9679 }
9680 #[inline]
9681 pub fn command(&self) -> u32 {
9682 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
9683 }
9684 #[inline]
9685 pub fn set_command(&mut self, val: u32) {
9686 unsafe {
9687 let val: u32 = ::core::mem::transmute(val);
9688 self._bitfield_1.set(24usize, 8u8, val as u64)
9689 }
9690 }
9691 #[inline]
9692 pub unsafe fn command_raw(this: *const Self) -> u32 {
9693 unsafe {
9694 ::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
9695 ::core::ptr::addr_of!((*this)._bitfield_1),
9696 24usize,
9697 8u8,
9698 ) as u32)
9699 }
9700 }
9701 #[inline]
9702 pub unsafe fn set_command_raw(this: *mut Self, val: u32) {
9703 unsafe {
9704 let val: u32 = ::core::mem::transmute(val);
9705 <__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
9706 ::core::ptr::addr_of_mut!((*this)._bitfield_1),
9707 24usize,
9708 8u8,
9709 val as u64,
9710 )
9711 }
9712 }
9713 #[inline]
9714 pub fn new_bitfield_1(sclk_10khz: u32, command: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
9715 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
9716 __bindgen_bitfield_unit.set(0usize, 24u8, {
9717 let sclk_10khz: u32 = unsafe { ::core::mem::transmute(sclk_10khz) };
9718 sclk_10khz as u64
9719 });
9720 __bindgen_bitfield_unit.set(24usize, 8u8, {
9721 let command: u32 = unsafe { ::core::mem::transmute(command) };
9722 command as u64
9723 });
9724 __bindgen_bitfield_unit
9725 }
9726}
9727#[repr(C)]
9728#[derive(Copy, Clone)]
9729pub union dynamic_memory_settings_parameters_v2_1 {
9730 pub mclk_setting: dynamic_mclk_settings_parameters_v2_1,
9731 pub sclk_setting: dynamic_sclk_settings_parameters_v2_1,
9732}
9733pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_REINIT:
9734 atom_umc6_0_ucode_function_call_enum_id = 0;
9735pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH:
9736 atom_umc6_0_ucode_function_call_enum_id = 1;
9737pub const atom_umc6_0_ucode_function_call_enum_id_UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH:
9738 atom_umc6_0_ucode_function_call_enum_id = 2;
9739pub type atom_umc6_0_ucode_function_call_enum_id = ::core::ffi::c_uint;
9740#[repr(C, packed)]
9741#[derive(Debug, Copy, Clone)]
9742pub struct memory_training_parameters_v2_1 {
9743 pub ucode_func_id: u8,
9744 pub ucode_reserved: [u8; 3usize],
9745 pub reserved: [u32; 5usize],
9746}
9747#[repr(C, packed)]
9748#[derive(Debug, Copy, Clone)]
9749pub struct set_pixel_clock_parameter_v1_7 {
9750 pub pixclk_100hz: u32,
9751 pub pll_id: u8,
9752 pub encoderobjid: u8,
9753 pub encoder_mode: u8,
9754 pub miscinfo: u8,
9755 pub crtc_id: u8,
9756 pub deep_color_ratio: u8,
9757 pub reserved1: [u8; 2usize],
9758 pub reserved2: u32,
9759}
9760pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL:
9761 atom_set_pixel_clock_v1_7_misc_info = 1;
9762pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_PROG_PHYPLL:
9763 atom_set_pixel_clock_v1_7_misc_info = 2;
9764pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_YUV420_MODE:
9765 atom_set_pixel_clock_v1_7_misc_info = 4;
9766pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN:
9767 atom_set_pixel_clock_v1_7_misc_info = 8;
9768pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC:
9769 atom_set_pixel_clock_v1_7_misc_info = 48;
9770pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN:
9771 atom_set_pixel_clock_v1_7_misc_info = 0;
9772pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE:
9773 atom_set_pixel_clock_v1_7_misc_info = 16;
9774pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK:
9775 atom_set_pixel_clock_v1_7_misc_info = 32;
9776pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD:
9777 atom_set_pixel_clock_v1_7_misc_info = 48;
9778pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE:
9779 atom_set_pixel_clock_v1_7_misc_info = 64;
9780pub const atom_set_pixel_clock_v1_7_misc_info_PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS:
9781 atom_set_pixel_clock_v1_7_misc_info = 128;
9782pub type atom_set_pixel_clock_v1_7_misc_info = ::core::ffi::c_uint;
9783pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS:
9784 atom_set_pixel_clock_v1_7_deepcolor_ratio = 0;
9785pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4:
9786 atom_set_pixel_clock_v1_7_deepcolor_ratio = 1;
9787pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2:
9788 atom_set_pixel_clock_v1_7_deepcolor_ratio = 2;
9789pub const atom_set_pixel_clock_v1_7_deepcolor_ratio_PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1:
9790 atom_set_pixel_clock_v1_7_deepcolor_ratio = 3;
9791pub type atom_set_pixel_clock_v1_7_deepcolor_ratio = ::core::ffi::c_uint;
9792#[repr(C, packed)]
9793#[derive(Debug, Copy, Clone)]
9794pub struct set_dce_clock_parameters_v2_1 {
9795 pub dceclk_10khz: u32,
9796 pub dceclktype: u8,
9797 pub dceclksrc: u8,
9798 pub dceclkflag: u8,
9799 pub crtc_id: u8,
9800}
9801pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_DISPCLK: atom_set_dce_clock_clock_type = 0;
9802pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_DPREFCLK: atom_set_dce_clock_clock_type = 1;
9803pub const atom_set_dce_clock_clock_type_DCE_CLOCK_TYPE_PIXELCLK: atom_set_dce_clock_clock_type = 2;
9804pub type atom_set_dce_clock_clock_type = ::core::ffi::c_uint;
9805pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK:
9806 atom_set_dce_clock_dprefclk_flag = 3;
9807pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA:
9808 atom_set_dce_clock_dprefclk_flag = 0;
9809pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK:
9810 atom_set_dce_clock_dprefclk_flag = 1;
9811pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE:
9812 atom_set_dce_clock_dprefclk_flag = 2;
9813pub const atom_set_dce_clock_dprefclk_flag_DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN:
9814 atom_set_dce_clock_dprefclk_flag = 3;
9815pub type atom_set_dce_clock_dprefclk_flag = ::core::ffi::c_uint;
9816pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK:
9817 atom_set_dce_clock_pixclk_flag = 3;
9818pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS:
9819 atom_set_dce_clock_pixclk_flag = 0;
9820pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4:
9821 atom_set_dce_clock_pixclk_flag = 1;
9822pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2:
9823 atom_set_dce_clock_pixclk_flag = 2;
9824pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1:
9825 atom_set_dce_clock_pixclk_flag = 3;
9826pub const atom_set_dce_clock_pixclk_flag_DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE:
9827 atom_set_dce_clock_pixclk_flag = 4;
9828pub type atom_set_dce_clock_pixclk_flag = ::core::ffi::c_uint;
9829#[repr(C, packed)]
9830#[derive(Debug, Copy, Clone)]
9831pub struct set_dce_clock_ps_allocation_v2_1 {
9832 pub param: set_dce_clock_parameters_v2_1,
9833 pub ulReserved: [u32; 2usize],
9834}
9835#[repr(C, packed)]
9836#[derive(Debug, Copy, Clone)]
9837pub struct blank_crtc_parameters {
9838 pub crtc_id: u8,
9839 pub blanking: u8,
9840 pub reserved: u16,
9841 pub reserved1: u32,
9842}
9843pub const atom_blank_crtc_command_ATOM_BLANKING: atom_blank_crtc_command = 1;
9844pub const atom_blank_crtc_command_ATOM_BLANKING_OFF: atom_blank_crtc_command = 0;
9845pub type atom_blank_crtc_command = ::core::ffi::c_uint;
9846#[repr(C)]
9847#[derive(Debug, Copy, Clone)]
9848pub struct enable_crtc_parameters {
9849 pub crtc_id: u8,
9850 pub enable: u8,
9851 pub padding: [u8; 2usize],
9852}
9853#[repr(C)]
9854#[derive(Debug, Copy, Clone)]
9855pub struct enable_disp_power_gating_parameters_v2_1 {
9856 pub disp_pipe_id: u8,
9857 pub enable: u8,
9858 pub padding: [u8; 2usize],
9859}
9860#[repr(C, packed)]
9861#[derive(Debug, Copy, Clone)]
9862pub struct enable_disp_power_gating_ps_allocation {
9863 pub param: enable_disp_power_gating_parameters_v2_1,
9864 pub ulReserved: [u32; 4usize],
9865}
9866#[repr(C, packed)]
9867#[derive(Debug, Copy, Clone)]
9868pub struct set_crtc_using_dtd_timing_parameters {
9869 pub h_size: u16,
9870 pub h_blanking_time: u16,
9871 pub v_size: u16,
9872 pub v_blanking_time: u16,
9873 pub h_syncoffset: u16,
9874 pub h_syncwidth: u16,
9875 pub v_syncoffset: u16,
9876 pub v_syncwidth: u16,
9877 pub modemiscinfo: u16,
9878 pub h_border: u8,
9879 pub v_border: u8,
9880 pub crtc_id: u8,
9881 pub encoder_mode: u8,
9882 pub padding: [u8; 2usize],
9883}
9884#[repr(C, packed)]
9885#[derive(Copy, Clone)]
9886pub struct process_i2c_channel_transaction_parameters {
9887 pub i2cspeed_khz: u8,
9888 pub regind_status: process_i2c_channel_transaction_parameters__bindgen_ty_1,
9889 pub i2c_data_out: u16,
9890 pub flag: u8,
9891 pub trans_bytes: u8,
9892 pub slave_addr: u8,
9893 pub i2c_id: u8,
9894}
9895#[repr(C)]
9896#[derive(Copy, Clone)]
9897pub union process_i2c_channel_transaction_parameters__bindgen_ty_1 {
9898 pub regindex: u8,
9899 pub status: u8,
9900}
9901pub const atom_process_i2c_flag_HW_I2C_WRITE: atom_process_i2c_flag = 1;
9902pub const atom_process_i2c_flag_HW_I2C_READ: atom_process_i2c_flag = 0;
9903pub const atom_process_i2c_flag_I2C_2BYTE_ADDR: atom_process_i2c_flag = 2;
9904pub const atom_process_i2c_flag_HW_I2C_SMBUS_BYTE_WR: atom_process_i2c_flag = 4;
9905pub type atom_process_i2c_flag = ::core::ffi::c_uint;
9906pub const atom_process_i2c_status_HW_ASSISTED_I2C_STATUS_FAILURE: atom_process_i2c_status = 2;
9907pub const atom_process_i2c_status_HW_ASSISTED_I2C_STATUS_SUCCESS: atom_process_i2c_status = 1;
9908pub type atom_process_i2c_status = ::core::ffi::c_uint;
9909#[repr(C, packed)]
9910#[derive(Copy, Clone)]
9911pub struct process_aux_channel_transaction_parameters_v1_2 {
9912 pub aux_request: u16,
9913 pub dataout: u16,
9914 pub channelid: u8,
9915 pub aux_status_delay: process_aux_channel_transaction_parameters_v1_2__bindgen_ty_1,
9916 pub dataout_len: u8,
9917 pub hpd_id: u8,
9918}
9919#[repr(C)]
9920#[derive(Copy, Clone)]
9921pub union process_aux_channel_transaction_parameters_v1_2__bindgen_ty_1 {
9922 pub reply_status: u8,
9923 pub aux_delay: u8,
9924}
9925#[repr(C)]
9926#[derive(Debug, Copy, Clone)]
9927pub struct select_crtc_source_parameters_v2_3 {
9928 pub crtc_id: u8,
9929 pub encoder_id: u8,
9930 pub encode_mode: u8,
9931 pub dst_bpc: u8,
9932}
9933pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DISABLE_DIG:
9934 atom_dig_encoder_control_action = 0;
9935pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_ENABLE_DIG:
9936 atom_dig_encoder_control_action = 1;
9937pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_START:
9938 atom_dig_encoder_control_action = 8;
9939pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1:
9940 atom_dig_encoder_control_action = 9;
9941pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2:
9942 atom_dig_encoder_control_action = 10;
9943pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3:
9944 atom_dig_encoder_control_action = 19;
9945pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE:
9946 atom_dig_encoder_control_action = 11;
9947pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_VIDEO_OFF:
9948 atom_dig_encoder_control_action = 12;
9949pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_VIDEO_ON:
9950 atom_dig_encoder_control_action = 13;
9951pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_SETUP_PANEL_MODE:
9952 atom_dig_encoder_control_action = 16;
9953pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4:
9954 atom_dig_encoder_control_action = 20;
9955pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_STREAM_SETUP:
9956 atom_dig_encoder_control_action = 15;
9957pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_LINK_SETUP:
9958 atom_dig_encoder_control_action = 17;
9959pub const atom_dig_encoder_control_action_ATOM_ENCODER_CMD_ENCODER_BLANK:
9960 atom_dig_encoder_control_action = 18;
9961pub type atom_dig_encoder_control_action = ::core::ffi::c_uint;
9962pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_DISABLE:
9963 atom_dig_encoder_control_panelmode = 0;
9964pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_ENABLE_eDP_MODE:
9965 atom_dig_encoder_control_panelmode = 1;
9966pub const atom_dig_encoder_control_panelmode_DP_PANEL_MODE_ENABLE_LVLINK_MODE:
9967 atom_dig_encoder_control_panelmode = 17;
9968pub type atom_dig_encoder_control_panelmode = ::core::ffi::c_uint;
9969pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER:
9970 atom_dig_encoder_control_v5_digid = 0;
9971pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER:
9972 atom_dig_encoder_control_v5_digid = 1;
9973pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER:
9974 atom_dig_encoder_control_v5_digid = 2;
9975pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER:
9976 atom_dig_encoder_control_v5_digid = 3;
9977pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER:
9978 atom_dig_encoder_control_v5_digid = 4;
9979pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER:
9980 atom_dig_encoder_control_v5_digid = 5;
9981pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER:
9982 atom_dig_encoder_control_v5_digid = 6;
9983pub const atom_dig_encoder_control_v5_digid_ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER:
9984 atom_dig_encoder_control_v5_digid = 7;
9985pub type atom_dig_encoder_control_v5_digid = ::core::ffi::c_uint;
9986#[repr(C, packed)]
9987#[derive(Debug, Copy, Clone)]
9988pub struct dig_encoder_stream_setup_parameters_v1_5 {
9989 pub digid: u8,
9990 pub action: u8,
9991 pub digmode: u8,
9992 pub lanenum: u8,
9993 pub pclk_10khz: u32,
9994 pub bitpercolor: u8,
9995 pub dplinkrate_270mhz: u8,
9996 pub reserved: [u8; 2usize],
9997}
9998#[repr(C)]
9999#[derive(Debug, Copy, Clone)]
10000pub struct dig_encoder_link_setup_parameters_v1_5 {
10001 pub digid: u8,
10002 pub action: u8,
10003 pub digmode: u8,
10004 pub lanenum: u8,
10005 pub symclk_10khz: u8,
10006 pub hpd_sel: u8,
10007 pub digfe_sel: u8,
10008 pub reserved: [u8; 2usize],
10009}
10010#[repr(C, packed)]
10011#[derive(Debug, Copy, Clone)]
10012pub struct dp_panel_mode_set_parameters_v1_5 {
10013 pub digid: u8,
10014 pub action: u8,
10015 pub panelmode: u8,
10016 pub reserved1: u8,
10017 pub reserved2: [u32; 2usize],
10018}
10019#[repr(C, packed)]
10020#[derive(Debug, Copy, Clone)]
10021pub struct dig_encoder_generic_cmd_parameters_v1_5 {
10022 pub digid: u8,
10023 pub action: u8,
10024 pub reserved1: [u8; 2usize],
10025 pub reserved2: [u32; 2usize],
10026}
10027#[repr(C)]
10028#[derive(Copy, Clone)]
10029pub union dig_encoder_control_parameters_v1_5 {
10030 pub cmd_param: dig_encoder_generic_cmd_parameters_v1_5,
10031 pub stream_param: dig_encoder_stream_setup_parameters_v1_5,
10032 pub link_param: dig_encoder_link_setup_parameters_v1_5,
10033 pub dppanel_param: dp_panel_mode_set_parameters_v1_5,
10034}
10035#[repr(C, packed)]
10036#[derive(Copy, Clone)]
10037pub struct dig_transmitter_control_parameters_v1_6 {
10038 pub phyid: u8,
10039 pub action: u8,
10040 pub mode_laneset: dig_transmitter_control_parameters_v1_6__bindgen_ty_1,
10041 pub lanenum: u8,
10042 pub symclk_10khz: u32,
10043 pub hpdsel: u8,
10044 pub digfe_sel: u8,
10045 pub connobj_id: u8,
10046 pub reserved: u8,
10047 pub reserved1: u32,
10048}
10049#[repr(C)]
10050#[derive(Copy, Clone)]
10051pub union dig_transmitter_control_parameters_v1_6__bindgen_ty_1 {
10052 pub digmode: u8,
10053 pub dplaneset: u8,
10054}
10055#[repr(C, packed)]
10056#[derive(Copy, Clone)]
10057pub struct dig_transmitter_control_ps_allocation_v1_6 {
10058 pub param: dig_transmitter_control_parameters_v1_6,
10059 pub reserved: [u32; 4usize],
10060}
10061pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_DISABLE:
10062 atom_dig_transmitter_control_action = 0;
10063pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_ENABLE:
10064 atom_dig_transmitter_control_action = 1;
10065pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_BLOFF:
10066 atom_dig_transmitter_control_action = 2;
10067pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_BLON:
10068 atom_dig_transmitter_control_action = 3;
10069pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL:
10070 atom_dig_transmitter_control_action = 4;
10071pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START:
10072 atom_dig_transmitter_control_action = 5;
10073pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP:
10074 atom_dig_transmitter_control_action = 6;
10075pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_INIT:
10076 atom_dig_transmitter_control_action = 7;
10077pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT:
10078 atom_dig_transmitter_control_action = 8;
10079pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT:
10080 atom_dig_transmitter_control_action = 9;
10081pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_SETUP:
10082 atom_dig_transmitter_control_action = 10;
10083pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH:
10084 atom_dig_transmitter_control_action = 11;
10085pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_POWER_ON:
10086 atom_dig_transmitter_control_action = 12;
10087pub const atom_dig_transmitter_control_action_ATOM_TRANSMITTER_ACTION_POWER_OFF:
10088 atom_dig_transmitter_control_action = 13;
10089pub type atom_dig_transmitter_control_action = ::core::ffi::c_uint;
10090pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGA_SEL:
10091 atom_dig_transmitter_control_digfe_sel = 1;
10092pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGB_SEL:
10093 atom_dig_transmitter_control_digfe_sel = 2;
10094pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGC_SEL:
10095 atom_dig_transmitter_control_digfe_sel = 4;
10096pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGD_SEL:
10097 atom_dig_transmitter_control_digfe_sel = 8;
10098pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGE_SEL:
10099 atom_dig_transmitter_control_digfe_sel = 16;
10100pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGF_SEL:
10101 atom_dig_transmitter_control_digfe_sel = 32;
10102pub const atom_dig_transmitter_control_digfe_sel_ATOM_TRANMSITTER_V6__DIGG_SEL:
10103 atom_dig_transmitter_control_digfe_sel = 64;
10104pub type atom_dig_transmitter_control_digfe_sel = ::core::ffi::c_uint;
10105pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_NO_HPD_SEL:
10106 atom_dig_transmitter_control_hpd_sel = 0;
10107pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD1_SEL:
10108 atom_dig_transmitter_control_hpd_sel = 1;
10109pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD2_SEL:
10110 atom_dig_transmitter_control_hpd_sel = 2;
10111pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD3_SEL:
10112 atom_dig_transmitter_control_hpd_sel = 3;
10113pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD4_SEL:
10114 atom_dig_transmitter_control_hpd_sel = 4;
10115pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD5_SEL:
10116 atom_dig_transmitter_control_hpd_sel = 5;
10117pub const atom_dig_transmitter_control_hpd_sel_ATOM_TRANSMITTER_V6_HPD6_SEL:
10118 atom_dig_transmitter_control_hpd_sel = 6;
10119pub type atom_dig_transmitter_control_hpd_sel = ::core::ffi::c_uint;
10120pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_4V:
10121 atom_dig_transmitter_control_dplaneset = 0;
10122pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_6V:
10123 atom_dig_transmitter_control_dplaneset = 1;
10124pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_0_8V:
10125 atom_dig_transmitter_control_dplaneset = 2;
10126pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__0DB_1_2V:
10127 atom_dig_transmitter_control_dplaneset = 3;
10128pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_4V:
10129 atom_dig_transmitter_control_dplaneset = 8;
10130pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_6V:
10131 atom_dig_transmitter_control_dplaneset = 9;
10132pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__3_5DB_0_8V:
10133 atom_dig_transmitter_control_dplaneset = 10;
10134pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__6DB_0_4V:
10135 atom_dig_transmitter_control_dplaneset = 16;
10136pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__6DB_0_6V:
10137 atom_dig_transmitter_control_dplaneset = 17;
10138pub const atom_dig_transmitter_control_dplaneset_DP_LANE_SET__9_5DB_0_4V:
10139 atom_dig_transmitter_control_dplaneset = 24;
10140pub type atom_dig_transmitter_control_dplaneset = ::core::ffi::c_uint;
10141#[repr(C, packed)]
10142#[derive(Debug, Copy, Clone)]
10143pub struct external_encoder_control_parameters_v2_4 {
10144 pub pixelclock_10khz: u16,
10145 pub config: u8,
10146 pub action: u8,
10147 pub encodermode: u8,
10148 pub lanenum: u8,
10149 pub bitpercolor: u8,
10150 pub hpd_id: u8,
10151}
10152pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT:
10153 external_encoder_control_action_def = 0;
10154pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT:
10155 external_encoder_control_action_def = 1;
10156pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT:
10157 external_encoder_control_action_def = 7;
10158pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP:
10159 external_encoder_control_action_def = 15;
10160pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF:
10161 external_encoder_control_action_def = 16;
10162pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING:
10163 external_encoder_control_action_def = 17;
10164pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION:
10165 external_encoder_control_action_def = 18;
10166pub const external_encoder_control_action_def_EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP:
10167 external_encoder_control_action_def = 20;
10168pub type external_encoder_control_action_def = ::core::ffi::c_uint;
10169pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK:
10170 external_encoder_control_v2_4_config_def = 3;
10171pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ:
10172 external_encoder_control_v2_4_config_def = 0;
10173pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ:
10174 external_encoder_control_v2_4_config_def = 1;
10175pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ:
10176 external_encoder_control_v2_4_config_def = 2;
10177pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ:
10178 external_encoder_control_v2_4_config_def = 3;
10179pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS:
10180 external_encoder_control_v2_4_config_def = 112;
10181pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER1:
10182 external_encoder_control_v2_4_config_def = 0;
10183pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER2:
10184 external_encoder_control_v2_4_config_def = 16;
10185pub const external_encoder_control_v2_4_config_def_EXTERNAL_ENCODER_CONFIG_V3_ENCODER3:
10186 external_encoder_control_v2_4_config_def = 32;
10187pub type external_encoder_control_v2_4_config_def = ::core::ffi::c_uint;
10188#[repr(C, packed)]
10189#[derive(Debug, Copy, Clone)]
10190pub struct external_encoder_control_ps_allocation_v2_4 {
10191 pub sExtEncoder: external_encoder_control_parameters_v2_4,
10192 pub reserved: [u32; 2usize],
10193}
10194#[repr(C, packed)]
10195#[derive(Debug, Copy, Clone)]
10196pub struct amd_acpi_description_header {
10197 pub signature: u32,
10198 pub tableLength: u32,
10199 pub revision: u8,
10200 pub checksum: u8,
10201 pub oemId: [u8; 6usize],
10202 pub oemTableId: [u8; 8usize],
10203 pub oemRevision: u32,
10204 pub creatorId: u32,
10205 pub creatorRevision: u32,
10206}
10207#[repr(C, packed)]
10208#[derive(Debug, Copy, Clone)]
10209pub struct uefi_acpi_vfct {
10210 pub sheader: amd_acpi_description_header,
10211 pub tableUUID: [u8; 16usize],
10212 pub vbiosimageoffset: u32,
10213 pub lib1Imageoffset: u32,
10214 pub reserved: [u32; 4usize],
10215}
10216#[repr(C, packed)]
10217#[derive(Debug, Copy, Clone)]
10218pub struct vfct_image_header {
10219 pub pcibus: u32,
10220 pub pcidevice: u32,
10221 pub pcifunction: u32,
10222 pub vendorid: u16,
10223 pub deviceid: u16,
10224 pub ssvid: u16,
10225 pub ssid: u16,
10226 pub revision: u32,
10227 pub imagelength: u32,
10228}
10229#[repr(C)]
10230#[derive(Debug, Copy, Clone)]
10231pub struct gop_vbios_content {
10232 pub vbiosheader: vfct_image_header,
10233 pub vbioscontent: [u8; 1usize],
10234}
10235#[repr(C)]
10236#[derive(Debug, Copy, Clone)]
10237pub struct gop_lib1_content {
10238 pub lib1header: vfct_image_header,
10239 pub lib1content: [u8; 1usize],
10240}
10241pub const scratch_register_def_ATOM_DEVICE_CONNECT_INFO_DEF: scratch_register_def = 0;
10242pub const scratch_register_def_ATOM_BL_BRI_LEVEL_INFO_DEF: scratch_register_def = 2;
10243pub const scratch_register_def_ATOM_ACTIVE_INFO_DEF: scratch_register_def = 3;
10244pub const scratch_register_def_ATOM_LCD_INFO_DEF: scratch_register_def = 4;
10245pub const scratch_register_def_ATOM_DEVICE_REQ_INFO_DEF: scratch_register_def = 5;
10246pub const scratch_register_def_ATOM_ACC_CHANGE_INFO_DEF: scratch_register_def = 6;
10247pub const scratch_register_def_ATOM_PRE_OS_MODE_INFO_DEF: scratch_register_def = 7;
10248pub const scratch_register_def_ATOM_PRE_OS_ASSERTION_DEF: scratch_register_def = 8;
10249pub const scratch_register_def_ATOM_INTERNAL_TIMER_INFO_DEF: scratch_register_def = 10;
10250pub type scratch_register_def = ::core::ffi::c_uint;
10251pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_LCD1_CONNECT:
10252 scratch_device_connect_info_bit_def = 2;
10253pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP1_CONNECT:
10254 scratch_device_connect_info_bit_def = 8;
10255pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP2_CONNECT:
10256 scratch_device_connect_info_bit_def = 128;
10257pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP3_CONNECT:
10258 scratch_device_connect_info_bit_def = 512;
10259pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP4_CONNECT:
10260 scratch_device_connect_info_bit_def = 1024;
10261pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP5_CONNECT:
10262 scratch_device_connect_info_bit_def = 2048;
10263pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFP6_CONNECT:
10264 scratch_device_connect_info_bit_def = 64;
10265pub const scratch_device_connect_info_bit_def_ATOM_DISPLAY_DFPx_CONNECT:
10266 scratch_device_connect_info_bit_def = 3784;
10267pub const scratch_device_connect_info_bit_def_ATOM_CONNECT_INFO_DEVICE_MASK:
10268 scratch_device_connect_info_bit_def = 4095;
10269pub type scratch_device_connect_info_bit_def = ::core::ffi::c_uint;
10270pub const scratch_bl_bri_level_info_bit_def_ATOM_CURRENT_BL_LEVEL_SHIFT:
10271 scratch_bl_bri_level_info_bit_def = 8;
10272pub const scratch_bl_bri_level_info_bit_def_ATOM_CURRENT_BL_LEVEL_MASK:
10273 scratch_bl_bri_level_info_bit_def = 65280;
10274pub const scratch_bl_bri_level_info_bit_def_ATOM_DEVICE_DPMS_STATE:
10275 scratch_bl_bri_level_info_bit_def = 65536;
10276pub type scratch_bl_bri_level_info_bit_def = ::core::ffi::c_uint;
10277pub const scratch_active_info_bits_def_ATOM_DISPLAY_LCD1_ACTIVE: scratch_active_info_bits_def = 2;
10278pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP1_ACTIVE: scratch_active_info_bits_def = 8;
10279pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP2_ACTIVE: scratch_active_info_bits_def = 128;
10280pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP3_ACTIVE: scratch_active_info_bits_def = 512;
10281pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP4_ACTIVE: scratch_active_info_bits_def =
10282 1024;
10283pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP5_ACTIVE: scratch_active_info_bits_def =
10284 2048;
10285pub const scratch_active_info_bits_def_ATOM_DISPLAY_DFP6_ACTIVE: scratch_active_info_bits_def = 64;
10286pub const scratch_active_info_bits_def_ATOM_ACTIVE_INFO_DEVICE_MASK: scratch_active_info_bits_def =
10287 4095;
10288pub type scratch_active_info_bits_def = ::core::ffi::c_uint;
10289pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_LCD1_REQ: scratch_device_req_info_bits_def =
10290 2;
10291pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP1_REQ: scratch_device_req_info_bits_def =
10292 8;
10293pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP2_REQ: scratch_device_req_info_bits_def =
10294 128;
10295pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP3_REQ: scratch_device_req_info_bits_def =
10296 512;
10297pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP4_REQ: scratch_device_req_info_bits_def =
10298 1024;
10299pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP5_REQ: scratch_device_req_info_bits_def =
10300 2048;
10301pub const scratch_device_req_info_bits_def_ATOM_DISPLAY_DFP6_REQ: scratch_device_req_info_bits_def =
10302 64;
10303pub const scratch_device_req_info_bits_def_ATOM_REQ_INFO_DEVICE_MASK:
10304 scratch_device_req_info_bits_def = 4095;
10305pub type scratch_device_req_info_bits_def = ::core::ffi::c_uint;
10306pub const scratch_acc_change_info_bitshift_def_ATOM_ACC_CHANGE_ACC_MODE_SHIFT:
10307 scratch_acc_change_info_bitshift_def = 4;
10308pub const scratch_acc_change_info_bitshift_def_ATOM_ACC_CHANGE_LID_STATUS_SHIFT:
10309 scratch_acc_change_info_bitshift_def = 6;
10310pub type scratch_acc_change_info_bitshift_def = ::core::ffi::c_uint;
10311pub const scratch_acc_change_info_bits_def_ATOM_ACC_CHANGE_ACC_MODE:
10312 scratch_acc_change_info_bits_def = 16;
10313pub const scratch_acc_change_info_bits_def_ATOM_ACC_CHANGE_LID_STATUS:
10314 scratch_acc_change_info_bits_def = 64;
10315pub type scratch_acc_change_info_bits_def = ::core::ffi::c_uint;
10316pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_MASK:
10317 scratch_pre_os_mode_info_bits_def = 3;
10318pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_VGA:
10319 scratch_pre_os_mode_info_bits_def = 0;
10320pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_VESA:
10321 scratch_pre_os_mode_info_bits_def = 1;
10322pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_GOP:
10323 scratch_pre_os_mode_info_bits_def = 2;
10324pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_PIXEL_DEPTH:
10325 scratch_pre_os_mode_info_bits_def = 12;
10326pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK:
10327 scratch_pre_os_mode_info_bits_def = 240;
10328pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_8BIT_PAL_EN:
10329 scratch_pre_os_mode_info_bits_def = 256;
10330pub const scratch_pre_os_mode_info_bits_def_ATOM_ASIC_INIT_COMPLETE:
10331 scratch_pre_os_mode_info_bits_def = 512;
10332pub const scratch_pre_os_mode_info_bits_def_ATOM_PRE_OS_MODE_NUMBER_MASK:
10333 scratch_pre_os_mode_info_bits_def = 4294901760;
10334pub type scratch_pre_os_mode_info_bits_def = ::core::ffi::c_uint;
10335pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UTILITY_PIPELINE: atom_master_data_table_id =
10336 0;
10337pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__MULTIMEDIA_INF: atom_master_data_table_id =
10338 1;
10339pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__FIRMWARE_INF: atom_master_data_table_id = 2;
10340pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__LCD_INF: atom_master_data_table_id = 3;
10341pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__SMU_INF: atom_master_data_table_id = 4;
10342pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE:
10343 atom_master_data_table_id = 5;
10344pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__GPIO_PIN_LUT: atom_master_data_table_id = 6;
10345pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__GFX_INF: atom_master_data_table_id = 7;
10346pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__POWER_PLAY_INF: atom_master_data_table_id =
10347 8;
10348pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF:
10349 atom_master_data_table_id = 9;
10350pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS:
10351 atom_master_data_table_id = 10;
10352pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UMC_INF: atom_master_data_table_id = 11;
10353pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__DCE_INF: atom_master_data_table_id = 12;
10354pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VRAM_INF: atom_master_data_table_id = 13;
10355pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF:
10356 atom_master_data_table_id = 14;
10357pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF:
10358 atom_master_data_table_id = 15;
10359pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF: atom_master_data_table_id =
10360 16;
10361pub const atom_master_data_table_id_VBIOS_DATA_TBL_ID__UNDEFINED: atom_master_data_table_id = 17;
10362pub type atom_master_data_table_id = ::core::ffi::c_uint;
10363pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ASIC_INIT: atom_master_command_table_id =
10364 0;
10365pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL:
10366 atom_master_command_table_id = 1;
10367pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK:
10368 atom_master_command_table_id = 2;
10369pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK:
10370 atom_master_command_table_id = 3;
10371pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK:
10372 atom_master_command_table_id = 4;
10373pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING:
10374 atom_master_command_table_id = 5;
10375pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__BLANK_CRTC: atom_master_command_table_id =
10376 6;
10377pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__ENABLE_CRTC: atom_master_command_table_id =
10378 7;
10379pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO:
10380 atom_master_command_table_id = 8;
10381pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE:
10382 atom_master_command_table_id = 9;
10383pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_DCE_CLOCK:
10384 atom_master_command_table_id = 10;
10385pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK:
10386 atom_master_command_table_id = 11;
10387pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK:
10388 atom_master_command_table_id = 12;
10389pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING:
10390 atom_master_command_table_id = 13;
10391pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL:
10392 atom_master_command_table_id = 14;
10393pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION:
10394 atom_master_command_table_id = 15;
10395pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM:
10396 atom_master_command_table_id = 16;
10397pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS:
10398 atom_master_command_table_id = 17;
10399pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__MEMORY_TRAINING:
10400 atom_master_command_table_id = 18;
10401pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__SET_VOLTAGE: atom_master_command_table_id =
10402 19;
10403pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL:
10404 atom_master_command_table_id = 20;
10405pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION:
10406 atom_master_command_table_id = 21;
10407pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF:
10408 atom_master_command_table_id = 22;
10409pub const atom_master_command_table_id_VBIOS_CMD_TBL_ID__UNDEFINED: atom_master_command_table_id =
10410 23;
10411pub type atom_master_command_table_id = ::core::ffi::c_uint;
10412#[repr(C)]
10413#[derive(Debug, Copy, Clone)]
10414pub struct metrics_table_header {
10415 pub structure_size: u16,
10416 pub format_revision: u8,
10417 pub content_revision: u8,
10418}
10419#[repr(C)]
10420#[derive(Debug, Copy, Clone)]
10421pub struct gpu_metrics_v1_0 {
10422 pub common_header: metrics_table_header,
10423 pub system_clock_counter: u64,
10424 pub temperature_edge: u16,
10425 pub temperature_hotspot: u16,
10426 pub temperature_mem: u16,
10427 pub temperature_vrgfx: u16,
10428 pub temperature_vrsoc: u16,
10429 pub temperature_vrmem: u16,
10430 pub average_gfx_activity: u16,
10431 pub average_umc_activity: u16,
10432 pub average_mm_activity: u16,
10433 pub average_socket_power: u16,
10434 pub energy_accumulator: u32,
10435 pub average_gfxclk_frequency: u16,
10436 pub average_socclk_frequency: u16,
10437 pub average_uclk_frequency: u16,
10438 pub average_vclk0_frequency: u16,
10439 pub average_dclk0_frequency: u16,
10440 pub average_vclk1_frequency: u16,
10441 pub average_dclk1_frequency: u16,
10442 pub current_gfxclk: u16,
10443 pub current_socclk: u16,
10444 pub current_uclk: u16,
10445 pub current_vclk0: u16,
10446 pub current_dclk0: u16,
10447 pub current_vclk1: u16,
10448 pub current_dclk1: u16,
10449 pub throttle_status: u32,
10450 pub current_fan_speed: u16,
10451 pub pcie_link_width: u8,
10452 pub pcie_link_speed: u8,
10453}
10454#[repr(C)]
10455#[derive(Debug, Copy, Clone)]
10456pub struct gpu_metrics_v1_1 {
10457 pub common_header: metrics_table_header,
10458 pub temperature_edge: u16,
10459 pub temperature_hotspot: u16,
10460 pub temperature_mem: u16,
10461 pub temperature_vrgfx: u16,
10462 pub temperature_vrsoc: u16,
10463 pub temperature_vrmem: u16,
10464 pub average_gfx_activity: u16,
10465 pub average_umc_activity: u16,
10466 pub average_mm_activity: u16,
10467 pub average_socket_power: u16,
10468 pub energy_accumulator: u64,
10469 pub system_clock_counter: u64,
10470 pub average_gfxclk_frequency: u16,
10471 pub average_socclk_frequency: u16,
10472 pub average_uclk_frequency: u16,
10473 pub average_vclk0_frequency: u16,
10474 pub average_dclk0_frequency: u16,
10475 pub average_vclk1_frequency: u16,
10476 pub average_dclk1_frequency: u16,
10477 pub current_gfxclk: u16,
10478 pub current_socclk: u16,
10479 pub current_uclk: u16,
10480 pub current_vclk0: u16,
10481 pub current_dclk0: u16,
10482 pub current_vclk1: u16,
10483 pub current_dclk1: u16,
10484 pub throttle_status: u32,
10485 pub current_fan_speed: u16,
10486 pub pcie_link_width: u16,
10487 pub pcie_link_speed: u16,
10488 pub padding: u16,
10489 pub gfx_activity_acc: u32,
10490 pub mem_activity_acc: u32,
10491 pub temperature_hbm: [u16; 4usize],
10492}
10493#[repr(C)]
10494#[derive(Debug, Copy, Clone)]
10495pub struct gpu_metrics_v1_2 {
10496 pub common_header: metrics_table_header,
10497 pub temperature_edge: u16,
10498 pub temperature_hotspot: u16,
10499 pub temperature_mem: u16,
10500 pub temperature_vrgfx: u16,
10501 pub temperature_vrsoc: u16,
10502 pub temperature_vrmem: u16,
10503 pub average_gfx_activity: u16,
10504 pub average_umc_activity: u16,
10505 pub average_mm_activity: u16,
10506 pub average_socket_power: u16,
10507 pub energy_accumulator: u64,
10508 pub system_clock_counter: u64,
10509 pub average_gfxclk_frequency: u16,
10510 pub average_socclk_frequency: u16,
10511 pub average_uclk_frequency: u16,
10512 pub average_vclk0_frequency: u16,
10513 pub average_dclk0_frequency: u16,
10514 pub average_vclk1_frequency: u16,
10515 pub average_dclk1_frequency: u16,
10516 pub current_gfxclk: u16,
10517 pub current_socclk: u16,
10518 pub current_uclk: u16,
10519 pub current_vclk0: u16,
10520 pub current_dclk0: u16,
10521 pub current_vclk1: u16,
10522 pub current_dclk1: u16,
10523 pub throttle_status: u32,
10524 pub current_fan_speed: u16,
10525 pub pcie_link_width: u16,
10526 pub pcie_link_speed: u16,
10527 pub padding: u16,
10528 pub gfx_activity_acc: u32,
10529 pub mem_activity_acc: u32,
10530 pub temperature_hbm: [u16; 4usize],
10531 pub firmware_timestamp: u64,
10532}
10533#[repr(C)]
10534#[derive(Debug, Copy, Clone)]
10535pub struct gpu_metrics_v1_3 {
10536 pub common_header: metrics_table_header,
10537 pub temperature_edge: u16,
10538 pub temperature_hotspot: u16,
10539 pub temperature_mem: u16,
10540 pub temperature_vrgfx: u16,
10541 pub temperature_vrsoc: u16,
10542 pub temperature_vrmem: u16,
10543 pub average_gfx_activity: u16,
10544 pub average_umc_activity: u16,
10545 pub average_mm_activity: u16,
10546 pub average_socket_power: u16,
10547 pub energy_accumulator: u64,
10548 pub system_clock_counter: u64,
10549 pub average_gfxclk_frequency: u16,
10550 pub average_socclk_frequency: u16,
10551 pub average_uclk_frequency: u16,
10552 pub average_vclk0_frequency: u16,
10553 pub average_dclk0_frequency: u16,
10554 pub average_vclk1_frequency: u16,
10555 pub average_dclk1_frequency: u16,
10556 pub current_gfxclk: u16,
10557 pub current_socclk: u16,
10558 pub current_uclk: u16,
10559 pub current_vclk0: u16,
10560 pub current_dclk0: u16,
10561 pub current_vclk1: u16,
10562 pub current_dclk1: u16,
10563 pub throttle_status: u32,
10564 pub current_fan_speed: u16,
10565 pub pcie_link_width: u16,
10566 pub pcie_link_speed: u16,
10567 pub padding: u16,
10568 pub gfx_activity_acc: u32,
10569 pub mem_activity_acc: u32,
10570 pub temperature_hbm: [u16; 4usize],
10571 pub firmware_timestamp: u64,
10572 pub voltage_soc: u16,
10573 pub voltage_gfx: u16,
10574 pub voltage_mem: u16,
10575 pub padding1: u16,
10576 pub indep_throttle_status: u64,
10577}
10578#[repr(C)]
10579#[derive(Debug, Copy, Clone)]
10580pub struct gpu_metrics_v1_4 {
10581 pub common_header: metrics_table_header,
10582 pub temperature_hotspot: u16,
10583 pub temperature_mem: u16,
10584 pub temperature_vrsoc: u16,
10585 pub curr_socket_power: u16,
10586 pub average_gfx_activity: u16,
10587 pub average_umc_activity: u16,
10588 pub vcn_activity: [u16; 4usize],
10589 pub energy_accumulator: u64,
10590 pub system_clock_counter: u64,
10591 pub throttle_status: u32,
10592 pub gfxclk_lock_status: u32,
10593 pub pcie_link_width: u16,
10594 pub pcie_link_speed: u16,
10595 pub xgmi_link_width: u16,
10596 pub xgmi_link_speed: u16,
10597 pub gfx_activity_acc: u32,
10598 pub mem_activity_acc: u32,
10599 pub pcie_bandwidth_acc: u64,
10600 pub pcie_bandwidth_inst: u64,
10601 pub pcie_l0_to_recov_count_acc: u64,
10602 pub pcie_replay_count_acc: u64,
10603 pub pcie_replay_rover_count_acc: u64,
10604 pub xgmi_read_data_acc: [u64; 8usize],
10605 pub xgmi_write_data_acc: [u64; 8usize],
10606 pub firmware_timestamp: u64,
10607 pub current_gfxclk: [u16; 8usize],
10608 pub current_socclk: [u16; 4usize],
10609 pub current_vclk0: [u16; 4usize],
10610 pub current_dclk0: [u16; 4usize],
10611 pub current_uclk: u16,
10612 pub padding: u16,
10613}
10614#[repr(C)]
10615#[derive(Debug, Copy, Clone)]
10616pub struct gpu_metrics_v1_5 {
10617 pub common_header: metrics_table_header,
10618 pub temperature_hotspot: u16,
10619 pub temperature_mem: u16,
10620 pub temperature_vrsoc: u16,
10621 pub curr_socket_power: u16,
10622 pub average_gfx_activity: u16,
10623 pub average_umc_activity: u16,
10624 pub vcn_activity: [u16; 4usize],
10625 pub jpeg_activity: [u16; 32usize],
10626 pub energy_accumulator: u64,
10627 pub system_clock_counter: u64,
10628 pub throttle_status: u32,
10629 pub gfxclk_lock_status: u32,
10630 pub pcie_link_width: u16,
10631 pub pcie_link_speed: u16,
10632 pub xgmi_link_width: u16,
10633 pub xgmi_link_speed: u16,
10634 pub gfx_activity_acc: u32,
10635 pub mem_activity_acc: u32,
10636 pub pcie_bandwidth_acc: u64,
10637 pub pcie_bandwidth_inst: u64,
10638 pub pcie_l0_to_recov_count_acc: u64,
10639 pub pcie_replay_count_acc: u64,
10640 pub pcie_replay_rover_count_acc: u64,
10641 pub pcie_nak_sent_count_acc: u32,
10642 pub pcie_nak_rcvd_count_acc: u32,
10643 pub xgmi_read_data_acc: [u64; 8usize],
10644 pub xgmi_write_data_acc: [u64; 8usize],
10645 pub firmware_timestamp: u64,
10646 pub current_gfxclk: [u16; 8usize],
10647 pub current_socclk: [u16; 4usize],
10648 pub current_vclk0: [u16; 4usize],
10649 pub current_dclk0: [u16; 4usize],
10650 pub current_uclk: u16,
10651 pub padding: u16,
10652}
10653#[repr(C)]
10654#[derive(Debug, Copy, Clone)]
10655pub struct gpu_metrics_v2_0 {
10656 pub common_header: metrics_table_header,
10657 pub system_clock_counter: u64,
10658 pub temperature_gfx: u16,
10659 pub temperature_soc: u16,
10660 pub temperature_core: [u16; 8usize],
10661 pub temperature_l3: [u16; 2usize],
10662 pub average_gfx_activity: u16,
10663 pub average_mm_activity: u16,
10664 pub average_socket_power: u16,
10665 pub average_cpu_power: u16,
10666 pub average_soc_power: u16,
10667 pub average_gfx_power: u16,
10668 pub average_core_power: [u16; 8usize],
10669 pub average_gfxclk_frequency: u16,
10670 pub average_socclk_frequency: u16,
10671 pub average_uclk_frequency: u16,
10672 pub average_fclk_frequency: u16,
10673 pub average_vclk_frequency: u16,
10674 pub average_dclk_frequency: u16,
10675 pub current_gfxclk: u16,
10676 pub current_socclk: u16,
10677 pub current_uclk: u16,
10678 pub current_fclk: u16,
10679 pub current_vclk: u16,
10680 pub current_dclk: u16,
10681 pub current_coreclk: [u16; 8usize],
10682 pub current_l3clk: [u16; 2usize],
10683 pub throttle_status: u32,
10684 pub fan_pwm: u16,
10685 pub padding: u16,
10686}
10687#[repr(C)]
10688#[derive(Debug, Copy, Clone)]
10689pub struct gpu_metrics_v2_1 {
10690 pub common_header: metrics_table_header,
10691 pub temperature_gfx: u16,
10692 pub temperature_soc: u16,
10693 pub temperature_core: [u16; 8usize],
10694 pub temperature_l3: [u16; 2usize],
10695 pub average_gfx_activity: u16,
10696 pub average_mm_activity: u16,
10697 pub system_clock_counter: u64,
10698 pub average_socket_power: u16,
10699 pub average_cpu_power: u16,
10700 pub average_soc_power: u16,
10701 pub average_gfx_power: u16,
10702 pub average_core_power: [u16; 8usize],
10703 pub average_gfxclk_frequency: u16,
10704 pub average_socclk_frequency: u16,
10705 pub average_uclk_frequency: u16,
10706 pub average_fclk_frequency: u16,
10707 pub average_vclk_frequency: u16,
10708 pub average_dclk_frequency: u16,
10709 pub current_gfxclk: u16,
10710 pub current_socclk: u16,
10711 pub current_uclk: u16,
10712 pub current_fclk: u16,
10713 pub current_vclk: u16,
10714 pub current_dclk: u16,
10715 pub current_coreclk: [u16; 8usize],
10716 pub current_l3clk: [u16; 2usize],
10717 pub throttle_status: u32,
10718 pub fan_pwm: u16,
10719 pub padding: [u16; 3usize],
10720}
10721#[repr(C)]
10722#[derive(Debug, Copy, Clone)]
10723pub struct gpu_metrics_v2_2 {
10724 pub common_header: metrics_table_header,
10725 pub temperature_gfx: u16,
10726 pub temperature_soc: u16,
10727 pub temperature_core: [u16; 8usize],
10728 pub temperature_l3: [u16; 2usize],
10729 pub average_gfx_activity: u16,
10730 pub average_mm_activity: u16,
10731 pub system_clock_counter: u64,
10732 pub average_socket_power: u16,
10733 pub average_cpu_power: u16,
10734 pub average_soc_power: u16,
10735 pub average_gfx_power: u16,
10736 pub average_core_power: [u16; 8usize],
10737 pub average_gfxclk_frequency: u16,
10738 pub average_socclk_frequency: u16,
10739 pub average_uclk_frequency: u16,
10740 pub average_fclk_frequency: u16,
10741 pub average_vclk_frequency: u16,
10742 pub average_dclk_frequency: u16,
10743 pub current_gfxclk: u16,
10744 pub current_socclk: u16,
10745 pub current_uclk: u16,
10746 pub current_fclk: u16,
10747 pub current_vclk: u16,
10748 pub current_dclk: u16,
10749 pub current_coreclk: [u16; 8usize],
10750 pub current_l3clk: [u16; 2usize],
10751 pub throttle_status: u32,
10752 pub fan_pwm: u16,
10753 pub padding: [u16; 3usize],
10754 pub indep_throttle_status: u64,
10755}
10756#[repr(C)]
10757#[derive(Debug, Copy, Clone)]
10758pub struct gpu_metrics_v2_3 {
10759 pub common_header: metrics_table_header,
10760 pub temperature_gfx: u16,
10761 pub temperature_soc: u16,
10762 pub temperature_core: [u16; 8usize],
10763 pub temperature_l3: [u16; 2usize],
10764 pub average_gfx_activity: u16,
10765 pub average_mm_activity: u16,
10766 pub system_clock_counter: u64,
10767 pub average_socket_power: u16,
10768 pub average_cpu_power: u16,
10769 pub average_soc_power: u16,
10770 pub average_gfx_power: u16,
10771 pub average_core_power: [u16; 8usize],
10772 pub average_gfxclk_frequency: u16,
10773 pub average_socclk_frequency: u16,
10774 pub average_uclk_frequency: u16,
10775 pub average_fclk_frequency: u16,
10776 pub average_vclk_frequency: u16,
10777 pub average_dclk_frequency: u16,
10778 pub current_gfxclk: u16,
10779 pub current_socclk: u16,
10780 pub current_uclk: u16,
10781 pub current_fclk: u16,
10782 pub current_vclk: u16,
10783 pub current_dclk: u16,
10784 pub current_coreclk: [u16; 8usize],
10785 pub current_l3clk: [u16; 2usize],
10786 pub throttle_status: u32,
10787 pub fan_pwm: u16,
10788 pub padding: [u16; 3usize],
10789 pub indep_throttle_status: u64,
10790 pub average_temperature_gfx: u16,
10791 pub average_temperature_soc: u16,
10792 pub average_temperature_core: [u16; 8usize],
10793 pub average_temperature_l3: [u16; 2usize],
10794}
10795#[repr(C)]
10796#[derive(Debug, Copy, Clone)]
10797pub struct gpu_metrics_v2_4 {
10798 pub common_header: metrics_table_header,
10799 pub temperature_gfx: u16,
10800 pub temperature_soc: u16,
10801 pub temperature_core: [u16; 8usize],
10802 pub temperature_l3: [u16; 2usize],
10803 pub average_gfx_activity: u16,
10804 pub average_mm_activity: u16,
10805 pub system_clock_counter: u64,
10806 pub average_socket_power: u16,
10807 pub average_cpu_power: u16,
10808 pub average_soc_power: u16,
10809 pub average_gfx_power: u16,
10810 pub average_core_power: [u16; 8usize],
10811 pub average_gfxclk_frequency: u16,
10812 pub average_socclk_frequency: u16,
10813 pub average_uclk_frequency: u16,
10814 pub average_fclk_frequency: u16,
10815 pub average_vclk_frequency: u16,
10816 pub average_dclk_frequency: u16,
10817 pub current_gfxclk: u16,
10818 pub current_socclk: u16,
10819 pub current_uclk: u16,
10820 pub current_fclk: u16,
10821 pub current_vclk: u16,
10822 pub current_dclk: u16,
10823 pub current_coreclk: [u16; 8usize],
10824 pub current_l3clk: [u16; 2usize],
10825 pub throttle_status: u32,
10826 pub fan_pwm: u16,
10827 pub padding: [u16; 3usize],
10828 pub indep_throttle_status: u64,
10829 pub average_temperature_gfx: u16,
10830 pub average_temperature_soc: u16,
10831 pub average_temperature_core: [u16; 8usize],
10832 pub average_temperature_l3: [u16; 2usize],
10833 pub average_cpu_voltage: u16,
10834 pub average_soc_voltage: u16,
10835 pub average_gfx_voltage: u16,
10836 pub average_cpu_current: u16,
10837 pub average_soc_current: u16,
10838 pub average_gfx_current: u16,
10839}
10840#[repr(C)]
10841#[derive(Debug, Copy, Clone)]
10842pub struct gpu_metrics_v3_0 {
10843 pub common_header: metrics_table_header,
10844 pub temperature_gfx: u16,
10845 pub temperature_soc: u16,
10846 pub temperature_core: [u16; 16usize],
10847 pub temperature_skin: u16,
10848 pub average_gfx_activity: u16,
10849 pub average_vcn_activity: u16,
10850 pub average_ipu_activity: [u16; 8usize],
10851 pub average_core_c0_activity: [u16; 16usize],
10852 pub average_dram_reads: u16,
10853 pub average_dram_writes: u16,
10854 pub average_ipu_reads: u16,
10855 pub average_ipu_writes: u16,
10856 pub system_clock_counter: u64,
10857 pub average_socket_power: u32,
10858 pub average_ipu_power: u16,
10859 pub average_apu_power: u32,
10860 pub average_gfx_power: u32,
10861 pub average_dgpu_power: u32,
10862 pub average_all_core_power: u32,
10863 pub average_core_power: [u16; 16usize],
10864 pub average_sys_power: u16,
10865 pub stapm_power_limit: u16,
10866 pub current_stapm_power_limit: u16,
10867 pub average_gfxclk_frequency: u16,
10868 pub average_socclk_frequency: u16,
10869 pub average_vpeclk_frequency: u16,
10870 pub average_ipuclk_frequency: u16,
10871 pub average_fclk_frequency: u16,
10872 pub average_vclk_frequency: u16,
10873 pub average_uclk_frequency: u16,
10874 pub average_mpipu_frequency: u16,
10875 pub current_coreclk: [u16; 16usize],
10876 pub current_core_maxfreq: u16,
10877 pub current_gfx_maxfreq: u16,
10878 pub throttle_residency_prochot: u32,
10879 pub throttle_residency_spl: u32,
10880 pub throttle_residency_fppt: u32,
10881 pub throttle_residency_sppt: u32,
10882 pub throttle_residency_thm_core: u32,
10883 pub throttle_residency_thm_gfx: u32,
10884 pub throttle_residency_thm_soc: u32,
10885 pub time_filter_alphavalue: u32,
10886}
10887pub type __builtin_va_list = [__va_list_tag; 1usize];
10888#[repr(C)]
10889#[derive(Debug, Copy, Clone)]
10890pub struct __va_list_tag {
10891 pub gp_offset: ::core::ffi::c_uint,
10892 pub fp_offset: ::core::ffi::c_uint,
10893 pub overflow_arg_area: *mut ::core::ffi::c_void,
10894 pub reg_save_area: *mut ::core::ffi::c_void,
10895}