lcd_async/interface.rs
1//! Interface traits and implementations
2
3mod spi;
4pub use spi::*;
5
6mod parallel;
7pub use parallel::*;
8
9/// Command and pixel interface
10pub trait Interface {
11 /// The native width of the interface
12 ///
13 /// In most cases this will be u8, except for larger parallel interfaces such as
14 /// 16 bit (currently supported)
15 /// or 9 or 18 bit (currently unsupported)
16 type Word: Copy;
17
18 /// Error type
19 type Error: core::fmt::Debug;
20
21 /// Kind
22 const KIND: InterfaceKind;
23
24 /// Send a command with optional parameters
25 fn send_command(
26 &mut self,
27 command: u8,
28 args: &[u8],
29 ) -> impl core::future::Future<Output = Result<(), Self::Error>>;
30
31 /// Send a raw slice of data, typically pre-formatted pixel data.
32 /// `WriteMemoryStart` (or equivalent) must be sent before calling this function.
33 /// The data is assumed to be in the correct format for the display and interface.
34 /// If Self::Word is u8, data is &[u8]. If Self::Word is u16, data is &[u16].
35 fn send_data_slice(
36 &mut self,
37 data: &[Self::Word],
38 ) -> impl core::future::Future<Output = Result<(), Self::Error>>;
39}
40
41impl<T: Interface + ?Sized> Interface for &mut T {
42 type Word = T::Word;
43 type Error = T::Error;
44 const KIND: InterfaceKind = T::KIND;
45
46 async fn send_command(&mut self, command: u8, args: &[u8]) -> Result<(), Self::Error> {
47 T::send_command(self, command, args).await
48 }
49
50 async fn send_data_slice(&mut self, data: &[Self::Word]) -> Result<(), Self::Error> {
51 T::send_data_slice(self, data).await
52 }
53}
54
55/// Interface kind.
56///
57/// Specifies the kind of physical connection to the display controller that is
58/// supported by this interface.
59#[derive(Debug, Clone, Copy, PartialEq, Eq)]
60#[non_exhaustive]
61pub enum InterfaceKind {
62 /// Serial interface with data/command pin.
63 ///
64 /// SPI style interface with 8 bits per word and an additional pin to
65 /// distinguish between data and command words.
66 Serial4Line,
67
68 /// 8 bit parallel interface.
69 ///
70 /// 8080 style parallel interface with 8 data pins and chip select, write enable,
71 /// and command/data signals.
72 Parallel8Bit,
73
74 /// 16 bit parallel interface.
75 ///
76 /// 8080 style parallel interface with 16 data pins and chip select, write enable,
77 /// and command/data signals.
78 Parallel16Bit,
79}