Module vector_add 

Elementwise vector add — the demonstrator op that proves the cascade.

out[i] = a[i] + b[i]. Trivial arithmetic on purpose: the point of this op is not the maths but to exercise the whole GPU->CPU machinery end to end — host data into storage buffers, a WGSL compute dispatch, readback through a staging buffer, and a pure-Rust twin that gives the identical answer when there is no GPU.

Both paths return Vec<f32> of the same length as the inputs, and for elementwise f32 addition the GPU and CPU results are bit-for-bit equal (IEEE-754 addition is exact and deterministic here — no reordering, no fused-multiply-add), which is why the tests can assert plain equality when a GPU is present.

Structs

VectorAdd

Elementwise vector addition. Zero-sized: it carries no state, it just names the operation so the ComputeOp impl and its two kernels hang off a type.

VectorAddInput

The two input vectors, borrowed. Equal length is a precondition (checked in both paths); mismatched lengths are a caller bug, not something to paper over.

Functions

vector_add_cpu

The pure-Rust floor of the cascade. Infallible and correct.

vector_add_gpu

The wgpu compute path. Fallible: any wgpu-level problem returns Err so the crate::Executor can fall back to vector_add_cpu.