khal_std/
memory.rs

1#[cfg(target_arch = "nvptx64")]
2pub use memory_nvptx::*;
3#[cfg(not(target_arch = "nvptx64"))]
4pub use spirv_std::memory::*;
5
6// On nvptx64, provide the memory scope constants.
7#[cfg(target_arch = "nvptx64")]
8pub mod memory_nvptx {
9    /// Memory scope levels matching SPIR-V semantics for use on the CUDA backend.
10    #[derive(Copy, Clone)]
11    #[repr(u32)]
12    pub enum Scope {
13        /// Visible across all devices.
14        CrossDevice = 0,
15        /// Visible within the current device.
16        Device = 1,
17        /// Visible within the current workgroup.
18        Workgroup = 2,
19        /// Visible within the current subgroup.
20        Subgroup = 3,
21        /// Visible only to the current invocation.
22        Invocation = 4,
23        /// Visible within the queue family.
24        QueueFamily = 5,
25    }
26    /// Memory ordering semantics matching SPIR-V for use on the CUDA backend.
27    #[derive(Copy, Clone)]
28    pub struct Semantics(u32);
29    impl Semantics {
30        /// No memory ordering constraints.
31        pub const NONE: Self = Self(0);
32        /// Acquire semantics.
33        pub const ACQUIRE: Self = Self(0x2);
34        /// Release semantics.
35        pub const RELEASE: Self = Self(0x4);
36        /// Acquire-release semantics.
37        pub const ACQUIRE_RELEASE: Self = Self(0x8);
38        /// Applies to uniform (constant) memory.
39        pub const UNIFORM_MEMORY: Self = Self(0x40);
40        /// Applies to workgroup (shared) memory.
41        pub const WORKGROUP_MEMORY: Self = Self(0x100);
42        /// Returns the raw bit representation.
43        pub const fn bits(self) -> u32 {
44            self.0
45        }
46    }
47
48    impl core::ops::BitOr for Semantics {
49        type Output = Self;
50        fn bitor(self, rhs: Self) -> Self {
51            Self(self.0 | rhs.0)
52        }
53    }
54}
khal_std/memory.rs

khal_std/
memory.rs
