kernel_elf_parser/auxv.rs
1use zerocopy::{Immutable, IntoBytes};
2
3/// Represents the type of an auxiliary vector entry.
4#[derive(Clone, Copy, PartialEq, Eq, IntoBytes, Immutable)]
5#[allow(non_camel_case_types, unused)]
6#[repr(usize)]
7pub enum AuxType {
8 /// End of vector
9 NULL = 0,
10 /// Entry should be ignored
11 IGNORE = 1,
12 /// File descriptor of program
13 EXECFD = 2,
14 /// Program headers for program
15 PHDR = 3,
16 /// Size of program header entry
17 PHENT = 4,
18 /// Number of program headers
19 PHNUM = 5,
20 /// System page size
21 PAGESZ = 6,
22 /// Base address of interpreter
23 BASE = 7,
24 /// Flags
25 FLAGS = 8,
26 /// Entry point of program
27 ENTRY = 9,
28 /// Program is not ELF
29 NOTELF = 10,
30 /// Real UID
31 UID = 11,
32 /// Effective UID
33 EUID = 12,
34 /// Real GID
35 GID = 13,
36 /// Effective GID
37 EGID = 14,
38 /// String identifying CPU for optimizations
39 PLATFORM = 15,
40 /// Arch dependent hints at CPU capabilities
41 HWCAP = 16,
42 /// Frequency at which times() increments
43 CLKTCK = 17,
44 /// Floating point unit control word
45 FPUCW = 18,
46 /// Data cache block size
47 DCACHEBSIZE = 19,
48 /// Instruction cache block size
49 ICACHEBSIZE = 20,
50 /// Unified cache block size
51 UCACHEBSIZE = 21,
52 /// Entry should be ignored on PowerPC
53 IGNOREPPC = 22,
54 /// Secure mode boolean
55 SECURE = 23,
56 /// String identifying real platform, may differ from AT_PLATFORM
57 BASE_PLATFORM = 24,
58 /// Address of 16 random bytes
59 RANDOM = 25,
60 /// Extension of AT_HWCAP
61 HWCAP2 = 26,
62 /// Filename of program
63 EXECFN = 31,
64 /// Address of the VDSO
65 SYSINFO = 32,
66 /// Address of the ELF header of the VDSO
67 SYSINFO_EHDR = 33,
68 /// Shape of level 1 instruction cache
69 L1I_CACHESHAPE = 34,
70 /// Shape of level 1 data cache
71 L1D_CACHESHAPE = 35,
72 /// Shape of level 2 cache
73 L2_CACHESHAPE = 36,
74 /// Shape of level 3 cache
75 L3_CACHESHAPE = 37,
76 /// Size of level 1 instruction cache
77 L1I_CACHESIZE = 40,
78 /// Geometry of level 1 instruction cache
79 L1I_CACHEGEOMETRY = 41,
80 /// Size of level 1 data cache
81 L1D_CACHESIZE = 42,
82 /// Geometry of level 1 data cache
83 L1D_CACHEGEOMETRY = 43,
84 /// Size of level 2 cache
85 L2_CACHESIZE = 44,
86 /// Geometry of level 2 cache
87 L2_CACHEGEOMETRY = 45,
88 /// Size of level 3 cache
89 L3_CACHESIZE = 46,
90 /// Geometry of level 3 cache
91 L3_CACHEGEOMETRY = 47,
92 /// Minimal stack size for signal delivery
93 MINSIGSTKSZ = 51,
94}
95
96/// Represents an entry in the auxiliary vector.
97#[derive(Clone, Copy, IntoBytes, Immutable)]
98#[repr(C)]
99pub struct AuxEntry {
100 /// The type of the auxiliary vector entry.
101 auxv_type: AuxType,
102 /// The value associated with the auxiliary vector entry.
103 auxv_val: usize,
104}
105
106impl AuxEntry {
107 /// Create a new auxv entry
108 pub fn new(auxv_type: AuxType, auxv_val: usize) -> Self {
109 Self {
110 auxv_type,
111 auxv_val,
112 }
113 }
114
115 /// Get [self::AuxvType] of the auxv entry
116 pub fn get_type(&self) -> AuxType {
117 self.auxv_type
118 }
119
120 /// Get the value of the auxv entry
121 pub fn value(&self) -> usize {
122 self.auxv_val
123 }
124
125 /// Get a mutable reference to the value of the auxv entry
126 pub fn value_mut_ref(&mut self) -> &mut usize {
127 &mut self.auxv_val
128 }
129}