ke04z4_pac/sim/
sopt.rs

1#[doc = "Register `SOPT` reader"]
2pub struct R(crate::R<SOPT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SOPT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SOPT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SOPT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SOPT` writer"]
17pub struct W(crate::W<SOPT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SOPT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SOPT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SOPT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "NMI Pin Enable\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum NMIE_A {
40    #[doc = "0: PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI1_P6, FTM2_CH4, SPI0_MISO or ACMP1_IN2."]
41    _0 = 0,
42    #[doc = "1: PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI."]
43    _1 = 1,
44}
45impl From<NMIE_A> for bool {
46    #[inline(always)]
47    fn from(variant: NMIE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `NMIE` reader - NMI Pin Enable"]
52pub struct NMIE_R(crate::FieldReader<bool, NMIE_A>);
53impl NMIE_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        NMIE_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> NMIE_A {
60        match self.bits {
61            false => NMIE_A::_0,
62            true => NMIE_A::_1,
63        }
64    }
65    #[doc = "Checks if the value of the field is `_0`"]
66    #[inline(always)]
67    pub fn is_0(&self) -> bool {
68        **self == NMIE_A::_0
69    }
70    #[doc = "Checks if the value of the field is `_1`"]
71    #[inline(always)]
72    pub fn is_1(&self) -> bool {
73        **self == NMIE_A::_1
74    }
75}
76impl core::ops::Deref for NMIE_R {
77    type Target = crate::FieldReader<bool, NMIE_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `NMIE` writer - NMI Pin Enable"]
84pub struct NMIE_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> NMIE_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: NMIE_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI1_P6, FTM2_CH4, SPI0_MISO or ACMP1_IN2."]
94    #[inline(always)]
95    pub fn _0(self) -> &'a mut W {
96        self.variant(NMIE_A::_0)
97    }
98    #[doc = "PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI."]
99    #[inline(always)]
100    pub fn _1(self) -> &'a mut W {
101        self.variant(NMIE_A::_1)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
117        self.w
118    }
119}
120#[doc = "RESET Pin Enable\n\nValue on reset: 1"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum RSTPE_A {
123    #[doc = "0: PTA5/IRQ/TCLK1/RESET pin functions as PTA5, IRQ, or TCLK1."]
124    _0 = 0,
125    #[doc = "1: PTA5/IRQ/TCLK1/RESET pin functions as RESET."]
126    _1 = 1,
127}
128impl From<RSTPE_A> for bool {
129    #[inline(always)]
130    fn from(variant: RSTPE_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `RSTPE` reader - RESET Pin Enable"]
135pub struct RSTPE_R(crate::FieldReader<bool, RSTPE_A>);
136impl RSTPE_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        RSTPE_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> RSTPE_A {
143        match self.bits {
144            false => RSTPE_A::_0,
145            true => RSTPE_A::_1,
146        }
147    }
148    #[doc = "Checks if the value of the field is `_0`"]
149    #[inline(always)]
150    pub fn is_0(&self) -> bool {
151        **self == RSTPE_A::_0
152    }
153    #[doc = "Checks if the value of the field is `_1`"]
154    #[inline(always)]
155    pub fn is_1(&self) -> bool {
156        **self == RSTPE_A::_1
157    }
158}
159impl core::ops::Deref for RSTPE_R {
160    type Target = crate::FieldReader<bool, RSTPE_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `RSTPE` writer - RESET Pin Enable"]
167pub struct RSTPE_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> RSTPE_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: RSTPE_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "PTA5/IRQ/TCLK1/RESET pin functions as PTA5, IRQ, or TCLK1."]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(RSTPE_A::_0)
180    }
181    #[doc = "PTA5/IRQ/TCLK1/RESET pin functions as RESET."]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(RSTPE_A::_1)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
200        self.w
201    }
202}
203#[doc = "Single Wire Debug Port Pin Enable\n\nValue on reset: 1"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum SWDE_A {
206    #[doc = "0: PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as PTA0, KBI0_P0, FTM0_CH0, RTCO, ACMP0_IN2 or ADC0_SE0 function."]
207    _0 = 0,
208    #[doc = "1: PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as SWD_CLK function."]
209    _1 = 1,
210}
211impl From<SWDE_A> for bool {
212    #[inline(always)]
213    fn from(variant: SWDE_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `SWDE` reader - Single Wire Debug Port Pin Enable"]
218pub struct SWDE_R(crate::FieldReader<bool, SWDE_A>);
219impl SWDE_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        SWDE_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> SWDE_A {
226        match self.bits {
227            false => SWDE_A::_0,
228            true => SWDE_A::_1,
229        }
230    }
231    #[doc = "Checks if the value of the field is `_0`"]
232    #[inline(always)]
233    pub fn is_0(&self) -> bool {
234        **self == SWDE_A::_0
235    }
236    #[doc = "Checks if the value of the field is `_1`"]
237    #[inline(always)]
238    pub fn is_1(&self) -> bool {
239        **self == SWDE_A::_1
240    }
241}
242impl core::ops::Deref for SWDE_R {
243    type Target = crate::FieldReader<bool, SWDE_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `SWDE` writer - Single Wire Debug Port Pin Enable"]
250pub struct SWDE_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> SWDE_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: SWDE_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as PTA0, KBI0_P0, FTM0_CH0, RTCO, ACMP0_IN2 or ADC0_SE0 function."]
260    #[inline(always)]
261    pub fn _0(self) -> &'a mut W {
262        self.variant(SWDE_A::_0)
263    }
264    #[doc = "PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as SWD_CLK function."]
265    #[inline(always)]
266    pub fn _1(self) -> &'a mut W {
267        self.variant(SWDE_A::_1)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
283        self.w
284    }
285}
286#[doc = "ACMP Trigger FTM2 selection\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288pub enum ACTRG_A {
289    #[doc = "0: ACMP0 out"]
290    _0 = 0,
291    #[doc = "1: ACMP1 out"]
292    _1 = 1,
293}
294impl From<ACTRG_A> for bool {
295    #[inline(always)]
296    fn from(variant: ACTRG_A) -> Self {
297        variant as u8 != 0
298    }
299}
300#[doc = "Field `ACTRG` reader - ACMP Trigger FTM2 selection"]
301pub struct ACTRG_R(crate::FieldReader<bool, ACTRG_A>);
302impl ACTRG_R {
303    pub(crate) fn new(bits: bool) -> Self {
304        ACTRG_R(crate::FieldReader::new(bits))
305    }
306    #[doc = r"Get enumerated values variant"]
307    #[inline(always)]
308    pub fn variant(&self) -> ACTRG_A {
309        match self.bits {
310            false => ACTRG_A::_0,
311            true => ACTRG_A::_1,
312        }
313    }
314    #[doc = "Checks if the value of the field is `_0`"]
315    #[inline(always)]
316    pub fn is_0(&self) -> bool {
317        **self == ACTRG_A::_0
318    }
319    #[doc = "Checks if the value of the field is `_1`"]
320    #[inline(always)]
321    pub fn is_1(&self) -> bool {
322        **self == ACTRG_A::_1
323    }
324}
325impl core::ops::Deref for ACTRG_R {
326    type Target = crate::FieldReader<bool, ACTRG_A>;
327    #[inline(always)]
328    fn deref(&self) -> &Self::Target {
329        &self.0
330    }
331}
332#[doc = "Field `ACTRG` writer - ACMP Trigger FTM2 selection"]
333pub struct ACTRG_W<'a> {
334    w: &'a mut W,
335}
336impl<'a> ACTRG_W<'a> {
337    #[doc = r"Writes `variant` to the field"]
338    #[inline(always)]
339    pub fn variant(self, variant: ACTRG_A) -> &'a mut W {
340        self.bit(variant.into())
341    }
342    #[doc = "ACMP0 out"]
343    #[inline(always)]
344    pub fn _0(self) -> &'a mut W {
345        self.variant(ACTRG_A::_0)
346    }
347    #[doc = "ACMP1 out"]
348    #[inline(always)]
349    pub fn _1(self) -> &'a mut W {
350        self.variant(ACTRG_A::_1)
351    }
352    #[doc = r"Sets the field bit"]
353    #[inline(always)]
354    pub fn set_bit(self) -> &'a mut W {
355        self.bit(true)
356    }
357    #[doc = r"Clears the field bit"]
358    #[inline(always)]
359    pub fn clear_bit(self) -> &'a mut W {
360        self.bit(false)
361    }
362    #[doc = r"Writes raw bits to the field"]
363    #[inline(always)]
364    pub fn bit(self, value: bool) -> &'a mut W {
365        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
366        self.w
367    }
368}
369#[doc = "FTM0CH0 Input Capture Source\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq)]
371#[repr(u8)]
372pub enum FTMIC_A {
373    #[doc = "0: FTM0_CH0 pin"]
374    _00 = 0,
375    #[doc = "1: ACMP0 OUT"]
376    _01 = 1,
377    #[doc = "2: ACMP1 OUT"]
378    _10 = 2,
379    #[doc = "3: RTC overflow"]
380    _11 = 3,
381}
382impl From<FTMIC_A> for u8 {
383    #[inline(always)]
384    fn from(variant: FTMIC_A) -> Self {
385        variant as _
386    }
387}
388#[doc = "Field `FTMIC` reader - FTM0CH0 Input Capture Source"]
389pub struct FTMIC_R(crate::FieldReader<u8, FTMIC_A>);
390impl FTMIC_R {
391    pub(crate) fn new(bits: u8) -> Self {
392        FTMIC_R(crate::FieldReader::new(bits))
393    }
394    #[doc = r"Get enumerated values variant"]
395    #[inline(always)]
396    pub fn variant(&self) -> FTMIC_A {
397        match self.bits {
398            0 => FTMIC_A::_00,
399            1 => FTMIC_A::_01,
400            2 => FTMIC_A::_10,
401            3 => FTMIC_A::_11,
402            _ => unreachable!(),
403        }
404    }
405    #[doc = "Checks if the value of the field is `_00`"]
406    #[inline(always)]
407    pub fn is_00(&self) -> bool {
408        **self == FTMIC_A::_00
409    }
410    #[doc = "Checks if the value of the field is `_01`"]
411    #[inline(always)]
412    pub fn is_01(&self) -> bool {
413        **self == FTMIC_A::_01
414    }
415    #[doc = "Checks if the value of the field is `_10`"]
416    #[inline(always)]
417    pub fn is_10(&self) -> bool {
418        **self == FTMIC_A::_10
419    }
420    #[doc = "Checks if the value of the field is `_11`"]
421    #[inline(always)]
422    pub fn is_11(&self) -> bool {
423        **self == FTMIC_A::_11
424    }
425}
426impl core::ops::Deref for FTMIC_R {
427    type Target = crate::FieldReader<u8, FTMIC_A>;
428    #[inline(always)]
429    fn deref(&self) -> &Self::Target {
430        &self.0
431    }
432}
433#[doc = "Field `FTMIC` writer - FTM0CH0 Input Capture Source"]
434pub struct FTMIC_W<'a> {
435    w: &'a mut W,
436}
437impl<'a> FTMIC_W<'a> {
438    #[doc = r"Writes `variant` to the field"]
439    #[inline(always)]
440    pub fn variant(self, variant: FTMIC_A) -> &'a mut W {
441        self.bits(variant.into())
442    }
443    #[doc = "FTM0_CH0 pin"]
444    #[inline(always)]
445    pub fn _00(self) -> &'a mut W {
446        self.variant(FTMIC_A::_00)
447    }
448    #[doc = "ACMP0 OUT"]
449    #[inline(always)]
450    pub fn _01(self) -> &'a mut W {
451        self.variant(FTMIC_A::_01)
452    }
453    #[doc = "ACMP1 OUT"]
454    #[inline(always)]
455    pub fn _10(self) -> &'a mut W {
456        self.variant(FTMIC_A::_10)
457    }
458    #[doc = "RTC overflow"]
459    #[inline(always)]
460    pub fn _11(self) -> &'a mut W {
461        self.variant(FTMIC_A::_11)
462    }
463    #[doc = r"Writes raw bits to the field"]
464    #[inline(always)]
465    pub fn bits(self, value: u8) -> &'a mut W {
466        self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6);
467        self.w
468    }
469}
470#[doc = "UART0 RxD Filter Select\n\nValue on reset: 0"]
471#[derive(Clone, Copy, Debug, PartialEq)]
472#[repr(u8)]
473pub enum RXDFE_A {
474    #[doc = "0: RXD0 input signal is connected to UART0 module directly."]
475    _00 = 0,
476    #[doc = "1: RXD0 input signal is filtered by ACMP0, then injected to UART0."]
477    _01 = 1,
478    #[doc = "2: RXD0 input signal is filtered by ACMP1, then injected to UART0."]
479    _10 = 2,
480}
481impl From<RXDFE_A> for u8 {
482    #[inline(always)]
483    fn from(variant: RXDFE_A) -> Self {
484        variant as _
485    }
486}
487#[doc = "Field `RXDFE` reader - UART0 RxD Filter Select"]
488pub struct RXDFE_R(crate::FieldReader<u8, RXDFE_A>);
489impl RXDFE_R {
490    pub(crate) fn new(bits: u8) -> Self {
491        RXDFE_R(crate::FieldReader::new(bits))
492    }
493    #[doc = r"Get enumerated values variant"]
494    #[inline(always)]
495    pub fn variant(&self) -> Option<RXDFE_A> {
496        match self.bits {
497            0 => Some(RXDFE_A::_00),
498            1 => Some(RXDFE_A::_01),
499            2 => Some(RXDFE_A::_10),
500            _ => None,
501        }
502    }
503    #[doc = "Checks if the value of the field is `_00`"]
504    #[inline(always)]
505    pub fn is_00(&self) -> bool {
506        **self == RXDFE_A::_00
507    }
508    #[doc = "Checks if the value of the field is `_01`"]
509    #[inline(always)]
510    pub fn is_01(&self) -> bool {
511        **self == RXDFE_A::_01
512    }
513    #[doc = "Checks if the value of the field is `_10`"]
514    #[inline(always)]
515    pub fn is_10(&self) -> bool {
516        **self == RXDFE_A::_10
517    }
518}
519impl core::ops::Deref for RXDFE_R {
520    type Target = crate::FieldReader<u8, RXDFE_A>;
521    #[inline(always)]
522    fn deref(&self) -> &Self::Target {
523        &self.0
524    }
525}
526#[doc = "Field `RXDFE` writer - UART0 RxD Filter Select"]
527pub struct RXDFE_W<'a> {
528    w: &'a mut W,
529}
530impl<'a> RXDFE_W<'a> {
531    #[doc = r"Writes `variant` to the field"]
532    #[inline(always)]
533    pub fn variant(self, variant: RXDFE_A) -> &'a mut W {
534        unsafe { self.bits(variant.into()) }
535    }
536    #[doc = "RXD0 input signal is connected to UART0 module directly."]
537    #[inline(always)]
538    pub fn _00(self) -> &'a mut W {
539        self.variant(RXDFE_A::_00)
540    }
541    #[doc = "RXD0 input signal is filtered by ACMP0, then injected to UART0."]
542    #[inline(always)]
543    pub fn _01(self) -> &'a mut W {
544        self.variant(RXDFE_A::_01)
545    }
546    #[doc = "RXD0 input signal is filtered by ACMP1, then injected to UART0."]
547    #[inline(always)]
548    pub fn _10(self) -> &'a mut W {
549        self.variant(RXDFE_A::_10)
550    }
551    #[doc = r"Writes raw bits to the field"]
552    #[inline(always)]
553    pub unsafe fn bits(self, value: u8) -> &'a mut W {
554        self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
555        self.w
556    }
557}
558#[doc = "UART0_RX Capture Select\n\nValue on reset: 0"]
559#[derive(Clone, Copy, Debug, PartialEq)]
560pub enum RXDCE_A {
561    #[doc = "0: UART0_RX input signal is connected to the UART0 module only."]
562    _0 = 0,
563    #[doc = "1: UART0_RX input signal is connected to the UART0 module and FTM0 channel 1."]
564    _1 = 1,
565}
566impl From<RXDCE_A> for bool {
567    #[inline(always)]
568    fn from(variant: RXDCE_A) -> Self {
569        variant as u8 != 0
570    }
571}
572#[doc = "Field `RXDCE` reader - UART0_RX Capture Select"]
573pub struct RXDCE_R(crate::FieldReader<bool, RXDCE_A>);
574impl RXDCE_R {
575    pub(crate) fn new(bits: bool) -> Self {
576        RXDCE_R(crate::FieldReader::new(bits))
577    }
578    #[doc = r"Get enumerated values variant"]
579    #[inline(always)]
580    pub fn variant(&self) -> RXDCE_A {
581        match self.bits {
582            false => RXDCE_A::_0,
583            true => RXDCE_A::_1,
584        }
585    }
586    #[doc = "Checks if the value of the field is `_0`"]
587    #[inline(always)]
588    pub fn is_0(&self) -> bool {
589        **self == RXDCE_A::_0
590    }
591    #[doc = "Checks if the value of the field is `_1`"]
592    #[inline(always)]
593    pub fn is_1(&self) -> bool {
594        **self == RXDCE_A::_1
595    }
596}
597impl core::ops::Deref for RXDCE_R {
598    type Target = crate::FieldReader<bool, RXDCE_A>;
599    #[inline(always)]
600    fn deref(&self) -> &Self::Target {
601        &self.0
602    }
603}
604#[doc = "Field `RXDCE` writer - UART0_RX Capture Select"]
605pub struct RXDCE_W<'a> {
606    w: &'a mut W,
607}
608impl<'a> RXDCE_W<'a> {
609    #[doc = r"Writes `variant` to the field"]
610    #[inline(always)]
611    pub fn variant(self, variant: RXDCE_A) -> &'a mut W {
612        self.bit(variant.into())
613    }
614    #[doc = "UART0_RX input signal is connected to the UART0 module only."]
615    #[inline(always)]
616    pub fn _0(self) -> &'a mut W {
617        self.variant(RXDCE_A::_0)
618    }
619    #[doc = "UART0_RX input signal is connected to the UART0 module and FTM0 channel 1."]
620    #[inline(always)]
621    pub fn _1(self) -> &'a mut W {
622        self.variant(RXDCE_A::_1)
623    }
624    #[doc = r"Sets the field bit"]
625    #[inline(always)]
626    pub fn set_bit(self) -> &'a mut W {
627        self.bit(true)
628    }
629    #[doc = r"Clears the field bit"]
630    #[inline(always)]
631    pub fn clear_bit(self) -> &'a mut W {
632        self.bit(false)
633    }
634    #[doc = r"Writes raw bits to the field"]
635    #[inline(always)]
636    pub fn bit(self, value: bool) -> &'a mut W {
637        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
638        self.w
639    }
640}
641#[doc = "FTM2 Synchronization Select\n\nValue on reset: 0"]
642#[derive(Clone, Copy, Debug, PartialEq)]
643pub enum FTMSYNC_AW {
644    #[doc = "0: No synchronization triggered."]
645    _0 = 0,
646    #[doc = "1: Generates a PWM synchronization trigger to the FTM2 modules."]
647    _1 = 1,
648}
649impl From<FTMSYNC_AW> for bool {
650    #[inline(always)]
651    fn from(variant: FTMSYNC_AW) -> Self {
652        variant as u8 != 0
653    }
654}
655#[doc = "Field `FTMSYNC` writer - FTM2 Synchronization Select"]
656pub struct FTMSYNC_W<'a> {
657    w: &'a mut W,
658}
659impl<'a> FTMSYNC_W<'a> {
660    #[doc = r"Writes `variant` to the field"]
661    #[inline(always)]
662    pub fn variant(self, variant: FTMSYNC_AW) -> &'a mut W {
663        self.bit(variant.into())
664    }
665    #[doc = "No synchronization triggered."]
666    #[inline(always)]
667    pub fn _0(self) -> &'a mut W {
668        self.variant(FTMSYNC_AW::_0)
669    }
670    #[doc = "Generates a PWM synchronization trigger to the FTM2 modules."]
671    #[inline(always)]
672    pub fn _1(self) -> &'a mut W {
673        self.variant(FTMSYNC_AW::_1)
674    }
675    #[doc = r"Sets the field bit"]
676    #[inline(always)]
677    pub fn set_bit(self) -> &'a mut W {
678        self.bit(true)
679    }
680    #[doc = r"Clears the field bit"]
681    #[inline(always)]
682    pub fn clear_bit(self) -> &'a mut W {
683        self.bit(false)
684    }
685    #[doc = r"Writes raw bits to the field"]
686    #[inline(always)]
687    pub fn bit(self, value: bool) -> &'a mut W {
688        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
689        self.w
690    }
691}
692#[doc = "UART0_TX Modulation Select\n\nValue on reset: 0"]
693#[derive(Clone, Copy, Debug, PartialEq)]
694pub enum TXDME_A {
695    #[doc = "0: UART0_TX output is connected to pinout directly."]
696    _0 = 0,
697    #[doc = "1: UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout."]
698    _1 = 1,
699}
700impl From<TXDME_A> for bool {
701    #[inline(always)]
702    fn from(variant: TXDME_A) -> Self {
703        variant as u8 != 0
704    }
705}
706#[doc = "Field `TXDME` reader - UART0_TX Modulation Select"]
707pub struct TXDME_R(crate::FieldReader<bool, TXDME_A>);
708impl TXDME_R {
709    pub(crate) fn new(bits: bool) -> Self {
710        TXDME_R(crate::FieldReader::new(bits))
711    }
712    #[doc = r"Get enumerated values variant"]
713    #[inline(always)]
714    pub fn variant(&self) -> TXDME_A {
715        match self.bits {
716            false => TXDME_A::_0,
717            true => TXDME_A::_1,
718        }
719    }
720    #[doc = "Checks if the value of the field is `_0`"]
721    #[inline(always)]
722    pub fn is_0(&self) -> bool {
723        **self == TXDME_A::_0
724    }
725    #[doc = "Checks if the value of the field is `_1`"]
726    #[inline(always)]
727    pub fn is_1(&self) -> bool {
728        **self == TXDME_A::_1
729    }
730}
731impl core::ops::Deref for TXDME_R {
732    type Target = crate::FieldReader<bool, TXDME_A>;
733    #[inline(always)]
734    fn deref(&self) -> &Self::Target {
735        &self.0
736    }
737}
738#[doc = "Field `TXDME` writer - UART0_TX Modulation Select"]
739pub struct TXDME_W<'a> {
740    w: &'a mut W,
741}
742impl<'a> TXDME_W<'a> {
743    #[doc = r"Writes `variant` to the field"]
744    #[inline(always)]
745    pub fn variant(self, variant: TXDME_A) -> &'a mut W {
746        self.bit(variant.into())
747    }
748    #[doc = "UART0_TX output is connected to pinout directly."]
749    #[inline(always)]
750    pub fn _0(self) -> &'a mut W {
751        self.variant(TXDME_A::_0)
752    }
753    #[doc = "UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout."]
754    #[inline(always)]
755    pub fn _1(self) -> &'a mut W {
756        self.variant(TXDME_A::_1)
757    }
758    #[doc = r"Sets the field bit"]
759    #[inline(always)]
760    pub fn set_bit(self) -> &'a mut W {
761        self.bit(true)
762    }
763    #[doc = r"Clears the field bit"]
764    #[inline(always)]
765    pub fn clear_bit(self) -> &'a mut W {
766        self.bit(false)
767    }
768    #[doc = r"Writes raw bits to the field"]
769    #[inline(always)]
770    pub fn bit(self, value: bool) -> &'a mut W {
771        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
772        self.w
773    }
774}
775#[doc = "BUS Clock Output select\n\nValue on reset: 0"]
776#[derive(Clone, Copy, Debug, PartialEq)]
777#[repr(u8)]
778pub enum BUSREF_A {
779    #[doc = "0: Bus"]
780    _000 = 0,
781    #[doc = "1: Bus divided by 2"]
782    _001 = 1,
783    #[doc = "2: Bus divided by 4"]
784    _010 = 2,
785    #[doc = "3: Bus divided by 8"]
786    _011 = 3,
787    #[doc = "4: Bus divided by 16"]
788    _100 = 4,
789    #[doc = "5: Bus divided by 32"]
790    _101 = 5,
791    #[doc = "6: Bus divided by 64"]
792    _110 = 6,
793    #[doc = "7: Bus divided by 128"]
794    _111 = 7,
795}
796impl From<BUSREF_A> for u8 {
797    #[inline(always)]
798    fn from(variant: BUSREF_A) -> Self {
799        variant as _
800    }
801}
802#[doc = "Field `BUSREF` reader - BUS Clock Output select"]
803pub struct BUSREF_R(crate::FieldReader<u8, BUSREF_A>);
804impl BUSREF_R {
805    pub(crate) fn new(bits: u8) -> Self {
806        BUSREF_R(crate::FieldReader::new(bits))
807    }
808    #[doc = r"Get enumerated values variant"]
809    #[inline(always)]
810    pub fn variant(&self) -> BUSREF_A {
811        match self.bits {
812            0 => BUSREF_A::_000,
813            1 => BUSREF_A::_001,
814            2 => BUSREF_A::_010,
815            3 => BUSREF_A::_011,
816            4 => BUSREF_A::_100,
817            5 => BUSREF_A::_101,
818            6 => BUSREF_A::_110,
819            7 => BUSREF_A::_111,
820            _ => unreachable!(),
821        }
822    }
823    #[doc = "Checks if the value of the field is `_000`"]
824    #[inline(always)]
825    pub fn is_000(&self) -> bool {
826        **self == BUSREF_A::_000
827    }
828    #[doc = "Checks if the value of the field is `_001`"]
829    #[inline(always)]
830    pub fn is_001(&self) -> bool {
831        **self == BUSREF_A::_001
832    }
833    #[doc = "Checks if the value of the field is `_010`"]
834    #[inline(always)]
835    pub fn is_010(&self) -> bool {
836        **self == BUSREF_A::_010
837    }
838    #[doc = "Checks if the value of the field is `_011`"]
839    #[inline(always)]
840    pub fn is_011(&self) -> bool {
841        **self == BUSREF_A::_011
842    }
843    #[doc = "Checks if the value of the field is `_100`"]
844    #[inline(always)]
845    pub fn is_100(&self) -> bool {
846        **self == BUSREF_A::_100
847    }
848    #[doc = "Checks if the value of the field is `_101`"]
849    #[inline(always)]
850    pub fn is_101(&self) -> bool {
851        **self == BUSREF_A::_101
852    }
853    #[doc = "Checks if the value of the field is `_110`"]
854    #[inline(always)]
855    pub fn is_110(&self) -> bool {
856        **self == BUSREF_A::_110
857    }
858    #[doc = "Checks if the value of the field is `_111`"]
859    #[inline(always)]
860    pub fn is_111(&self) -> bool {
861        **self == BUSREF_A::_111
862    }
863}
864impl core::ops::Deref for BUSREF_R {
865    type Target = crate::FieldReader<u8, BUSREF_A>;
866    #[inline(always)]
867    fn deref(&self) -> &Self::Target {
868        &self.0
869    }
870}
871#[doc = "Field `BUSREF` writer - BUS Clock Output select"]
872pub struct BUSREF_W<'a> {
873    w: &'a mut W,
874}
875impl<'a> BUSREF_W<'a> {
876    #[doc = r"Writes `variant` to the field"]
877    #[inline(always)]
878    pub fn variant(self, variant: BUSREF_A) -> &'a mut W {
879        self.bits(variant.into())
880    }
881    #[doc = "Bus"]
882    #[inline(always)]
883    pub fn _000(self) -> &'a mut W {
884        self.variant(BUSREF_A::_000)
885    }
886    #[doc = "Bus divided by 2"]
887    #[inline(always)]
888    pub fn _001(self) -> &'a mut W {
889        self.variant(BUSREF_A::_001)
890    }
891    #[doc = "Bus divided by 4"]
892    #[inline(always)]
893    pub fn _010(self) -> &'a mut W {
894        self.variant(BUSREF_A::_010)
895    }
896    #[doc = "Bus divided by 8"]
897    #[inline(always)]
898    pub fn _011(self) -> &'a mut W {
899        self.variant(BUSREF_A::_011)
900    }
901    #[doc = "Bus divided by 16"]
902    #[inline(always)]
903    pub fn _100(self) -> &'a mut W {
904        self.variant(BUSREF_A::_100)
905    }
906    #[doc = "Bus divided by 32"]
907    #[inline(always)]
908    pub fn _101(self) -> &'a mut W {
909        self.variant(BUSREF_A::_101)
910    }
911    #[doc = "Bus divided by 64"]
912    #[inline(always)]
913    pub fn _110(self) -> &'a mut W {
914        self.variant(BUSREF_A::_110)
915    }
916    #[doc = "Bus divided by 128"]
917    #[inline(always)]
918    pub fn _111(self) -> &'a mut W {
919        self.variant(BUSREF_A::_111)
920    }
921    #[doc = r"Writes raw bits to the field"]
922    #[inline(always)]
923    pub fn bits(self, value: u8) -> &'a mut W {
924        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
925        self.w
926    }
927}
928#[doc = "Bus Clock Output Enable\n\nValue on reset: 0"]
929#[derive(Clone, Copy, Debug, PartialEq)]
930pub enum CLKOE_A {
931    #[doc = "0: Bus clock output is disabled on PTC5."]
932    _0 = 0,
933    #[doc = "1: Bus clock output is enabled on PTC5."]
934    _1 = 1,
935}
936impl From<CLKOE_A> for bool {
937    #[inline(always)]
938    fn from(variant: CLKOE_A) -> Self {
939        variant as u8 != 0
940    }
941}
942#[doc = "Field `CLKOE` reader - Bus Clock Output Enable"]
943pub struct CLKOE_R(crate::FieldReader<bool, CLKOE_A>);
944impl CLKOE_R {
945    pub(crate) fn new(bits: bool) -> Self {
946        CLKOE_R(crate::FieldReader::new(bits))
947    }
948    #[doc = r"Get enumerated values variant"]
949    #[inline(always)]
950    pub fn variant(&self) -> CLKOE_A {
951        match self.bits {
952            false => CLKOE_A::_0,
953            true => CLKOE_A::_1,
954        }
955    }
956    #[doc = "Checks if the value of the field is `_0`"]
957    #[inline(always)]
958    pub fn is_0(&self) -> bool {
959        **self == CLKOE_A::_0
960    }
961    #[doc = "Checks if the value of the field is `_1`"]
962    #[inline(always)]
963    pub fn is_1(&self) -> bool {
964        **self == CLKOE_A::_1
965    }
966}
967impl core::ops::Deref for CLKOE_R {
968    type Target = crate::FieldReader<bool, CLKOE_A>;
969    #[inline(always)]
970    fn deref(&self) -> &Self::Target {
971        &self.0
972    }
973}
974#[doc = "Field `CLKOE` writer - Bus Clock Output Enable"]
975pub struct CLKOE_W<'a> {
976    w: &'a mut W,
977}
978impl<'a> CLKOE_W<'a> {
979    #[doc = r"Writes `variant` to the field"]
980    #[inline(always)]
981    pub fn variant(self, variant: CLKOE_A) -> &'a mut W {
982        self.bit(variant.into())
983    }
984    #[doc = "Bus clock output is disabled on PTC5."]
985    #[inline(always)]
986    pub fn _0(self) -> &'a mut W {
987        self.variant(CLKOE_A::_0)
988    }
989    #[doc = "Bus clock output is enabled on PTC5."]
990    #[inline(always)]
991    pub fn _1(self) -> &'a mut W {
992        self.variant(CLKOE_A::_1)
993    }
994    #[doc = r"Sets the field bit"]
995    #[inline(always)]
996    pub fn set_bit(self) -> &'a mut W {
997        self.bit(true)
998    }
999    #[doc = r"Clears the field bit"]
1000    #[inline(always)]
1001    pub fn clear_bit(self) -> &'a mut W {
1002        self.bit(false)
1003    }
1004    #[doc = r"Writes raw bits to the field"]
1005    #[inline(always)]
1006    pub fn bit(self, value: bool) -> &'a mut W {
1007        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
1008        self.w
1009    }
1010}
1011#[doc = "ADC Hardware Trigger Source\n\nValue on reset: 0"]
1012#[derive(Clone, Copy, Debug, PartialEq)]
1013#[repr(u8)]
1014pub enum ADHWT_A {
1015    #[doc = "0: RTC overflow as the ADC hardware trigger"]
1016    _000 = 0,
1017    #[doc = "1: FTM0 init trigger as the ADC hardware trigger"]
1018    _001 = 1,
1019    #[doc = "2: FTM2 init trigger with 8-bit programmable counter delay"]
1020    _010 = 2,
1021    #[doc = "3: FTM2 match trigger with 8-bit programmable counter delay"]
1022    _011 = 3,
1023    #[doc = "4: PIT channel0 overflow as the ADC hardware trigger"]
1024    _100 = 4,
1025    #[doc = "5: PIT channel1 overflow as the ADC hardware trigger"]
1026    _101 = 5,
1027    #[doc = "6: ACMP0 out as the ADC hardware trigger."]
1028    _110 = 6,
1029    #[doc = "7: ACMP1 out as the ADC hardware trigger"]
1030    _111 = 7,
1031}
1032impl From<ADHWT_A> for u8 {
1033    #[inline(always)]
1034    fn from(variant: ADHWT_A) -> Self {
1035        variant as _
1036    }
1037}
1038#[doc = "Field `ADHWT` reader - ADC Hardware Trigger Source"]
1039pub struct ADHWT_R(crate::FieldReader<u8, ADHWT_A>);
1040impl ADHWT_R {
1041    pub(crate) fn new(bits: u8) -> Self {
1042        ADHWT_R(crate::FieldReader::new(bits))
1043    }
1044    #[doc = r"Get enumerated values variant"]
1045    #[inline(always)]
1046    pub fn variant(&self) -> ADHWT_A {
1047        match self.bits {
1048            0 => ADHWT_A::_000,
1049            1 => ADHWT_A::_001,
1050            2 => ADHWT_A::_010,
1051            3 => ADHWT_A::_011,
1052            4 => ADHWT_A::_100,
1053            5 => ADHWT_A::_101,
1054            6 => ADHWT_A::_110,
1055            7 => ADHWT_A::_111,
1056            _ => unreachable!(),
1057        }
1058    }
1059    #[doc = "Checks if the value of the field is `_000`"]
1060    #[inline(always)]
1061    pub fn is_000(&self) -> bool {
1062        **self == ADHWT_A::_000
1063    }
1064    #[doc = "Checks if the value of the field is `_001`"]
1065    #[inline(always)]
1066    pub fn is_001(&self) -> bool {
1067        **self == ADHWT_A::_001
1068    }
1069    #[doc = "Checks if the value of the field is `_010`"]
1070    #[inline(always)]
1071    pub fn is_010(&self) -> bool {
1072        **self == ADHWT_A::_010
1073    }
1074    #[doc = "Checks if the value of the field is `_011`"]
1075    #[inline(always)]
1076    pub fn is_011(&self) -> bool {
1077        **self == ADHWT_A::_011
1078    }
1079    #[doc = "Checks if the value of the field is `_100`"]
1080    #[inline(always)]
1081    pub fn is_100(&self) -> bool {
1082        **self == ADHWT_A::_100
1083    }
1084    #[doc = "Checks if the value of the field is `_101`"]
1085    #[inline(always)]
1086    pub fn is_101(&self) -> bool {
1087        **self == ADHWT_A::_101
1088    }
1089    #[doc = "Checks if the value of the field is `_110`"]
1090    #[inline(always)]
1091    pub fn is_110(&self) -> bool {
1092        **self == ADHWT_A::_110
1093    }
1094    #[doc = "Checks if the value of the field is `_111`"]
1095    #[inline(always)]
1096    pub fn is_111(&self) -> bool {
1097        **self == ADHWT_A::_111
1098    }
1099}
1100impl core::ops::Deref for ADHWT_R {
1101    type Target = crate::FieldReader<u8, ADHWT_A>;
1102    #[inline(always)]
1103    fn deref(&self) -> &Self::Target {
1104        &self.0
1105    }
1106}
1107#[doc = "Field `ADHWT` writer - ADC Hardware Trigger Source"]
1108pub struct ADHWT_W<'a> {
1109    w: &'a mut W,
1110}
1111impl<'a> ADHWT_W<'a> {
1112    #[doc = r"Writes `variant` to the field"]
1113    #[inline(always)]
1114    pub fn variant(self, variant: ADHWT_A) -> &'a mut W {
1115        self.bits(variant.into())
1116    }
1117    #[doc = "RTC overflow as the ADC hardware trigger"]
1118    #[inline(always)]
1119    pub fn _000(self) -> &'a mut W {
1120        self.variant(ADHWT_A::_000)
1121    }
1122    #[doc = "FTM0 init trigger as the ADC hardware trigger"]
1123    #[inline(always)]
1124    pub fn _001(self) -> &'a mut W {
1125        self.variant(ADHWT_A::_001)
1126    }
1127    #[doc = "FTM2 init trigger with 8-bit programmable counter delay"]
1128    #[inline(always)]
1129    pub fn _010(self) -> &'a mut W {
1130        self.variant(ADHWT_A::_010)
1131    }
1132    #[doc = "FTM2 match trigger with 8-bit programmable counter delay"]
1133    #[inline(always)]
1134    pub fn _011(self) -> &'a mut W {
1135        self.variant(ADHWT_A::_011)
1136    }
1137    #[doc = "PIT channel0 overflow as the ADC hardware trigger"]
1138    #[inline(always)]
1139    pub fn _100(self) -> &'a mut W {
1140        self.variant(ADHWT_A::_100)
1141    }
1142    #[doc = "PIT channel1 overflow as the ADC hardware trigger"]
1143    #[inline(always)]
1144    pub fn _101(self) -> &'a mut W {
1145        self.variant(ADHWT_A::_101)
1146    }
1147    #[doc = "ACMP0 out as the ADC hardware trigger."]
1148    #[inline(always)]
1149    pub fn _110(self) -> &'a mut W {
1150        self.variant(ADHWT_A::_110)
1151    }
1152    #[doc = "ACMP1 out as the ADC hardware trigger"]
1153    #[inline(always)]
1154    pub fn _111(self) -> &'a mut W {
1155        self.variant(ADHWT_A::_111)
1156    }
1157    #[doc = r"Writes raw bits to the field"]
1158    #[inline(always)]
1159    pub fn bits(self, value: u8) -> &'a mut W {
1160        self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20);
1161        self.w
1162    }
1163}
1164#[doc = "FTM2 Trigger Delay Active\n\nValue on reset: 0"]
1165#[derive(Clone, Copy, Debug, PartialEq)]
1166pub enum DLYACT_A {
1167    #[doc = "0: The delay is inactive."]
1168    _0 = 0,
1169    #[doc = "1: The delay is active."]
1170    _1 = 1,
1171}
1172impl From<DLYACT_A> for bool {
1173    #[inline(always)]
1174    fn from(variant: DLYACT_A) -> Self {
1175        variant as u8 != 0
1176    }
1177}
1178#[doc = "Field `DLYACT` reader - FTM2 Trigger Delay Active"]
1179pub struct DLYACT_R(crate::FieldReader<bool, DLYACT_A>);
1180impl DLYACT_R {
1181    pub(crate) fn new(bits: bool) -> Self {
1182        DLYACT_R(crate::FieldReader::new(bits))
1183    }
1184    #[doc = r"Get enumerated values variant"]
1185    #[inline(always)]
1186    pub fn variant(&self) -> DLYACT_A {
1187        match self.bits {
1188            false => DLYACT_A::_0,
1189            true => DLYACT_A::_1,
1190        }
1191    }
1192    #[doc = "Checks if the value of the field is `_0`"]
1193    #[inline(always)]
1194    pub fn is_0(&self) -> bool {
1195        **self == DLYACT_A::_0
1196    }
1197    #[doc = "Checks if the value of the field is `_1`"]
1198    #[inline(always)]
1199    pub fn is_1(&self) -> bool {
1200        **self == DLYACT_A::_1
1201    }
1202}
1203impl core::ops::Deref for DLYACT_R {
1204    type Target = crate::FieldReader<bool, DLYACT_A>;
1205    #[inline(always)]
1206    fn deref(&self) -> &Self::Target {
1207        &self.0
1208    }
1209}
1210#[doc = "Field `DELAY` reader - FTM2 Trigger Delay"]
1211pub struct DELAY_R(crate::FieldReader<u8, u8>);
1212impl DELAY_R {
1213    pub(crate) fn new(bits: u8) -> Self {
1214        DELAY_R(crate::FieldReader::new(bits))
1215    }
1216}
1217impl core::ops::Deref for DELAY_R {
1218    type Target = crate::FieldReader<u8, u8>;
1219    #[inline(always)]
1220    fn deref(&self) -> &Self::Target {
1221        &self.0
1222    }
1223}
1224#[doc = "Field `DELAY` writer - FTM2 Trigger Delay"]
1225pub struct DELAY_W<'a> {
1226    w: &'a mut W,
1227}
1228impl<'a> DELAY_W<'a> {
1229    #[doc = r"Writes raw bits to the field"]
1230    #[inline(always)]
1231    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1232        self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24);
1233        self.w
1234    }
1235}
1236impl R {
1237    #[doc = "Bit 1 - NMI Pin Enable"]
1238    #[inline(always)]
1239    pub fn nmie(&self) -> NMIE_R {
1240        NMIE_R::new(((self.bits >> 1) & 0x01) != 0)
1241    }
1242    #[doc = "Bit 2 - RESET Pin Enable"]
1243    #[inline(always)]
1244    pub fn rstpe(&self) -> RSTPE_R {
1245        RSTPE_R::new(((self.bits >> 2) & 0x01) != 0)
1246    }
1247    #[doc = "Bit 3 - Single Wire Debug Port Pin Enable"]
1248    #[inline(always)]
1249    pub fn swde(&self) -> SWDE_R {
1250        SWDE_R::new(((self.bits >> 3) & 0x01) != 0)
1251    }
1252    #[doc = "Bit 5 - ACMP Trigger FTM2 selection"]
1253    #[inline(always)]
1254    pub fn actrg(&self) -> ACTRG_R {
1255        ACTRG_R::new(((self.bits >> 5) & 0x01) != 0)
1256    }
1257    #[doc = "Bits 6:7 - FTM0CH0 Input Capture Source"]
1258    #[inline(always)]
1259    pub fn ftmic(&self) -> FTMIC_R {
1260        FTMIC_R::new(((self.bits >> 6) & 0x03) as u8)
1261    }
1262    #[doc = "Bits 8:9 - UART0 RxD Filter Select"]
1263    #[inline(always)]
1264    pub fn rxdfe(&self) -> RXDFE_R {
1265        RXDFE_R::new(((self.bits >> 8) & 0x03) as u8)
1266    }
1267    #[doc = "Bit 12 - UART0_RX Capture Select"]
1268    #[inline(always)]
1269    pub fn rxdce(&self) -> RXDCE_R {
1270        RXDCE_R::new(((self.bits >> 12) & 0x01) != 0)
1271    }
1272    #[doc = "Bit 15 - UART0_TX Modulation Select"]
1273    #[inline(always)]
1274    pub fn txdme(&self) -> TXDME_R {
1275        TXDME_R::new(((self.bits >> 15) & 0x01) != 0)
1276    }
1277    #[doc = "Bits 16:18 - BUS Clock Output select"]
1278    #[inline(always)]
1279    pub fn busref(&self) -> BUSREF_R {
1280        BUSREF_R::new(((self.bits >> 16) & 0x07) as u8)
1281    }
1282    #[doc = "Bit 19 - Bus Clock Output Enable"]
1283    #[inline(always)]
1284    pub fn clkoe(&self) -> CLKOE_R {
1285        CLKOE_R::new(((self.bits >> 19) & 0x01) != 0)
1286    }
1287    #[doc = "Bits 20:22 - ADC Hardware Trigger Source"]
1288    #[inline(always)]
1289    pub fn adhwt(&self) -> ADHWT_R {
1290        ADHWT_R::new(((self.bits >> 20) & 0x07) as u8)
1291    }
1292    #[doc = "Bit 23 - FTM2 Trigger Delay Active"]
1293    #[inline(always)]
1294    pub fn dlyact(&self) -> DLYACT_R {
1295        DLYACT_R::new(((self.bits >> 23) & 0x01) != 0)
1296    }
1297    #[doc = "Bits 24:31 - FTM2 Trigger Delay"]
1298    #[inline(always)]
1299    pub fn delay(&self) -> DELAY_R {
1300        DELAY_R::new(((self.bits >> 24) & 0xff) as u8)
1301    }
1302}
1303impl W {
1304    #[doc = "Bit 1 - NMI Pin Enable"]
1305    #[inline(always)]
1306    pub fn nmie(&mut self) -> NMIE_W {
1307        NMIE_W { w: self }
1308    }
1309    #[doc = "Bit 2 - RESET Pin Enable"]
1310    #[inline(always)]
1311    pub fn rstpe(&mut self) -> RSTPE_W {
1312        RSTPE_W { w: self }
1313    }
1314    #[doc = "Bit 3 - Single Wire Debug Port Pin Enable"]
1315    #[inline(always)]
1316    pub fn swde(&mut self) -> SWDE_W {
1317        SWDE_W { w: self }
1318    }
1319    #[doc = "Bit 5 - ACMP Trigger FTM2 selection"]
1320    #[inline(always)]
1321    pub fn actrg(&mut self) -> ACTRG_W {
1322        ACTRG_W { w: self }
1323    }
1324    #[doc = "Bits 6:7 - FTM0CH0 Input Capture Source"]
1325    #[inline(always)]
1326    pub fn ftmic(&mut self) -> FTMIC_W {
1327        FTMIC_W { w: self }
1328    }
1329    #[doc = "Bits 8:9 - UART0 RxD Filter Select"]
1330    #[inline(always)]
1331    pub fn rxdfe(&mut self) -> RXDFE_W {
1332        RXDFE_W { w: self }
1333    }
1334    #[doc = "Bit 12 - UART0_RX Capture Select"]
1335    #[inline(always)]
1336    pub fn rxdce(&mut self) -> RXDCE_W {
1337        RXDCE_W { w: self }
1338    }
1339    #[doc = "Bit 14 - FTM2 Synchronization Select"]
1340    #[inline(always)]
1341    pub fn ftmsync(&mut self) -> FTMSYNC_W {
1342        FTMSYNC_W { w: self }
1343    }
1344    #[doc = "Bit 15 - UART0_TX Modulation Select"]
1345    #[inline(always)]
1346    pub fn txdme(&mut self) -> TXDME_W {
1347        TXDME_W { w: self }
1348    }
1349    #[doc = "Bits 16:18 - BUS Clock Output select"]
1350    #[inline(always)]
1351    pub fn busref(&mut self) -> BUSREF_W {
1352        BUSREF_W { w: self }
1353    }
1354    #[doc = "Bit 19 - Bus Clock Output Enable"]
1355    #[inline(always)]
1356    pub fn clkoe(&mut self) -> CLKOE_W {
1357        CLKOE_W { w: self }
1358    }
1359    #[doc = "Bits 20:22 - ADC Hardware Trigger Source"]
1360    #[inline(always)]
1361    pub fn adhwt(&mut self) -> ADHWT_W {
1362        ADHWT_W { w: self }
1363    }
1364    #[doc = "Bits 24:31 - FTM2 Trigger Delay"]
1365    #[inline(always)]
1366    pub fn delay(&mut self) -> DELAY_W {
1367        DELAY_W { w: self }
1368    }
1369    #[doc = "Writes raw bits to the register."]
1370    #[inline(always)]
1371    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1372        self.0.bits(bits);
1373        self
1374    }
1375}
1376#[doc = "System Options Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sopt](index.html) module"]
1377pub struct SOPT_SPEC;
1378impl crate::RegisterSpec for SOPT_SPEC {
1379    type Ux = u32;
1380}
1381#[doc = "`read()` method returns [sopt::R](R) reader structure"]
1382impl crate::Readable for SOPT_SPEC {
1383    type Reader = R;
1384}
1385#[doc = "`write(|w| ..)` method takes [sopt::W](W) writer structure"]
1386impl crate::Writable for SOPT_SPEC {
1387    type Writer = W;
1388}
1389#[doc = "`reset()` method sets SOPT to value 0x0e"]
1390impl crate::Resettable for SOPT_SPEC {
1391    #[inline(always)]
1392    fn reset_value() -> Self::Ux {
1393        0x0e
1394    }
1395}
ke04z4_pac/sim/sopt.rs

ke04z4_pac/sim/
sopt.rs
