Struct kaze::Mem

#[must_use]pub struct Mem<'a> { /* fields omitted */ }

A synchronous memory, created by the Module::mem method.

Memories in kaze are always sequential/synchronous-read, sequential/synchronous-write memories. This means that when a read and/or write is asserted, the read/write will be visible on the cycle immediately following the cycle in which it's asserted. If both a write and a read to the same location occurs within the same cycle, the read will return the previous value at the memory location, not the newly-written value.

Memories must have at least one read port specified. Multiple reads to the same location within the same cycle will return the same value.

Memories may optionally have initial contents and/or a write port specified. If either of these are missing, the contents of the memory can't be determined, so this is a logical error.

Examples

use kaze::*;

let c = Context::new();

let m = c.module("MyModule");

let my_mem = m.mem("my_mem", 1, 32);
// Optional, unless no write port is specified
my_mem.initial_contents(&[0xfadebabeu32, 0xdeadbeefu32]);
// Optional, unless no initial contents are specified
my_mem.write_port(m.high(), m.lit(0xabad1deau32, 32), m.high());
m.output("my_output", my_mem.read_port(m.high(), m.high()));

Methods

impl<'a> Mem<'a>

pub fn initial_contents<C: Clone + Into<Constant>>(&'a self, contents: &[C])

Specifies the initial contents for this Mem.

Reads from this Mem will reflect the values specified unless writes have overwritten them (if the Mem has a write port).

By default, a Mem does not have initial contents, and it is not required to specify them unless the Mem does not have a write port. If initial contents are not specified, then this Mem's contents will be undefined initially.

Note that these contents are not restored when the containing Module's implicit reset is asserted.

Panics

Panics if this Mem already has initial contents specified, if contents.len() doesn't match the number of elements in this Mem, or if any of the specified element values don't fit into this Mem's element bit width.

Examples

use kaze::*;

let c = Context::new();

let m = c.module("MyModule");

let my_mem = m.mem("my_mem", 1, 32);
// Optional, unless no write port is specified
my_mem.initial_contents(&[0xfadebabeu32, 0xdeadbeefu32]);
// Optional, unless no initial contents are specified
my_mem.write_port(m.high(), m.lit(0xabad1deau32, 32), m.high());
m.output("my_output", my_mem.read_port(m.high(), m.high()));

pub fn read_port(
    &'a self,
    address: &'a Signal<'a>,
    enable: &'a Signal<'a>
) -> &Signal<'a>

Specifies a read port for this Mem and returns a Signal representing the data read from this port.

Mems are required to have at least one read port, otherwise the memory contents could never be read, which would be a logical error. There is no upper bound to the number of read ports specified in kaze, however a target device may not be able to synthesize the resulting Verilog code if too many are used.

Read ports always have an address signal and an enable signal. When enable is asserted, the returned Signal will reflect the data read from the location specified by address on the following cycle. If enable is not asserted, then the value of the returned Signal is undefined on the following cycle.

Panics

Panics if address's bit width doesn't match this Mem's address bit width, or if enable's bit width is not 1.

Examples

use kaze::*;

let c = Context::new();

let m = c.module("MyModule");

let my_mem = m.mem("my_mem", 1, 32);
// Optional, unless no write port is specified
my_mem.initial_contents(&[0xfadebabeu32, 0xdeadbeefu32]);
// Optional, unless no initial contents are specified
my_mem.write_port(m.high(), m.lit(0xabad1deau32, 32), m.high());
m.output("my_output", my_mem.read_port(m.high(), m.high()));

pub fn write_port(
    &'a self,
    address: &'a Signal<'a>,
    value: &'a Signal<'a>,
    enable: &'a Signal<'a>
)

Specifies a write port for this Mem.

By default, a Mem does not have any write ports, and it is not required to specify one unless the Mem does not have initial contents.

Write ports always have an address signal, a value signal, and an enable signal. When enable is asserted, the value at the location specified by address will reflect the value of the value signal on the following cycle. If enable is not asserted, then the memory contents will not change.

Panics

Panics if this Mem already has a write port specified, if address's bit width doesn't match this Mem's address bit width, if value's bit width doesn't match this Mem's element bit width, or if enable's bit width is not 1.

Examples

use kaze::*;

let c = Context::new();

let m = c.module("MyModule");

let my_mem = m.mem("my_mem", 1, 32);
// Optional, unless no write port is specified
my_mem.initial_contents(&[0xfadebabeu32, 0xdeadbeefu32]);
// Optional, unless no initial contents are specified
my_mem.write_port(m.high(), m.lit(0xabad1deau32, 32), m.high());
m.output("my_output", my_mem.read_port(m.high(), m.high()));

Trait Implementations

impl<'a> Eq for &'a Mem<'a>

impl<'a> Hash for &'a Mem<'a>

fn hash<H: Hasher>(&self, state: &mut H)

Feeds this value into the given [Hasher].

fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 

Feeds a slice of this type into the given [Hasher].

impl<'a> PartialEq<&'a Mem<'a>> for &'a Mem<'a>

fn eq(&self, other: &Self) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.