kaze's API is designed to be as minimal as possible while still being expressive. It's designed to prevent the user from being able to describe buggy or incorrect hardware as much as possible. This enables a user to hack on designs fearlessly, while the API and generators ensure that these designs are sound.
[dependencies] kaze = "0.1"
use kaze::*; // Create a context, which will contain our module(s) let c = Context::new(); // Create a module let inverter = c.module("Inverter"); let i = inverter.input("i", 1); // 1-bit input inverter.output("o", !i); // Output inverted input // Generate Rust simulator code sim::generate(inverter, std::io::stdout())?; // Generate Verilog code verilog::generate(inverter, std::io::stdout())?;
Rust simulator code generation.
Verilog code generation.
A top-level container/owner object for a
Represents a collection of 1 or more bits driven by some source.
A container for different types of integer constant values.
The maximum allowed bit width for any given
The minimum allowed bit width for any given
UNSTABLE: Provides a convenient way to write conditional combinational logic.