[−][src]Crate kaze

An HDL embedded in Rust.

kaze provides an API to describe Modules composed of Signals, which can then be used to generate Rust simulator code or Verilog modules.

kaze's API is designed to be as minimal as possible while still being expressive. It's designed to prevent the user from being able to describe buggy or incorrect hardware as much as possible. This enables a user to hack on designs fearlessly, while the API and generators ensure that these designs are sound.

Usage

[dependencies]
kaze = "0.1"

Examples

use kaze::*;

// Create a context, which will contain our module(s)
let c = Context::new();

// Create a module
let inverter = c.module("Inverter");
let i = inverter.input("i", 1); // 1-bit input
inverter.output("o", !i); // Output inverted input

// Generate Rust simulator code
sim::generate(inverter, sim::GenerationOptions::default(), std::io::stdout())?;

// Generate Verilog code
verilog::generate(inverter, std::io::stdout())?;

Modules

runtime	Rust simulator runtime dependencies. These are only required for simulators with tracing enabled.
sim	Rust simulator code generation.
verilog	Verilog code generation.

Structs

Context	A top-level container/owner object for a `Module` graph.
Instance	An instance of a `Module`, created by the `Module::instance` method.
Mem	A synchronous memory, created by the `Module::mem` method.
Module	A self-contained and potentially-reusable hardware design unit, created by the `Context::module` method.
Register	A hardware register, created by the `Module::reg` method.
Signal	A collection of 1 or more bits driven by some source.

Enums

Constant

A container for different types of integer constant values.

Constants

MAX_SIGNAL_BIT_WIDTH	The maximum allowed bit width for any given `Signal`.
MIN_SIGNAL_BIT_WIDTH	The minimum allowed bit width for any given `Signal`.

Functions

if_	UNSTABLE: Provides a convenient way to write conditional combinational logic.