k66/uart3/
c5.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u8,
8}
9impl super::C5 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `RDMAS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum RDMASR {
48    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDFR interrupt request signal is asserted to request an interrupt service."]
49    _0,
50    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDRF DMA request signal is asserted to request a DMA transfer."]
51    _1,
52}
53impl RDMASR {
54    #[doc = r" Returns `true` if the bit is clear (0)"]
55    #[inline]
56    pub fn bit_is_clear(&self) -> bool {
57        !self.bit()
58    }
59    #[doc = r" Returns `true` if the bit is set (1)"]
60    #[inline]
61    pub fn bit_is_set(&self) -> bool {
62        self.bit()
63    }
64    #[doc = r" Value of the field as raw bits"]
65    #[inline]
66    pub fn bit(&self) -> bool {
67        match *self {
68            RDMASR::_0 => false,
69            RDMASR::_1 => true,
70        }
71    }
72    #[allow(missing_docs)]
73    #[doc(hidden)]
74    #[inline]
75    pub fn _from(value: bool) -> RDMASR {
76        match value {
77            false => RDMASR::_0,
78            true => RDMASR::_1,
79        }
80    }
81    #[doc = "Checks if the value of the field is `_0`"]
82    #[inline]
83    pub fn is_0(&self) -> bool {
84        *self == RDMASR::_0
85    }
86    #[doc = "Checks if the value of the field is `_1`"]
87    #[inline]
88    pub fn is_1(&self) -> bool {
89        *self == RDMASR::_1
90    }
91}
92#[doc = "Possible values of the field `TDMAS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum TDMASR {
95    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE interrupt request signal is asserted to request interrupt service."]
96    _0,
97    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer."]
98    _1,
99}
100impl TDMASR {
101    #[doc = r" Returns `true` if the bit is clear (0)"]
102    #[inline]
103    pub fn bit_is_clear(&self) -> bool {
104        !self.bit()
105    }
106    #[doc = r" Returns `true` if the bit is set (1)"]
107    #[inline]
108    pub fn bit_is_set(&self) -> bool {
109        self.bit()
110    }
111    #[doc = r" Value of the field as raw bits"]
112    #[inline]
113    pub fn bit(&self) -> bool {
114        match *self {
115            TDMASR::_0 => false,
116            TDMASR::_1 => true,
117        }
118    }
119    #[allow(missing_docs)]
120    #[doc(hidden)]
121    #[inline]
122    pub fn _from(value: bool) -> TDMASR {
123        match value {
124            false => TDMASR::_0,
125            true => TDMASR::_1,
126        }
127    }
128    #[doc = "Checks if the value of the field is `_0`"]
129    #[inline]
130    pub fn is_0(&self) -> bool {
131        *self == TDMASR::_0
132    }
133    #[doc = "Checks if the value of the field is `_1`"]
134    #[inline]
135    pub fn is_1(&self) -> bool {
136        *self == TDMASR::_1
137    }
138}
139#[doc = "Values that can be written to the field `RDMAS`"]
140pub enum RDMASW {
141    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDFR interrupt request signal is asserted to request an interrupt service."]
142    _0,
143    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDRF DMA request signal is asserted to request a DMA transfer."]
144    _1,
145}
146impl RDMASW {
147    #[allow(missing_docs)]
148    #[doc(hidden)]
149    #[inline]
150    pub fn _bits(&self) -> bool {
151        match *self {
152            RDMASW::_0 => false,
153            RDMASW::_1 => true,
154        }
155    }
156}
157#[doc = r" Proxy"]
158pub struct _RDMASW<'a> {
159    w: &'a mut W,
160}
161impl<'a> _RDMASW<'a> {
162    #[doc = r" Writes `variant` to the field"]
163    #[inline]
164    pub fn variant(self, variant: RDMASW) -> &'a mut W {
165        {
166            self.bit(variant._bits())
167        }
168    }
169    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDFR interrupt request signal is asserted to request an interrupt service."]
170    #[inline]
171    pub fn _0(self) -> &'a mut W {
172        self.variant(RDMASW::_0)
173    }
174    #[doc = "If C2\\[RIE\\] and S1\\[RDRF\\] are set, the RDRF DMA request signal is asserted to request a DMA transfer."]
175    #[inline]
176    pub fn _1(self) -> &'a mut W {
177        self.variant(RDMASW::_1)
178    }
179    #[doc = r" Sets the field bit"]
180    pub fn set_bit(self) -> &'a mut W {
181        self.bit(true)
182    }
183    #[doc = r" Clears the field bit"]
184    pub fn clear_bit(self) -> &'a mut W {
185        self.bit(false)
186    }
187    #[doc = r" Writes raw bits to the field"]
188    #[inline]
189    pub fn bit(self, value: bool) -> &'a mut W {
190        const MASK: bool = true;
191        const OFFSET: u8 = 5;
192        self.w.bits &= !((MASK as u8) << OFFSET);
193        self.w.bits |= ((value & MASK) as u8) << OFFSET;
194        self.w
195    }
196}
197#[doc = "Values that can be written to the field `TDMAS`"]
198pub enum TDMASW {
199    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE interrupt request signal is asserted to request interrupt service."]
200    _0,
201    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer."]
202    _1,
203}
204impl TDMASW {
205    #[allow(missing_docs)]
206    #[doc(hidden)]
207    #[inline]
208    pub fn _bits(&self) -> bool {
209        match *self {
210            TDMASW::_0 => false,
211            TDMASW::_1 => true,
212        }
213    }
214}
215#[doc = r" Proxy"]
216pub struct _TDMASW<'a> {
217    w: &'a mut W,
218}
219impl<'a> _TDMASW<'a> {
220    #[doc = r" Writes `variant` to the field"]
221    #[inline]
222    pub fn variant(self, variant: TDMASW) -> &'a mut W {
223        {
224            self.bit(variant._bits())
225        }
226    }
227    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE interrupt request signal is asserted to request interrupt service."]
228    #[inline]
229    pub fn _0(self) -> &'a mut W {
230        self.variant(TDMASW::_0)
231    }
232    #[doc = "If C2\\[TIE\\] is set and the S1\\[TDRE\\] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer."]
233    #[inline]
234    pub fn _1(self) -> &'a mut W {
235        self.variant(TDMASW::_1)
236    }
237    #[doc = r" Sets the field bit"]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r" Clears the field bit"]
242    pub fn clear_bit(self) -> &'a mut W {
243        self.bit(false)
244    }
245    #[doc = r" Writes raw bits to the field"]
246    #[inline]
247    pub fn bit(self, value: bool) -> &'a mut W {
248        const MASK: bool = true;
249        const OFFSET: u8 = 7;
250        self.w.bits &= !((MASK as u8) << OFFSET);
251        self.w.bits |= ((value & MASK) as u8) << OFFSET;
252        self.w
253    }
254}
255impl R {
256    #[doc = r" Value of the register as raw bits"]
257    #[inline]
258    pub fn bits(&self) -> u8 {
259        self.bits
260    }
261    #[doc = "Bit 5 - Receiver Full DMA Select"]
262    #[inline]
263    pub fn rdmas(&self) -> RDMASR {
264        RDMASR::_from({
265            const MASK: bool = true;
266            const OFFSET: u8 = 5;
267            ((self.bits >> OFFSET) & MASK as u8) != 0
268        })
269    }
270    #[doc = "Bit 7 - Transmitter DMA Select"]
271    #[inline]
272    pub fn tdmas(&self) -> TDMASR {
273        TDMASR::_from({
274            const MASK: bool = true;
275            const OFFSET: u8 = 7;
276            ((self.bits >> OFFSET) & MASK as u8) != 0
277        })
278    }
279}
280impl W {
281    #[doc = r" Reset value of the register"]
282    #[inline]
283    pub fn reset_value() -> W {
284        W { bits: 0 }
285    }
286    #[doc = r" Writes raw bits to the register"]
287    #[inline]
288    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
289        self.bits = bits;
290        self
291    }
292    #[doc = "Bit 5 - Receiver Full DMA Select"]
293    #[inline]
294    pub fn rdmas(&mut self) -> _RDMASW {
295        _RDMASW { w: self }
296    }
297    #[doc = "Bit 7 - Transmitter DMA Select"]
298    #[inline]
299    pub fn tdmas(&mut self) -> _TDMASW {
300        _TDMASW { w: self }
301    }
302}